1/* 2 * linux/arch/arm/plat-omap/mcbsp.c 3 * 4 * Copyright (C) 2004 Nokia Corporation 5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> 6 * 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Multichannel mode not supported. 13 */ 14 15#include <linux/module.h> 16#include <linux/init.h> 17#include <linux/device.h> 18#include <linux/wait.h> 19#include <linux/completion.h> 20#include <linux/interrupt.h> 21#include <linux/err.h> 22#include <linux/clk.h> 23#include <linux/delay.h> 24 25#include <asm/io.h> 26#include <asm/irq.h> 27 28#include <asm/arch/dma.h> 29#include <asm/arch/mux.h> 30#include <asm/arch/irqs.h> 31#include <asm/arch/dsp_common.h> 32#include <asm/arch/mcbsp.h> 33 34#ifdef CONFIG_MCBSP_DEBUG 35#define DBG(x...) printk(x) 36#else 37#define DBG(x...) do { } while (0) 38#endif 39 40struct omap_mcbsp { 41 u32 io_base; 42 u8 id; 43 u8 free; 44 omap_mcbsp_word_length rx_word_length; 45 omap_mcbsp_word_length tx_word_length; 46 47 omap_mcbsp_io_type_t io_type; /* IRQ or poll */ 48 /* IRQ based TX/RX */ 49 int rx_irq; 50 int tx_irq; 51 52 /* DMA stuff */ 53 u8 dma_rx_sync; 54 short dma_rx_lch; 55 u8 dma_tx_sync; 56 short dma_tx_lch; 57 58 /* Completion queues */ 59 struct completion tx_irq_completion; 60 struct completion rx_irq_completion; 61 struct completion tx_dma_completion; 62 struct completion rx_dma_completion; 63 64 spinlock_t lock; 65}; 66 67static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT]; 68#ifdef CONFIG_ARCH_OMAP1 69static struct clk *mcbsp_dsp_ck = 0; 70static struct clk *mcbsp_api_ck = 0; 71static struct clk *mcbsp_dspxor_ck = 0; 72#endif 73#ifdef CONFIG_ARCH_OMAP2 74static struct clk *mcbsp1_ick = 0; 75static struct clk *mcbsp1_fck = 0; 76static struct clk *mcbsp2_ick = 0; 77static struct clk *mcbsp2_fck = 0; 78#endif 79 80static void omap_mcbsp_dump_reg(u8 id) 81{ 82 DBG("**** MCBSP%d regs ****\n", mcbsp[id].id); 83 DBG("DRR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2)); 84 DBG("DRR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1)); 85 DBG("DXR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2)); 86 DBG("DXR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1)); 87 DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2)); 88 DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1)); 89 DBG("RCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2)); 90 DBG("RCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1)); 91 DBG("XCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2)); 92 DBG("XCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1)); 93 DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2)); 94 DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1)); 95 DBG("PCR0: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0)); 96 DBG("***********************\n"); 97} 98 99static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id) 100{ 101 struct omap_mcbsp * mcbsp_tx = (struct omap_mcbsp *)(dev_id); 102 103 DBG("TX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2)); 104 105 complete(&mcbsp_tx->tx_irq_completion); 106 return IRQ_HANDLED; 107} 108 109static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id) 110{ 111 struct omap_mcbsp * mcbsp_rx = (struct omap_mcbsp *)(dev_id); 112 113 DBG("RX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2)); 114 115 complete(&mcbsp_rx->rx_irq_completion); 116 return IRQ_HANDLED; 117} 118 119static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data) 120{ 121 struct omap_mcbsp * mcbsp_dma_tx = (struct omap_mcbsp *)(data); 122 123 DBG("TX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2)); 124 125 /* We can free the channels */ 126 omap_free_dma(mcbsp_dma_tx->dma_tx_lch); 127 mcbsp_dma_tx->dma_tx_lch = -1; 128 129 complete(&mcbsp_dma_tx->tx_dma_completion); 130} 131 132static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data) 133{ 134 struct omap_mcbsp * mcbsp_dma_rx = (struct omap_mcbsp *)(data); 135 136 DBG("RX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2)); 137 138 /* We can free the channels */ 139 omap_free_dma(mcbsp_dma_rx->dma_rx_lch); 140 mcbsp_dma_rx->dma_rx_lch = -1; 141 142 complete(&mcbsp_dma_rx->rx_dma_completion); 143} 144 145 146/* 147 * omap_mcbsp_config simply write a config to the 148 * appropriate McBSP. 149 * You either call this function or set the McBSP registers 150 * by yourself before calling omap_mcbsp_start(). 151 */ 152 153void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config) 154{ 155 u32 io_base = mcbsp[id].io_base; 156 157 DBG("OMAP-McBSP: McBSP%d io_base: 0x%8x\n", id+1, io_base); 158 159 /* We write the given config */ 160 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2); 161 OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1); 162 OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2); 163 OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1); 164 OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2); 165 OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1); 166 OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2); 167 OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1); 168 OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2); 169 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1); 170 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0); 171} 172 173 174 175static int omap_mcbsp_check(unsigned int id) 176{ 177 if (cpu_is_omap730()) { 178 if (id > OMAP_MAX_MCBSP_COUNT - 1) { 179 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1); 180 return -1; 181 } 182 return 0; 183 } 184 185 if (cpu_is_omap15xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) { 186 if (id > OMAP_MAX_MCBSP_COUNT) { 187 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1); 188 return -1; 189 } 190 return 0; 191 } 192 193 return -1; 194} 195 196#ifdef CONFIG_ARCH_OMAP1 197static void omap_mcbsp_dsp_request(void) 198{ 199 if (cpu_is_omap15xx() || cpu_is_omap16xx()) { 200 clk_enable(mcbsp_dsp_ck); 201 clk_enable(mcbsp_api_ck); 202 203 /* enable 12MHz clock to mcbsp 1 & 3 */ 204 clk_enable(mcbsp_dspxor_ck); 205 206 __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1, 207 DSP_RSTCT2); 208 } 209} 210 211static void omap_mcbsp_dsp_free(void) 212{ 213 if (cpu_is_omap15xx() || cpu_is_omap16xx()) { 214 clk_disable(mcbsp_dspxor_ck); 215 clk_disable(mcbsp_dsp_ck); 216 clk_disable(mcbsp_api_ck); 217 } 218} 219#endif 220 221#ifdef CONFIG_ARCH_OMAP2 222static void omap2_mcbsp2_mux_setup(void) 223{ 224 if (cpu_is_omap2420()) { 225 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX); 226 omap_cfg_reg(R14_24XX_MCBSP2_FSX); 227 omap_cfg_reg(W15_24XX_MCBSP2_DR); 228 omap_cfg_reg(V15_24XX_MCBSP2_DX); 229 omap_cfg_reg(V14_24XX_GPIO117); 230 } 231 /* 232 * Need to add MUX settings for OMAP 2430 SDP 233 */ 234} 235#endif 236 237/* 238 * We can choose between IRQ based or polled IO. 239 * This needs to be called before omap_mcbsp_request(). 240 */ 241int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type) 242{ 243 if (omap_mcbsp_check(id) < 0) 244 return -EINVAL; 245 246 spin_lock(&mcbsp[id].lock); 247 248 if (!mcbsp[id].free) { 249 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1); 250 spin_unlock(&mcbsp[id].lock); 251 return -EINVAL; 252 } 253 254 mcbsp[id].io_type = io_type; 255 256 spin_unlock(&mcbsp[id].lock); 257 258 return 0; 259} 260 261int omap_mcbsp_request(unsigned int id) 262{ 263 int err; 264 265 if (omap_mcbsp_check(id) < 0) 266 return -EINVAL; 267 268#ifdef CONFIG_ARCH_OMAP1 269 /* 270 * On 1510, 1610 and 1710, McBSP1 and McBSP3 271 * are DSP public peripherals. 272 */ 273 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) 274 omap_mcbsp_dsp_request(); 275#endif 276 277#ifdef CONFIG_ARCH_OMAP2 278 if (cpu_is_omap24xx()) { 279 if (id == OMAP_MCBSP1) { 280 clk_enable(mcbsp1_ick); 281 clk_enable(mcbsp1_fck); 282 } else { 283 clk_enable(mcbsp2_ick); 284 clk_enable(mcbsp2_fck); 285 } 286 } 287#endif 288 289 spin_lock(&mcbsp[id].lock); 290 if (!mcbsp[id].free) { 291 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1); 292 spin_unlock(&mcbsp[id].lock); 293 return -1; 294 } 295 296 mcbsp[id].free = 0; 297 spin_unlock(&mcbsp[id].lock); 298 299 if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) { 300 /* We need to get IRQs here */ 301 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0, 302 "McBSP", 303 (void *) (&mcbsp[id])); 304 if (err != 0) { 305 printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for McBSP%d\n", 306 mcbsp[id].tx_irq, mcbsp[id].id); 307 return err; 308 } 309 310 init_completion(&(mcbsp[id].tx_irq_completion)); 311 312 313 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0, 314 "McBSP", 315 (void *) (&mcbsp[id])); 316 if (err != 0) { 317 printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for McBSP%d\n", 318 mcbsp[id].rx_irq, mcbsp[id].id); 319 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id])); 320 return err; 321 } 322 323 init_completion(&(mcbsp[id].rx_irq_completion)); 324 } 325 326 return 0; 327 328} 329 330void omap_mcbsp_free(unsigned int id) 331{ 332 if (omap_mcbsp_check(id) < 0) 333 return; 334 335#ifdef CONFIG_ARCH_OMAP1 336 if (cpu_class_is_omap1()) { 337 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) 338 omap_mcbsp_dsp_free(); 339 } 340#endif 341 342#ifdef CONFIG_ARCH_OMAP2 343 if (cpu_is_omap24xx()) { 344 if (id == OMAP_MCBSP1) { 345 clk_disable(mcbsp1_ick); 346 clk_disable(mcbsp1_fck); 347 } else { 348 clk_disable(mcbsp2_ick); 349 clk_disable(mcbsp2_fck); 350 } 351 } 352#endif 353 354 spin_lock(&mcbsp[id].lock); 355 if (mcbsp[id].free) { 356 printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 1); 357 spin_unlock(&mcbsp[id].lock); 358 return; 359 } 360 361 mcbsp[id].free = 1; 362 spin_unlock(&mcbsp[id].lock); 363 364 if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) { 365 /* Free IRQs */ 366 free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id])); 367 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id])); 368 } 369} 370 371/* 372 * Here we start the McBSP, by enabling the sample 373 * generator, both transmitter and receivers, 374 * and the frame sync. 375 */ 376void omap_mcbsp_start(unsigned int id) 377{ 378 u32 io_base; 379 u16 w; 380 381 if (omap_mcbsp_check(id) < 0) 382 return; 383 384 io_base = mcbsp[id].io_base; 385 386 mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7); 387 mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7); 388 389 /* Start the sample generator */ 390 w = OMAP_MCBSP_READ(io_base, SPCR2); 391 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6)); 392 393 /* Enable transmitter and receiver */ 394 w = OMAP_MCBSP_READ(io_base, SPCR2); 395 OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1); 396 397 w = OMAP_MCBSP_READ(io_base, SPCR1); 398 OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1); 399 400 udelay(100); 401 402 /* Start frame sync */ 403 w = OMAP_MCBSP_READ(io_base, SPCR2); 404 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7)); 405 406 /* Dump McBSP Regs */ 407 omap_mcbsp_dump_reg(id); 408 409} 410 411void omap_mcbsp_stop(unsigned int id) 412{ 413 u32 io_base; 414 u16 w; 415 416 if (omap_mcbsp_check(id) < 0) 417 return; 418 419 io_base = mcbsp[id].io_base; 420 421 /* Reset transmitter */ 422 w = OMAP_MCBSP_READ(io_base, SPCR2); 423 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1)); 424 425 /* Reset receiver */ 426 w = OMAP_MCBSP_READ(io_base, SPCR1); 427 OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1)); 428 429 /* Reset the sample rate generator */ 430 w = OMAP_MCBSP_READ(io_base, SPCR2); 431 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6)); 432} 433 434 435/* polled mcbsp i/o operations */ 436int omap_mcbsp_pollwrite(unsigned int id, u16 buf) 437{ 438 u32 base = mcbsp[id].io_base; 439 writew(buf, base + OMAP_MCBSP_REG_DXR1); 440 /* if frame sync error - clear the error */ 441 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) { 442 /* clear error */ 443 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR), 444 base + OMAP_MCBSP_REG_SPCR2); 445 /* resend */ 446 return -1; 447 } else { 448 /* wait for transmit confirmation */ 449 int attemps = 0; 450 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) { 451 if (attemps++ > 1000) { 452 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & 453 (~XRST), 454 base + OMAP_MCBSP_REG_SPCR2); 455 udelay(10); 456 writew(readw(base + OMAP_MCBSP_REG_SPCR2) | 457 (XRST), 458 base + OMAP_MCBSP_REG_SPCR2); 459 udelay(10); 460 printk(KERN_ERR 461 " Could not write to McBSP Register\n"); 462 return -2; 463 } 464 } 465 } 466 return 0; 467} 468 469int omap_mcbsp_pollread(unsigned int id, u16 * buf) 470{ 471 u32 base = mcbsp[id].io_base; 472 /* if frame sync error - clear the error */ 473 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) { 474 /* clear error */ 475 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR), 476 base + OMAP_MCBSP_REG_SPCR1); 477 /* resend */ 478 return -1; 479 } else { 480 /* wait for recieve confirmation */ 481 int attemps = 0; 482 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) { 483 if (attemps++ > 1000) { 484 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & 485 (~RRST), 486 base + OMAP_MCBSP_REG_SPCR1); 487 udelay(10); 488 writew(readw(base + OMAP_MCBSP_REG_SPCR1) | 489 (RRST), 490 base + OMAP_MCBSP_REG_SPCR1); 491 udelay(10); 492 printk(KERN_ERR 493 " Could not read from McBSP Register\n"); 494 return -2; 495 } 496 } 497 } 498 *buf = readw(base + OMAP_MCBSP_REG_DRR1); 499 return 0; 500} 501 502/* 503 * IRQ based word transmission. 504 */ 505void omap_mcbsp_xmit_word(unsigned int id, u32 word) 506{ 507 u32 io_base; 508 omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length; 509 510 if (omap_mcbsp_check(id) < 0) 511 return; 512 513 io_base = mcbsp[id].io_base; 514 515 wait_for_completion(&(mcbsp[id].tx_irq_completion)); 516 517 if (word_length > OMAP_MCBSP_WORD_16) 518 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16); 519 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff); 520} 521 522u32 omap_mcbsp_recv_word(unsigned int id) 523{ 524 u32 io_base; 525 u16 word_lsb, word_msb = 0; 526 omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length; 527 528 if (omap_mcbsp_check(id) < 0) 529 return -EINVAL; 530 531 io_base = mcbsp[id].io_base; 532 533 wait_for_completion(&(mcbsp[id].rx_irq_completion)); 534 535 if (word_length > OMAP_MCBSP_WORD_16) 536 word_msb = OMAP_MCBSP_READ(io_base, DRR2); 537 word_lsb = OMAP_MCBSP_READ(io_base, DRR1); 538 539 return (word_lsb | (word_msb << 16)); 540} 541 542 543int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) 544{ 545 u32 io_base = mcbsp[id].io_base; 546 omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length; 547 omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length; 548 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; 549 550 if (tx_word_length != rx_word_length) 551 return -EINVAL; 552 553 /* First we wait for the transmitter to be ready */ 554 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2); 555 while (!(spcr2 & XRDY)) { 556 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2); 557 if (attempts++ > 1000) { 558 /* We must reset the transmitter */ 559 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST)); 560 udelay(10); 561 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); 562 udelay(10); 563 printk("McBSP transmitter not ready\n"); 564 return -EAGAIN; 565 } 566 } 567 568 /* Now we can push the data */ 569 if (tx_word_length > OMAP_MCBSP_WORD_16) 570 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16); 571 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff); 572 573 /* We wait for the receiver to be ready */ 574 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1); 575 while (!(spcr1 & RRDY)) { 576 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1); 577 if (attempts++ > 1000) { 578 /* We must reset the receiver */ 579 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST)); 580 udelay(10); 581 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); 582 udelay(10); 583 printk("McBSP receiver not ready\n"); 584 return -EAGAIN; 585 } 586 } 587 588 /* Receiver is ready, let's read the dummy data */ 589 if (rx_word_length > OMAP_MCBSP_WORD_16) 590 word_msb = OMAP_MCBSP_READ(io_base, DRR2); 591 word_lsb = OMAP_MCBSP_READ(io_base, DRR1); 592 593 return 0; 594} 595 596int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word) 597{ 598 u32 io_base = mcbsp[id].io_base, clock_word = 0; 599 omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length; 600 omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length; 601 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; 602 603 if (tx_word_length != rx_word_length) 604 return -EINVAL; 605 606 /* First we wait for the transmitter to be ready */ 607 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2); 608 while (!(spcr2 & XRDY)) { 609 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2); 610 if (attempts++ > 1000) { 611 /* We must reset the transmitter */ 612 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST)); 613 udelay(10); 614 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); 615 udelay(10); 616 printk("McBSP transmitter not ready\n"); 617 return -EAGAIN; 618 } 619 } 620 621 /* We first need to enable the bus clock */ 622 if (tx_word_length > OMAP_MCBSP_WORD_16) 623 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16); 624 OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff); 625 626 /* We wait for the receiver to be ready */ 627 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1); 628 while (!(spcr1 & RRDY)) { 629 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1); 630 if (attempts++ > 1000) { 631 /* We must reset the receiver */ 632 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST)); 633 udelay(10); 634 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); 635 udelay(10); 636 printk("McBSP receiver not ready\n"); 637 return -EAGAIN; 638 } 639 } 640 641 /* Receiver is ready, there is something for us */ 642 if (rx_word_length > OMAP_MCBSP_WORD_16) 643 word_msb = OMAP_MCBSP_READ(io_base, DRR2); 644 word_lsb = OMAP_MCBSP_READ(io_base, DRR1); 645 646 word[0] = (word_lsb | (word_msb << 16)); 647 648 return 0; 649} 650 651 652/* 653 * Simple DMA based buffer rx/tx routines. 654 * Nothing fancy, just a single buffer tx/rx through DMA. 655 * The DMA resources are released once the transfer is done. 656 * For anything fancier, you should use your own customized DMA 657 * routines and callbacks. 658 */ 659int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length) 660{ 661 int dma_tx_ch; 662 int src_port = 0; 663 int dest_port = 0; 664 int sync_dev = 0; 665 666 if (omap_mcbsp_check(id) < 0) 667 return -EINVAL; 668 669 if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", omap_mcbsp_tx_dma_callback, 670 &mcbsp[id], 671 &dma_tx_ch)) { 672 printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d TX. Trying IRQ based TX\n", id+1); 673 return -EAGAIN; 674 } 675 mcbsp[id].dma_tx_lch = dma_tx_ch; 676 677 DBG("TX DMA on channel %d\n", dma_tx_ch); 678 679 init_completion(&(mcbsp[id].tx_dma_completion)); 680 681 if (cpu_class_is_omap1()) { 682 src_port = OMAP_DMA_PORT_TIPB; 683 dest_port = OMAP_DMA_PORT_EMIFF; 684 } 685 if (cpu_is_omap24xx()) 686 sync_dev = mcbsp[id].dma_tx_sync; 687 688 omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch, 689 OMAP_DMA_DATA_TYPE_S16, 690 length >> 1, 1, 691 OMAP_DMA_SYNC_ELEMENT, 692 sync_dev, 0); 693 694 omap_set_dma_dest_params(mcbsp[id].dma_tx_lch, 695 src_port, 696 OMAP_DMA_AMODE_CONSTANT, 697 mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1, 698 0, 0); 699 700 omap_set_dma_src_params(mcbsp[id].dma_tx_lch, 701 dest_port, 702 OMAP_DMA_AMODE_POST_INC, 703 buffer, 704 0, 0); 705 706 omap_start_dma(mcbsp[id].dma_tx_lch); 707 wait_for_completion(&(mcbsp[id].tx_dma_completion)); 708 return 0; 709} 710 711 712int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length) 713{ 714 int dma_rx_ch; 715 int src_port = 0; 716 int dest_port = 0; 717 int sync_dev = 0; 718 719 if (omap_mcbsp_check(id) < 0) 720 return -EINVAL; 721 722 if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", omap_mcbsp_rx_dma_callback, 723 &mcbsp[id], 724 &dma_rx_ch)) { 725 printk("Unable to request DMA channel for McBSP%d RX. Trying IRQ based RX\n", id+1); 726 return -EAGAIN; 727 } 728 mcbsp[id].dma_rx_lch = dma_rx_ch; 729 730 DBG("RX DMA on channel %d\n", dma_rx_ch); 731 732 init_completion(&(mcbsp[id].rx_dma_completion)); 733 734 if (cpu_class_is_omap1()) { 735 src_port = OMAP_DMA_PORT_TIPB; 736 dest_port = OMAP_DMA_PORT_EMIFF; 737 } 738 if (cpu_is_omap24xx()) 739 sync_dev = mcbsp[id].dma_rx_sync; 740 741 omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch, 742 OMAP_DMA_DATA_TYPE_S16, 743 length >> 1, 1, 744 OMAP_DMA_SYNC_ELEMENT, 745 sync_dev, 0); 746 747 omap_set_dma_src_params(mcbsp[id].dma_rx_lch, 748 src_port, 749 OMAP_DMA_AMODE_CONSTANT, 750 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1, 751 0, 0); 752 753 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch, 754 dest_port, 755 OMAP_DMA_AMODE_POST_INC, 756 buffer, 757 0, 0); 758 759 omap_start_dma(mcbsp[id].dma_rx_lch); 760 wait_for_completion(&(mcbsp[id].rx_dma_completion)); 761 return 0; 762} 763 764 765/* 766 * SPI wrapper. 767 * Since SPI setup is much simpler than the generic McBSP one, 768 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input. 769 * Once this is done, you can call omap_mcbsp_start(). 770 */ 771void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg) 772{ 773 struct omap_mcbsp_reg_cfg mcbsp_cfg; 774 775 if (omap_mcbsp_check(id) < 0) 776 return; 777 778 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg)); 779 780 /* SPI has only one frame */ 781 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0)); 782 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0)); 783 784 /* Clock stop mode */ 785 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY) 786 mcbsp_cfg.spcr1 |= (1 << 12); 787 else 788 mcbsp_cfg.spcr1 |= (3 << 11); 789 790 /* Set clock parities */ 791 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING) 792 mcbsp_cfg.pcr0 |= CLKRP; 793 else 794 mcbsp_cfg.pcr0 &= ~CLKRP; 795 796 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING) 797 mcbsp_cfg.pcr0 &= ~CLKXP; 798 else 799 mcbsp_cfg.pcr0 |= CLKXP; 800 801 /* Set SCLKME to 0 and CLKSM to 1 */ 802 mcbsp_cfg.pcr0 &= ~SCLKME; 803 mcbsp_cfg.srgr2 |= CLKSM; 804 805 /* Set FSXP */ 806 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH) 807 mcbsp_cfg.pcr0 &= ~FSXP; 808 else 809 mcbsp_cfg.pcr0 |= FSXP; 810 811 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) { 812 mcbsp_cfg.pcr0 |= CLKXM; 813 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1); 814 mcbsp_cfg.pcr0 |= FSXM; 815 mcbsp_cfg.srgr2 &= ~FSGM; 816 mcbsp_cfg.xcr2 |= XDATDLY(1); 817 mcbsp_cfg.rcr2 |= RDATDLY(1); 818 } 819 else { 820 mcbsp_cfg.pcr0 &= ~CLKXM; 821 mcbsp_cfg.srgr1 |= CLKGDV(1); 822 mcbsp_cfg.pcr0 &= ~FSXM; 823 mcbsp_cfg.xcr2 &= ~XDATDLY(3); 824 mcbsp_cfg.rcr2 &= ~RDATDLY(3); 825 } 826 827 mcbsp_cfg.xcr2 &= ~XPHASE; 828 mcbsp_cfg.rcr2 &= ~RPHASE; 829 830 omap_mcbsp_config(id, &mcbsp_cfg); 831} 832 833 834/* 835 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. 836 * 730 has only 2 McBSP, and both of them are MPU peripherals. 837 */ 838struct omap_mcbsp_info { 839 u32 virt_base; 840 u8 dma_rx_sync, dma_tx_sync; 841 u16 rx_irq, tx_irq; 842}; 843 844#ifdef CONFIG_ARCH_OMAP730 845static const struct omap_mcbsp_info mcbsp_730[] = { 846 [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE), 847 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 848 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 849 .rx_irq = INT_730_McBSP1RX, 850 .tx_irq = INT_730_McBSP1TX }, 851 [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE), 852 .dma_rx_sync = OMAP_DMA_MCBSP3_RX, 853 .dma_tx_sync = OMAP_DMA_MCBSP3_TX, 854 .rx_irq = INT_730_McBSP2RX, 855 .tx_irq = INT_730_McBSP2TX }, 856}; 857#endif 858 859#ifdef CONFIG_ARCH_OMAP15XX 860static const struct omap_mcbsp_info mcbsp_1510[] = { 861 [0] = { .virt_base = OMAP1510_MCBSP1_BASE, 862 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 863 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 864 .rx_irq = INT_McBSP1RX, 865 .tx_irq = INT_McBSP1TX }, 866 [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE), 867 .dma_rx_sync = OMAP_DMA_MCBSP2_RX, 868 .dma_tx_sync = OMAP_DMA_MCBSP2_TX, 869 .rx_irq = INT_1510_SPI_RX, 870 .tx_irq = INT_1510_SPI_TX }, 871 [2] = { .virt_base = OMAP1510_MCBSP3_BASE, 872 .dma_rx_sync = OMAP_DMA_MCBSP3_RX, 873 .dma_tx_sync = OMAP_DMA_MCBSP3_TX, 874 .rx_irq = INT_McBSP3RX, 875 .tx_irq = INT_McBSP3TX }, 876}; 877#endif 878 879#if defined(CONFIG_ARCH_OMAP16XX) 880static const struct omap_mcbsp_info mcbsp_1610[] = { 881 [0] = { .virt_base = OMAP1610_MCBSP1_BASE, 882 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 883 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 884 .rx_irq = INT_McBSP1RX, 885 .tx_irq = INT_McBSP1TX }, 886 [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE), 887 .dma_rx_sync = OMAP_DMA_MCBSP2_RX, 888 .dma_tx_sync = OMAP_DMA_MCBSP2_TX, 889 .rx_irq = INT_1610_McBSP2_RX, 890 .tx_irq = INT_1610_McBSP2_TX }, 891 [2] = { .virt_base = OMAP1610_MCBSP3_BASE, 892 .dma_rx_sync = OMAP_DMA_MCBSP3_RX, 893 .dma_tx_sync = OMAP_DMA_MCBSP3_TX, 894 .rx_irq = INT_McBSP3RX, 895 .tx_irq = INT_McBSP3TX }, 896}; 897#endif 898 899#if defined(CONFIG_ARCH_OMAP24XX) 900static const struct omap_mcbsp_info mcbsp_24xx[] = { 901 [0] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE), 902 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, 903 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 904 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 905 .tx_irq = INT_24XX_MCBSP1_IRQ_TX, 906 }, 907 [1] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE), 908 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, 909 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, 910 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 911 .tx_irq = INT_24XX_MCBSP2_IRQ_TX, 912 }, 913}; 914#endif 915 916static int __init omap_mcbsp_init(void) 917{ 918 int mcbsp_count = 0, i; 919 static const struct omap_mcbsp_info *mcbsp_info; 920 921 printk("Initializing OMAP McBSP system\n"); 922 923#ifdef CONFIG_ARCH_OMAP1 924 mcbsp_dsp_ck = clk_get(0, "dsp_ck"); 925 if (IS_ERR(mcbsp_dsp_ck)) { 926 printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n"); 927 return PTR_ERR(mcbsp_dsp_ck); 928 } 929 mcbsp_api_ck = clk_get(0, "api_ck"); 930 if (IS_ERR(mcbsp_api_ck)) { 931 printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n"); 932 return PTR_ERR(mcbsp_api_ck); 933 } 934 mcbsp_dspxor_ck = clk_get(0, "dspxor_ck"); 935 if (IS_ERR(mcbsp_dspxor_ck)) { 936 printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n"); 937 return PTR_ERR(mcbsp_dspxor_ck); 938 } 939#endif 940#ifdef CONFIG_ARCH_OMAP2 941 mcbsp1_ick = clk_get(0, "mcbsp1_ick"); 942 if (IS_ERR(mcbsp1_ick)) { 943 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_ick handle.\n"); 944 return PTR_ERR(mcbsp1_ick); 945 } 946 mcbsp1_fck = clk_get(0, "mcbsp1_fck"); 947 if (IS_ERR(mcbsp1_fck)) { 948 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_fck handle.\n"); 949 return PTR_ERR(mcbsp1_fck); 950 } 951 mcbsp2_ick = clk_get(0, "mcbsp2_ick"); 952 if (IS_ERR(mcbsp2_ick)) { 953 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_ick handle.\n"); 954 return PTR_ERR(mcbsp2_ick); 955 } 956 mcbsp2_fck = clk_get(0, "mcbsp2_fck"); 957 if (IS_ERR(mcbsp2_fck)) { 958 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_fck handle.\n"); 959 return PTR_ERR(mcbsp2_fck); 960 } 961#endif 962 963#ifdef CONFIG_ARCH_OMAP730 964 if (cpu_is_omap730()) { 965 mcbsp_info = mcbsp_730; 966 mcbsp_count = ARRAY_SIZE(mcbsp_730); 967 } 968#endif 969#ifdef CONFIG_ARCH_OMAP15XX 970 if (cpu_is_omap15xx()) { 971 mcbsp_info = mcbsp_1510; 972 mcbsp_count = ARRAY_SIZE(mcbsp_1510); 973 } 974#endif 975#if defined(CONFIG_ARCH_OMAP16XX) 976 if (cpu_is_omap16xx()) { 977 mcbsp_info = mcbsp_1610; 978 mcbsp_count = ARRAY_SIZE(mcbsp_1610); 979 } 980#endif 981#if defined(CONFIG_ARCH_OMAP24XX) 982 if (cpu_is_omap24xx()) { 983 mcbsp_info = mcbsp_24xx; 984 mcbsp_count = ARRAY_SIZE(mcbsp_24xx); 985 omap2_mcbsp2_mux_setup(); 986 } 987#endif 988 for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) { 989 if (i >= mcbsp_count) { 990 mcbsp[i].io_base = 0; 991 mcbsp[i].free = 0; 992 continue; 993 } 994 mcbsp[i].id = i + 1; 995 mcbsp[i].free = 1; 996 mcbsp[i].dma_tx_lch = -1; 997 mcbsp[i].dma_rx_lch = -1; 998 999 mcbsp[i].io_base = mcbsp_info[i].virt_base; 1000 mcbsp[i].io_type = OMAP_MCBSP_IRQ_IO; /* Default I/O is IRQ based */ 1001 mcbsp[i].tx_irq = mcbsp_info[i].tx_irq; 1002 mcbsp[i].rx_irq = mcbsp_info[i].rx_irq; 1003 mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync; 1004 mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync; 1005 spin_lock_init(&mcbsp[i].lock); 1006 } 1007 1008 return 0; 1009} 1010 1011arch_initcall(omap_mcbsp_init); 1012 1013EXPORT_SYMBOL(omap_mcbsp_config); 1014EXPORT_SYMBOL(omap_mcbsp_request); 1015EXPORT_SYMBOL(omap_mcbsp_set_io_type); 1016EXPORT_SYMBOL(omap_mcbsp_free); 1017EXPORT_SYMBOL(omap_mcbsp_start); 1018EXPORT_SYMBOL(omap_mcbsp_stop); 1019EXPORT_SYMBOL(omap_mcbsp_xmit_word); 1020EXPORT_SYMBOL(omap_mcbsp_recv_word); 1021EXPORT_SYMBOL(omap_mcbsp_xmit_buffer); 1022EXPORT_SYMBOL(omap_mcbsp_recv_buffer); 1023EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll); 1024EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll); 1025EXPORT_SYMBOL(omap_mcbsp_set_spi_mode); 1026