1/* 2 * linux/arch/arm/plat-omap/gpio.c 3 * 4 * Support functions for OMAP GPIO 5 * 6 * Copyright (C) 2003-2005 Nokia Corporation 7 * Written by Juha Yrj�l� <juha.yrjola@nokia.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14#include <linux/init.h> 15#include <linux/module.h> 16#include <linux/interrupt.h> 17#include <linux/sysdev.h> 18#include <linux/err.h> 19#include <linux/clk.h> 20 21#include <asm/hardware.h> 22#include <asm/irq.h> 23#include <asm/arch/irqs.h> 24#include <asm/arch/gpio.h> 25#include <asm/mach/irq.h> 26 27#include <asm/io.h> 28 29/* 30 * OMAP1510 GPIO registers 31 */ 32#define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000 33#define OMAP1510_GPIO_DATA_INPUT 0x00 34#define OMAP1510_GPIO_DATA_OUTPUT 0x04 35#define OMAP1510_GPIO_DIR_CONTROL 0x08 36#define OMAP1510_GPIO_INT_CONTROL 0x0c 37#define OMAP1510_GPIO_INT_MASK 0x10 38#define OMAP1510_GPIO_INT_STATUS 0x14 39#define OMAP1510_GPIO_PIN_CONTROL 0x18 40 41#define OMAP1510_IH_GPIO_BASE 64 42 43/* 44 * OMAP1610 specific GPIO registers 45 */ 46#define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400 47#define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00 48#define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400 49#define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00 50#define OMAP1610_GPIO_REVISION 0x0000 51#define OMAP1610_GPIO_SYSCONFIG 0x0010 52#define OMAP1610_GPIO_SYSSTATUS 0x0014 53#define OMAP1610_GPIO_IRQSTATUS1 0x0018 54#define OMAP1610_GPIO_IRQENABLE1 0x001c 55#define OMAP1610_GPIO_WAKEUPENABLE 0x0028 56#define OMAP1610_GPIO_DATAIN 0x002c 57#define OMAP1610_GPIO_DATAOUT 0x0030 58#define OMAP1610_GPIO_DIRECTION 0x0034 59#define OMAP1610_GPIO_EDGE_CTRL1 0x0038 60#define OMAP1610_GPIO_EDGE_CTRL2 0x003c 61#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c 62#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 63#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 64#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc 65#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 66#define OMAP1610_GPIO_SET_DATAOUT 0x00f0 67 68/* 69 * OMAP730 specific GPIO registers 70 */ 71#define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000 72#define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800 73#define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000 74#define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800 75#define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000 76#define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800 77#define OMAP730_GPIO_DATA_INPUT 0x00 78#define OMAP730_GPIO_DATA_OUTPUT 0x04 79#define OMAP730_GPIO_DIR_CONTROL 0x08 80#define OMAP730_GPIO_INT_CONTROL 0x0c 81#define OMAP730_GPIO_INT_MASK 0x10 82#define OMAP730_GPIO_INT_STATUS 0x14 83 84/* 85 * omap24xx specific GPIO registers 86 */ 87#define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000 88#define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000 89#define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000 90#define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000 91 92#define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000 93#define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000 94#define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000 95#define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000 96#define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000 97 98#define OMAP24XX_GPIO_REVISION 0x0000 99#define OMAP24XX_GPIO_SYSCONFIG 0x0010 100#define OMAP24XX_GPIO_SYSSTATUS 0x0014 101#define OMAP24XX_GPIO_IRQSTATUS1 0x0018 102#define OMAP24XX_GPIO_IRQSTATUS2 0x0028 103#define OMAP24XX_GPIO_IRQENABLE2 0x002c 104#define OMAP24XX_GPIO_IRQENABLE1 0x001c 105#define OMAP24XX_GPIO_CTRL 0x0030 106#define OMAP24XX_GPIO_OE 0x0034 107#define OMAP24XX_GPIO_DATAIN 0x0038 108#define OMAP24XX_GPIO_DATAOUT 0x003c 109#define OMAP24XX_GPIO_LEVELDETECT0 0x0040 110#define OMAP24XX_GPIO_LEVELDETECT1 0x0044 111#define OMAP24XX_GPIO_RISINGDETECT 0x0048 112#define OMAP24XX_GPIO_FALLINGDETECT 0x004c 113#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 114#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 115#define OMAP24XX_GPIO_CLEARWKUENA 0x0080 116#define OMAP24XX_GPIO_SETWKUENA 0x0084 117#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 118#define OMAP24XX_GPIO_SETDATAOUT 0x0094 119 120struct gpio_bank { 121 void __iomem *base; 122 u16 irq; 123 u16 virtual_irq_start; 124 int method; 125 u32 reserved_map; 126#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) 127 u32 suspend_wakeup; 128 u32 saved_wakeup; 129#endif 130#ifdef CONFIG_ARCH_OMAP24XX 131 u32 non_wakeup_gpios; 132 u32 enabled_non_wakeup_gpios; 133 134 u32 saved_datain; 135 u32 saved_fallingdetect; 136 u32 saved_risingdetect; 137#endif 138 spinlock_t lock; 139}; 140 141#define METHOD_MPUIO 0 142#define METHOD_GPIO_1510 1 143#define METHOD_GPIO_1610 2 144#define METHOD_GPIO_730 3 145#define METHOD_GPIO_24XX 4 146 147#ifdef CONFIG_ARCH_OMAP16XX 148static struct gpio_bank gpio_bank_1610[5] = { 149 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, 150 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, 151 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, 152 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, 153 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 }, 154}; 155#endif 156 157#ifdef CONFIG_ARCH_OMAP15XX 158static struct gpio_bank gpio_bank_1510[2] = { 159 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 160 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } 161}; 162#endif 163 164#ifdef CONFIG_ARCH_OMAP730 165static struct gpio_bank gpio_bank_730[7] = { 166 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 167 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, 168 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, 169 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, 170 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 }, 171 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 }, 172 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 }, 173}; 174#endif 175 176#ifdef CONFIG_ARCH_OMAP24XX 177 178static struct gpio_bank gpio_bank_242x[4] = { 179 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, 180 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, 181 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, 182 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, 183}; 184 185static struct gpio_bank gpio_bank_243x[5] = { 186 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, 187 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, 188 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, 189 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, 190 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, 191}; 192 193#endif 194 195static struct gpio_bank *gpio_bank; 196static int gpio_bank_count; 197 198static inline struct gpio_bank *get_gpio_bank(int gpio) 199{ 200#ifdef CONFIG_ARCH_OMAP15XX 201 if (cpu_is_omap15xx()) { 202 if (OMAP_GPIO_IS_MPUIO(gpio)) 203 return &gpio_bank[0]; 204 return &gpio_bank[1]; 205 } 206#endif 207#if defined(CONFIG_ARCH_OMAP16XX) 208 if (cpu_is_omap16xx()) { 209 if (OMAP_GPIO_IS_MPUIO(gpio)) 210 return &gpio_bank[0]; 211 return &gpio_bank[1 + (gpio >> 4)]; 212 } 213#endif 214#ifdef CONFIG_ARCH_OMAP730 215 if (cpu_is_omap730()) { 216 if (OMAP_GPIO_IS_MPUIO(gpio)) 217 return &gpio_bank[0]; 218 return &gpio_bank[1 + (gpio >> 5)]; 219 } 220#endif 221#ifdef CONFIG_ARCH_OMAP24XX 222 if (cpu_is_omap24xx()) 223 return &gpio_bank[gpio >> 5]; 224#endif 225} 226 227static inline int get_gpio_index(int gpio) 228{ 229#ifdef CONFIG_ARCH_OMAP730 230 if (cpu_is_omap730()) 231 return gpio & 0x1f; 232#endif 233#ifdef CONFIG_ARCH_OMAP24XX 234 if (cpu_is_omap24xx()) 235 return gpio & 0x1f; 236#endif 237 return gpio & 0x0f; 238} 239 240static inline int gpio_valid(int gpio) 241{ 242 if (gpio < 0) 243 return -1; 244#ifndef CONFIG_ARCH_OMAP24XX 245 if (OMAP_GPIO_IS_MPUIO(gpio)) { 246 if (gpio >= OMAP_MAX_GPIO_LINES + 16) 247 return -1; 248 return 0; 249 } 250#endif 251#ifdef CONFIG_ARCH_OMAP15XX 252 if (cpu_is_omap15xx() && gpio < 16) 253 return 0; 254#endif 255#if defined(CONFIG_ARCH_OMAP16XX) 256 if ((cpu_is_omap16xx()) && gpio < 64) 257 return 0; 258#endif 259#ifdef CONFIG_ARCH_OMAP730 260 if (cpu_is_omap730() && gpio < 192) 261 return 0; 262#endif 263#ifdef CONFIG_ARCH_OMAP24XX 264 if (cpu_is_omap24xx() && gpio < 128) 265 return 0; 266#endif 267 return -1; 268} 269 270static int check_gpio(int gpio) 271{ 272 if (unlikely(gpio_valid(gpio)) < 0) { 273 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); 274 dump_stack(); 275 return -1; 276 } 277 return 0; 278} 279 280static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) 281{ 282 void __iomem *reg = bank->base; 283 u32 l; 284 285 switch (bank->method) { 286#ifdef CONFIG_ARCH_OMAP1 287 case METHOD_MPUIO: 288 reg += OMAP_MPUIO_IO_CNTL; 289 break; 290#endif 291#ifdef CONFIG_ARCH_OMAP15XX 292 case METHOD_GPIO_1510: 293 reg += OMAP1510_GPIO_DIR_CONTROL; 294 break; 295#endif 296#ifdef CONFIG_ARCH_OMAP16XX 297 case METHOD_GPIO_1610: 298 reg += OMAP1610_GPIO_DIRECTION; 299 break; 300#endif 301#ifdef CONFIG_ARCH_OMAP730 302 case METHOD_GPIO_730: 303 reg += OMAP730_GPIO_DIR_CONTROL; 304 break; 305#endif 306#ifdef CONFIG_ARCH_OMAP24XX 307 case METHOD_GPIO_24XX: 308 reg += OMAP24XX_GPIO_OE; 309 break; 310#endif 311 default: 312 WARN_ON(1); 313 return; 314 } 315 l = __raw_readl(reg); 316 if (is_input) 317 l |= 1 << gpio; 318 else 319 l &= ~(1 << gpio); 320 __raw_writel(l, reg); 321} 322 323void omap_set_gpio_direction(int gpio, int is_input) 324{ 325 struct gpio_bank *bank; 326 327 if (check_gpio(gpio) < 0) 328 return; 329 bank = get_gpio_bank(gpio); 330 spin_lock(&bank->lock); 331 _set_gpio_direction(bank, get_gpio_index(gpio), is_input); 332 spin_unlock(&bank->lock); 333} 334 335static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) 336{ 337 void __iomem *reg = bank->base; 338 u32 l = 0; 339 340 switch (bank->method) { 341#ifdef CONFIG_ARCH_OMAP1 342 case METHOD_MPUIO: 343 reg += OMAP_MPUIO_OUTPUT; 344 l = __raw_readl(reg); 345 if (enable) 346 l |= 1 << gpio; 347 else 348 l &= ~(1 << gpio); 349 break; 350#endif 351#ifdef CONFIG_ARCH_OMAP15XX 352 case METHOD_GPIO_1510: 353 reg += OMAP1510_GPIO_DATA_OUTPUT; 354 l = __raw_readl(reg); 355 if (enable) 356 l |= 1 << gpio; 357 else 358 l &= ~(1 << gpio); 359 break; 360#endif 361#ifdef CONFIG_ARCH_OMAP16XX 362 case METHOD_GPIO_1610: 363 if (enable) 364 reg += OMAP1610_GPIO_SET_DATAOUT; 365 else 366 reg += OMAP1610_GPIO_CLEAR_DATAOUT; 367 l = 1 << gpio; 368 break; 369#endif 370#ifdef CONFIG_ARCH_OMAP730 371 case METHOD_GPIO_730: 372 reg += OMAP730_GPIO_DATA_OUTPUT; 373 l = __raw_readl(reg); 374 if (enable) 375 l |= 1 << gpio; 376 else 377 l &= ~(1 << gpio); 378 break; 379#endif 380#ifdef CONFIG_ARCH_OMAP24XX 381 case METHOD_GPIO_24XX: 382 if (enable) 383 reg += OMAP24XX_GPIO_SETDATAOUT; 384 else 385 reg += OMAP24XX_GPIO_CLEARDATAOUT; 386 l = 1 << gpio; 387 break; 388#endif 389 default: 390 WARN_ON(1); 391 return; 392 } 393 __raw_writel(l, reg); 394} 395 396void omap_set_gpio_dataout(int gpio, int enable) 397{ 398 struct gpio_bank *bank; 399 400 if (check_gpio(gpio) < 0) 401 return; 402 bank = get_gpio_bank(gpio); 403 spin_lock(&bank->lock); 404 _set_gpio_dataout(bank, get_gpio_index(gpio), enable); 405 spin_unlock(&bank->lock); 406} 407 408int omap_get_gpio_datain(int gpio) 409{ 410 struct gpio_bank *bank; 411 void __iomem *reg; 412 413 if (check_gpio(gpio) < 0) 414 return -EINVAL; 415 bank = get_gpio_bank(gpio); 416 reg = bank->base; 417 switch (bank->method) { 418#ifdef CONFIG_ARCH_OMAP1 419 case METHOD_MPUIO: 420 reg += OMAP_MPUIO_INPUT_LATCH; 421 break; 422#endif 423#ifdef CONFIG_ARCH_OMAP15XX 424 case METHOD_GPIO_1510: 425 reg += OMAP1510_GPIO_DATA_INPUT; 426 break; 427#endif 428#ifdef CONFIG_ARCH_OMAP16XX 429 case METHOD_GPIO_1610: 430 reg += OMAP1610_GPIO_DATAIN; 431 break; 432#endif 433#ifdef CONFIG_ARCH_OMAP730 434 case METHOD_GPIO_730: 435 reg += OMAP730_GPIO_DATA_INPUT; 436 break; 437#endif 438#ifdef CONFIG_ARCH_OMAP24XX 439 case METHOD_GPIO_24XX: 440 reg += OMAP24XX_GPIO_DATAIN; 441 break; 442#endif 443 default: 444 return -EINVAL; 445 } 446 return (__raw_readl(reg) 447 & (1 << get_gpio_index(gpio))) != 0; 448} 449 450#define MOD_REG_BIT(reg, bit_mask, set) \ 451do { \ 452 int l = __raw_readl(base + reg); \ 453 if (set) l |= bit_mask; \ 454 else l &= ~bit_mask; \ 455 __raw_writel(l, base + reg); \ 456} while(0) 457 458#ifdef CONFIG_ARCH_OMAP24XX 459static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 460{ 461 void __iomem *base = bank->base; 462 u32 gpio_bit = 1 << gpio; 463 464 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, 465 trigger & __IRQT_LOWLVL); 466 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, 467 trigger & __IRQT_HIGHLVL); 468 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, 469 trigger & __IRQT_RISEDGE); 470 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 471 trigger & __IRQT_FALEDGE); 472 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { 473 if (trigger != 0) 474 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA); 475 else 476 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA); 477 } else { 478 if (trigger != 0) 479 bank->enabled_non_wakeup_gpios |= gpio_bit; 480 else 481 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 482 } 483} 484#endif 485 486static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 487{ 488 void __iomem *reg = bank->base; 489 u32 l = 0; 490 491 switch (bank->method) { 492#ifdef CONFIG_ARCH_OMAP1 493 case METHOD_MPUIO: 494 reg += OMAP_MPUIO_GPIO_INT_EDGE; 495 l = __raw_readl(reg); 496 if (trigger & __IRQT_RISEDGE) 497 l |= 1 << gpio; 498 else if (trigger & __IRQT_FALEDGE) 499 l &= ~(1 << gpio); 500 else 501 goto bad; 502 break; 503#endif 504#ifdef CONFIG_ARCH_OMAP15XX 505 case METHOD_GPIO_1510: 506 reg += OMAP1510_GPIO_INT_CONTROL; 507 l = __raw_readl(reg); 508 if (trigger & __IRQT_RISEDGE) 509 l |= 1 << gpio; 510 else if (trigger & __IRQT_FALEDGE) 511 l &= ~(1 << gpio); 512 else 513 goto bad; 514 break; 515#endif 516#ifdef CONFIG_ARCH_OMAP16XX 517 case METHOD_GPIO_1610: 518 if (gpio & 0x08) 519 reg += OMAP1610_GPIO_EDGE_CTRL2; 520 else 521 reg += OMAP1610_GPIO_EDGE_CTRL1; 522 gpio &= 0x07; 523 l = __raw_readl(reg); 524 l &= ~(3 << (gpio << 1)); 525 if (trigger & __IRQT_RISEDGE) 526 l |= 2 << (gpio << 1); 527 if (trigger & __IRQT_FALEDGE) 528 l |= 1 << (gpio << 1); 529 if (trigger) 530 /* Enable wake-up during idle for dynamic tick */ 531 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); 532 else 533 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); 534 break; 535#endif 536#ifdef CONFIG_ARCH_OMAP730 537 case METHOD_GPIO_730: 538 reg += OMAP730_GPIO_INT_CONTROL; 539 l = __raw_readl(reg); 540 if (trigger & __IRQT_RISEDGE) 541 l |= 1 << gpio; 542 else if (trigger & __IRQT_FALEDGE) 543 l &= ~(1 << gpio); 544 else 545 goto bad; 546 break; 547#endif 548#ifdef CONFIG_ARCH_OMAP24XX 549 case METHOD_GPIO_24XX: 550 set_24xx_gpio_triggering(bank, gpio, trigger); 551 break; 552#endif 553 default: 554 goto bad; 555 } 556 __raw_writel(l, reg); 557 return 0; 558bad: 559 return -EINVAL; 560} 561 562static int gpio_irq_type(unsigned irq, unsigned type) 563{ 564 struct gpio_bank *bank; 565 unsigned gpio; 566 int retval; 567 568 if (!cpu_is_omap24xx() && irq > IH_MPUIO_BASE) 569 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); 570 else 571 gpio = irq - IH_GPIO_BASE; 572 573 if (check_gpio(gpio) < 0) 574 return -EINVAL; 575 576 if (type & ~IRQ_TYPE_SENSE_MASK) 577 return -EINVAL; 578 579 /* OMAP1 allows only only edge triggering */ 580 if (!cpu_is_omap24xx() 581 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) 582 return -EINVAL; 583 584 bank = get_irq_chip_data(irq); 585 spin_lock(&bank->lock); 586 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); 587 if (retval == 0) { 588 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; 589 irq_desc[irq].status |= type; 590 } 591 spin_unlock(&bank->lock); 592 return retval; 593} 594 595static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 596{ 597 void __iomem *reg = bank->base; 598 599 switch (bank->method) { 600#ifdef CONFIG_ARCH_OMAP1 601 case METHOD_MPUIO: 602 /* MPUIO irqstatus is reset by reading the status register, 603 * so do nothing here */ 604 return; 605#endif 606#ifdef CONFIG_ARCH_OMAP15XX 607 case METHOD_GPIO_1510: 608 reg += OMAP1510_GPIO_INT_STATUS; 609 break; 610#endif 611#ifdef CONFIG_ARCH_OMAP16XX 612 case METHOD_GPIO_1610: 613 reg += OMAP1610_GPIO_IRQSTATUS1; 614 break; 615#endif 616#ifdef CONFIG_ARCH_OMAP730 617 case METHOD_GPIO_730: 618 reg += OMAP730_GPIO_INT_STATUS; 619 break; 620#endif 621#ifdef CONFIG_ARCH_OMAP24XX 622 case METHOD_GPIO_24XX: 623 reg += OMAP24XX_GPIO_IRQSTATUS1; 624 break; 625#endif 626 default: 627 WARN_ON(1); 628 return; 629 } 630 __raw_writel(gpio_mask, reg); 631 632 if (cpu_is_omap2420()) 633 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2); 634} 635 636static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) 637{ 638 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); 639} 640 641static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) 642{ 643 void __iomem *reg = bank->base; 644 int inv = 0; 645 u32 l; 646 u32 mask; 647 648 switch (bank->method) { 649#ifdef CONFIG_ARCH_OMAP1 650 case METHOD_MPUIO: 651 reg += OMAP_MPUIO_GPIO_MASKIT; 652 mask = 0xffff; 653 inv = 1; 654 break; 655#endif 656#ifdef CONFIG_ARCH_OMAP15XX 657 case METHOD_GPIO_1510: 658 reg += OMAP1510_GPIO_INT_MASK; 659 mask = 0xffff; 660 inv = 1; 661 break; 662#endif 663#ifdef CONFIG_ARCH_OMAP16XX 664 case METHOD_GPIO_1610: 665 reg += OMAP1610_GPIO_IRQENABLE1; 666 mask = 0xffff; 667 break; 668#endif 669#ifdef CONFIG_ARCH_OMAP730 670 case METHOD_GPIO_730: 671 reg += OMAP730_GPIO_INT_MASK; 672 mask = 0xffffffff; 673 inv = 1; 674 break; 675#endif 676#ifdef CONFIG_ARCH_OMAP24XX 677 case METHOD_GPIO_24XX: 678 reg += OMAP24XX_GPIO_IRQENABLE1; 679 mask = 0xffffffff; 680 break; 681#endif 682 default: 683 WARN_ON(1); 684 return 0; 685 } 686 687 l = __raw_readl(reg); 688 if (inv) 689 l = ~l; 690 l &= mask; 691 return l; 692} 693 694static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) 695{ 696 void __iomem *reg = bank->base; 697 u32 l; 698 699 switch (bank->method) { 700#ifdef CONFIG_ARCH_OMAP1 701 case METHOD_MPUIO: 702 reg += OMAP_MPUIO_GPIO_MASKIT; 703 l = __raw_readl(reg); 704 if (enable) 705 l &= ~(gpio_mask); 706 else 707 l |= gpio_mask; 708 break; 709#endif 710#ifdef CONFIG_ARCH_OMAP15XX 711 case METHOD_GPIO_1510: 712 reg += OMAP1510_GPIO_INT_MASK; 713 l = __raw_readl(reg); 714 if (enable) 715 l &= ~(gpio_mask); 716 else 717 l |= gpio_mask; 718 break; 719#endif 720#ifdef CONFIG_ARCH_OMAP16XX 721 case METHOD_GPIO_1610: 722 if (enable) 723 reg += OMAP1610_GPIO_SET_IRQENABLE1; 724 else 725 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; 726 l = gpio_mask; 727 break; 728#endif 729#ifdef CONFIG_ARCH_OMAP730 730 case METHOD_GPIO_730: 731 reg += OMAP730_GPIO_INT_MASK; 732 l = __raw_readl(reg); 733 if (enable) 734 l &= ~(gpio_mask); 735 else 736 l |= gpio_mask; 737 break; 738#endif 739#ifdef CONFIG_ARCH_OMAP24XX 740 case METHOD_GPIO_24XX: 741 if (enable) 742 reg += OMAP24XX_GPIO_SETIRQENABLE1; 743 else 744 reg += OMAP24XX_GPIO_CLEARIRQENABLE1; 745 l = gpio_mask; 746 break; 747#endif 748 default: 749 WARN_ON(1); 750 return; 751 } 752 __raw_writel(l, reg); 753} 754 755static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) 756{ 757 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); 758} 759 760/* 761 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. 762 * 1510 does not seem to have a wake-up register. If JTAG is connected 763 * to the target, system will wake up always on GPIO events. While 764 * system is running all registered GPIO interrupts need to have wake-up 765 * enabled. When system is suspended, only selected GPIO interrupts need 766 * to have wake-up enabled. 767 */ 768static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) 769{ 770 switch (bank->method) { 771#ifdef CONFIG_ARCH_OMAP16XX 772 case METHOD_MPUIO: 773 case METHOD_GPIO_1610: 774 spin_lock(&bank->lock); 775 if (enable) { 776 bank->suspend_wakeup |= (1 << gpio); 777 enable_irq_wake(bank->irq); 778 } else { 779 disable_irq_wake(bank->irq); 780 bank->suspend_wakeup &= ~(1 << gpio); 781 } 782 spin_unlock(&bank->lock); 783 return 0; 784#endif 785#ifdef CONFIG_ARCH_OMAP24XX 786 case METHOD_GPIO_24XX: 787 if (bank->non_wakeup_gpios & (1 << gpio)) { 788 printk(KERN_ERR "Unable to modify wakeup on " 789 "non-wakeup GPIO%d\n", 790 (bank - gpio_bank) * 32 + gpio); 791 return -EINVAL; 792 } 793 spin_lock(&bank->lock); 794 if (enable) { 795 bank->suspend_wakeup |= (1 << gpio); 796 enable_irq_wake(bank->irq); 797 } else { 798 disable_irq_wake(bank->irq); 799 bank->suspend_wakeup &= ~(1 << gpio); 800 } 801 spin_unlock(&bank->lock); 802 return 0; 803#endif 804 default: 805 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", 806 bank->method); 807 return -EINVAL; 808 } 809} 810 811static void _reset_gpio(struct gpio_bank *bank, int gpio) 812{ 813 _set_gpio_direction(bank, get_gpio_index(gpio), 1); 814 _set_gpio_irqenable(bank, gpio, 0); 815 _clear_gpio_irqstatus(bank, gpio); 816 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE); 817} 818 819/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ 820static int gpio_wake_enable(unsigned int irq, unsigned int enable) 821{ 822 unsigned int gpio = irq - IH_GPIO_BASE; 823 struct gpio_bank *bank; 824 int retval; 825 826 if (check_gpio(gpio) < 0) 827 return -ENODEV; 828 bank = get_irq_chip_data(irq); 829 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); 830 831 return retval; 832} 833 834int omap_request_gpio(int gpio) 835{ 836 struct gpio_bank *bank; 837 838 if (check_gpio(gpio) < 0) 839 return -EINVAL; 840 841 bank = get_gpio_bank(gpio); 842 spin_lock(&bank->lock); 843 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) { 844 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio); 845 dump_stack(); 846 spin_unlock(&bank->lock); 847 return -1; 848 } 849 bank->reserved_map |= (1 << get_gpio_index(gpio)); 850 851 /* Set trigger to none. You need to enable the desired trigger with 852 * request_irq() or set_irq_type(). 853 */ 854 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE); 855 856#ifdef CONFIG_ARCH_OMAP15XX 857 if (bank->method == METHOD_GPIO_1510) { 858 void __iomem *reg; 859 860 /* Claim the pin for MPU */ 861 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; 862 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg); 863 } 864#endif 865 spin_unlock(&bank->lock); 866 867 return 0; 868} 869 870void omap_free_gpio(int gpio) 871{ 872 struct gpio_bank *bank; 873 874 if (check_gpio(gpio) < 0) 875 return; 876 bank = get_gpio_bank(gpio); 877 spin_lock(&bank->lock); 878 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) { 879 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio); 880 dump_stack(); 881 spin_unlock(&bank->lock); 882 return; 883 } 884#ifdef CONFIG_ARCH_OMAP16XX 885 if (bank->method == METHOD_GPIO_1610) { 886 /* Disable wake-up during idle for dynamic tick */ 887 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; 888 __raw_writel(1 << get_gpio_index(gpio), reg); 889 } 890#endif 891#ifdef CONFIG_ARCH_OMAP24XX 892 if (bank->method == METHOD_GPIO_24XX) { 893 /* Disable wake-up during idle for dynamic tick */ 894 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 895 __raw_writel(1 << get_gpio_index(gpio), reg); 896 } 897#endif 898 bank->reserved_map &= ~(1 << get_gpio_index(gpio)); 899 _reset_gpio(bank, gpio); 900 spin_unlock(&bank->lock); 901} 902 903/* 904 * We need to unmask the GPIO bank interrupt as soon as possible to 905 * avoid missing GPIO interrupts for other lines in the bank. 906 * Then we need to mask-read-clear-unmask the triggered GPIO lines 907 * in the bank to avoid missing nested interrupts for a GPIO line. 908 * If we wait to unmask individual GPIO lines in the bank after the 909 * line's interrupt handler has been run, we may miss some nested 910 * interrupts. 911 */ 912static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 913{ 914 void __iomem *isr_reg = NULL; 915 u32 isr; 916 unsigned int gpio_irq; 917 struct gpio_bank *bank; 918 u32 retrigger = 0; 919 int unmasked = 0; 920 921 desc->chip->ack(irq); 922 923 bank = get_irq_data(irq); 924#ifdef CONFIG_ARCH_OMAP1 925 if (bank->method == METHOD_MPUIO) 926 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; 927#endif 928#ifdef CONFIG_ARCH_OMAP15XX 929 if (bank->method == METHOD_GPIO_1510) 930 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; 931#endif 932#if defined(CONFIG_ARCH_OMAP16XX) 933 if (bank->method == METHOD_GPIO_1610) 934 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; 935#endif 936#ifdef CONFIG_ARCH_OMAP730 937 if (bank->method == METHOD_GPIO_730) 938 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; 939#endif 940#ifdef CONFIG_ARCH_OMAP24XX 941 if (bank->method == METHOD_GPIO_24XX) 942 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; 943#endif 944 while(1) { 945 u32 isr_saved, level_mask = 0; 946 u32 enabled; 947 948 enabled = _get_gpio_irqbank_mask(bank); 949 isr_saved = isr = __raw_readl(isr_reg) & enabled; 950 951 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) 952 isr &= 0x0000ffff; 953 954 if (cpu_is_omap24xx()) { 955 level_mask = 956 __raw_readl(bank->base + 957 OMAP24XX_GPIO_LEVELDETECT0) | 958 __raw_readl(bank->base + 959 OMAP24XX_GPIO_LEVELDETECT1); 960 level_mask &= enabled; 961 } 962 963 /* clear edge sensitive interrupts before handler(s) are 964 called so that we don't miss any interrupt occurred while 965 executing them */ 966 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); 967 _clear_gpio_irqbank(bank, isr_saved & ~level_mask); 968 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); 969 970 /* if there is only edge sensitive GPIO pin interrupts 971 configured, we could unmask GPIO bank interrupt immediately */ 972 if (!level_mask && !unmasked) { 973 unmasked = 1; 974 desc->chip->unmask(irq); 975 } 976 977 isr |= retrigger; 978 retrigger = 0; 979 if (!isr) 980 break; 981 982 gpio_irq = bank->virtual_irq_start; 983 for (; isr != 0; isr >>= 1, gpio_irq++) { 984 struct irq_desc *d; 985 int irq_mask; 986 if (!(isr & 1)) 987 continue; 988 d = irq_desc + gpio_irq; 989 /* Don't run the handler if it's already running 990 * or was disabled lazely. 991 */ 992 if (unlikely((d->depth || 993 (d->status & IRQ_INPROGRESS)))) { 994 irq_mask = 1 << 995 (gpio_irq - bank->virtual_irq_start); 996 /* The unmasking will be done by 997 * enable_irq in case it is disabled or 998 * after returning from the handler if 999 * it's already running. 1000 */ 1001 _enable_gpio_irqbank(bank, irq_mask, 0); 1002 if (!d->depth) { 1003 /* Level triggered interrupts 1004 * won't ever be reentered 1005 */ 1006 BUG_ON(level_mask & irq_mask); 1007 d->status |= IRQ_PENDING; 1008 } 1009 continue; 1010 } 1011 1012 desc_handle_irq(gpio_irq, d); 1013 1014 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) { 1015 irq_mask = 1 << 1016 (gpio_irq - bank->virtual_irq_start); 1017 d->status &= ~IRQ_PENDING; 1018 _enable_gpio_irqbank(bank, irq_mask, 1); 1019 retrigger |= irq_mask; 1020 } 1021 } 1022 1023 if (cpu_is_omap24xx()) { 1024 /* clear level sensitive interrupts after handler(s) */ 1025 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0); 1026 _clear_gpio_irqbank(bank, isr_saved & level_mask); 1027 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1); 1028 } 1029 1030 } 1031 /* if bank has any level sensitive GPIO pin interrupt 1032 configured, we must unmask the bank interrupt only after 1033 handler(s) are executed in order to avoid spurious bank 1034 interrupt */ 1035 if (!unmasked) 1036 desc->chip->unmask(irq); 1037 1038} 1039 1040static void gpio_irq_shutdown(unsigned int irq) 1041{ 1042 unsigned int gpio = irq - IH_GPIO_BASE; 1043 struct gpio_bank *bank = get_irq_chip_data(irq); 1044 1045 _reset_gpio(bank, gpio); 1046} 1047 1048static void gpio_ack_irq(unsigned int irq) 1049{ 1050 unsigned int gpio = irq - IH_GPIO_BASE; 1051 struct gpio_bank *bank = get_irq_chip_data(irq); 1052 1053 _clear_gpio_irqstatus(bank, gpio); 1054} 1055 1056static void gpio_mask_irq(unsigned int irq) 1057{ 1058 unsigned int gpio = irq - IH_GPIO_BASE; 1059 struct gpio_bank *bank = get_irq_chip_data(irq); 1060 1061 _set_gpio_irqenable(bank, gpio, 0); 1062} 1063 1064static void gpio_unmask_irq(unsigned int irq) 1065{ 1066 unsigned int gpio = irq - IH_GPIO_BASE; 1067 unsigned int gpio_idx = get_gpio_index(gpio); 1068 struct gpio_bank *bank = get_irq_chip_data(irq); 1069 1070 _set_gpio_irqenable(bank, gpio_idx, 1); 1071} 1072 1073static struct irq_chip gpio_irq_chip = { 1074 .name = "GPIO", 1075 .shutdown = gpio_irq_shutdown, 1076 .ack = gpio_ack_irq, 1077 .mask = gpio_mask_irq, 1078 .unmask = gpio_unmask_irq, 1079 .set_type = gpio_irq_type, 1080 .set_wake = gpio_wake_enable, 1081}; 1082 1083/*---------------------------------------------------------------------*/ 1084 1085#ifdef CONFIG_ARCH_OMAP1 1086 1087/* MPUIO uses the always-on 32k clock */ 1088 1089static void mpuio_ack_irq(unsigned int irq) 1090{ 1091 /* The ISR is reset automatically, so do nothing here. */ 1092} 1093 1094static void mpuio_mask_irq(unsigned int irq) 1095{ 1096 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); 1097 struct gpio_bank *bank = get_irq_chip_data(irq); 1098 1099 _set_gpio_irqenable(bank, gpio, 0); 1100} 1101 1102static void mpuio_unmask_irq(unsigned int irq) 1103{ 1104 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); 1105 struct gpio_bank *bank = get_irq_chip_data(irq); 1106 1107 _set_gpio_irqenable(bank, gpio, 1); 1108} 1109 1110static struct irq_chip mpuio_irq_chip = { 1111 .name = "MPUIO", 1112 .ack = mpuio_ack_irq, 1113 .mask = mpuio_mask_irq, 1114 .unmask = mpuio_unmask_irq, 1115 .set_type = gpio_irq_type, 1116#ifdef CONFIG_ARCH_OMAP16XX 1117 /* REVISIT: assuming only 16xx supports MPUIO wake events */ 1118 .set_wake = gpio_wake_enable, 1119#endif 1120}; 1121 1122 1123#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) 1124 1125 1126#ifdef CONFIG_ARCH_OMAP16XX 1127 1128#include <linux/platform_device.h> 1129 1130static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg) 1131{ 1132 struct gpio_bank *bank = platform_get_drvdata(pdev); 1133 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; 1134 1135 spin_lock(&bank->lock); 1136 bank->saved_wakeup = __raw_readl(mask_reg); 1137 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); 1138 spin_unlock(&bank->lock); 1139 1140 return 0; 1141} 1142 1143static int omap_mpuio_resume_early(struct platform_device *pdev) 1144{ 1145 struct gpio_bank *bank = platform_get_drvdata(pdev); 1146 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; 1147 1148 spin_lock(&bank->lock); 1149 __raw_writel(bank->saved_wakeup, mask_reg); 1150 spin_unlock(&bank->lock); 1151 1152 return 0; 1153} 1154 1155/* use platform_driver for this, now that there's no longer any 1156 * point to sys_device (other than not disturbing old code). 1157 */ 1158static struct platform_driver omap_mpuio_driver = { 1159 .suspend_late = omap_mpuio_suspend_late, 1160 .resume_early = omap_mpuio_resume_early, 1161 .driver = { 1162 .name = "mpuio", 1163 }, 1164}; 1165 1166static struct platform_device omap_mpuio_device = { 1167 .name = "mpuio", 1168 .id = -1, 1169 .dev = { 1170 .driver = &omap_mpuio_driver.driver, 1171 } 1172 /* could list the /proc/iomem resources */ 1173}; 1174 1175static inline void mpuio_init(void) 1176{ 1177 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); 1178 1179 if (platform_driver_register(&omap_mpuio_driver) == 0) 1180 (void) platform_device_register(&omap_mpuio_device); 1181} 1182 1183#else 1184static inline void mpuio_init(void) {} 1185#endif /* 16xx */ 1186 1187#else 1188 1189extern struct irq_chip mpuio_irq_chip; 1190 1191#define bank_is_mpuio(bank) 0 1192static inline void mpuio_init(void) {} 1193 1194#endif 1195 1196/*---------------------------------------------------------------------*/ 1197 1198static int initialized; 1199static struct clk * gpio_ick; 1200static struct clk * gpio_fck; 1201 1202#ifdef CONFIG_ARCH_OMAP2430 1203static struct clk * gpio5_ick; 1204static struct clk * gpio5_fck; 1205#endif 1206 1207static int __init _omap_gpio_init(void) 1208{ 1209 int i; 1210 struct gpio_bank *bank; 1211 1212 initialized = 1; 1213 1214 if (cpu_is_omap15xx()) { 1215 gpio_ick = clk_get(NULL, "arm_gpio_ck"); 1216 if (IS_ERR(gpio_ick)) 1217 printk("Could not get arm_gpio_ck\n"); 1218 else 1219 clk_enable(gpio_ick); 1220 } 1221 if (cpu_is_omap24xx()) { 1222 gpio_ick = clk_get(NULL, "gpios_ick"); 1223 if (IS_ERR(gpio_ick)) 1224 printk("Could not get gpios_ick\n"); 1225 else 1226 clk_enable(gpio_ick); 1227 gpio_fck = clk_get(NULL, "gpios_fck"); 1228 if (IS_ERR(gpio_fck)) 1229 printk("Could not get gpios_fck\n"); 1230 else 1231 clk_enable(gpio_fck); 1232 1233 /* 1234 * On 2430 GPIO 5 uses CORE L4 ICLK 1235 */ 1236#ifdef CONFIG_ARCH_OMAP2430 1237 if (cpu_is_omap2430()) { 1238 gpio5_ick = clk_get(NULL, "gpio5_ick"); 1239 if (IS_ERR(gpio5_ick)) 1240 printk("Could not get gpio5_ick\n"); 1241 else 1242 clk_enable(gpio5_ick); 1243 gpio5_fck = clk_get(NULL, "gpio5_fck"); 1244 if (IS_ERR(gpio5_fck)) 1245 printk("Could not get gpio5_fck\n"); 1246 else 1247 clk_enable(gpio5_fck); 1248 } 1249#endif 1250} 1251 1252#ifdef CONFIG_ARCH_OMAP15XX 1253 if (cpu_is_omap15xx()) { 1254 printk(KERN_INFO "OMAP1510 GPIO hardware\n"); 1255 gpio_bank_count = 2; 1256 gpio_bank = gpio_bank_1510; 1257 } 1258#endif 1259#if defined(CONFIG_ARCH_OMAP16XX) 1260 if (cpu_is_omap16xx()) { 1261 u32 rev; 1262 1263 gpio_bank_count = 5; 1264 gpio_bank = gpio_bank_1610; 1265 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); 1266 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", 1267 (rev >> 4) & 0x0f, rev & 0x0f); 1268 } 1269#endif 1270#ifdef CONFIG_ARCH_OMAP730 1271 if (cpu_is_omap730()) { 1272 printk(KERN_INFO "OMAP730 GPIO hardware\n"); 1273 gpio_bank_count = 7; 1274 gpio_bank = gpio_bank_730; 1275 } 1276#endif 1277 1278#ifdef CONFIG_ARCH_OMAP24XX 1279 if (cpu_is_omap242x()) { 1280 int rev; 1281 1282 gpio_bank_count = 4; 1283 gpio_bank = gpio_bank_242x; 1284 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1285 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n", 1286 (rev >> 4) & 0x0f, rev & 0x0f); 1287 } 1288 if (cpu_is_omap243x()) { 1289 int rev; 1290 1291 gpio_bank_count = 5; 1292 gpio_bank = gpio_bank_243x; 1293 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1294 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n", 1295 (rev >> 4) & 0x0f, rev & 0x0f); 1296 } 1297#endif 1298 for (i = 0; i < gpio_bank_count; i++) { 1299 int j, gpio_count = 16; 1300 1301 bank = &gpio_bank[i]; 1302 bank->reserved_map = 0; 1303 bank->base = IO_ADDRESS(bank->base); 1304 spin_lock_init(&bank->lock); 1305 if (bank_is_mpuio(bank)) 1306 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT); 1307#ifdef CONFIG_ARCH_OMAP15XX 1308 if (bank->method == METHOD_GPIO_1510) { 1309 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); 1310 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); 1311 } 1312#endif 1313#if defined(CONFIG_ARCH_OMAP16XX) 1314 if (bank->method == METHOD_GPIO_1610) { 1315 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); 1316 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); 1317 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); 1318 } 1319#endif 1320#ifdef CONFIG_ARCH_OMAP730 1321 if (bank->method == METHOD_GPIO_730) { 1322 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); 1323 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); 1324 1325 gpio_count = 32; /* 730 has 32-bit GPIOs */ 1326 } 1327#endif 1328#ifdef CONFIG_ARCH_OMAP24XX 1329 if (bank->method == METHOD_GPIO_24XX) { 1330 static const u32 non_wakeup_gpios[] = { 1331 0xe203ffc0, 0x08700040 1332 }; 1333 1334 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); 1335 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); 1336 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); 1337 1338 /* Initialize interface clock ungated, module enabled */ 1339 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); 1340 if (i < ARRAY_SIZE(non_wakeup_gpios)) 1341 bank->non_wakeup_gpios = non_wakeup_gpios[i]; 1342 gpio_count = 32; 1343 } 1344#endif 1345 for (j = bank->virtual_irq_start; 1346 j < bank->virtual_irq_start + gpio_count; j++) { 1347 set_irq_chip_data(j, bank); 1348 if (bank_is_mpuio(bank)) 1349 set_irq_chip(j, &mpuio_irq_chip); 1350 else 1351 set_irq_chip(j, &gpio_irq_chip); 1352 set_irq_handler(j, handle_simple_irq); 1353 set_irq_flags(j, IRQF_VALID); 1354 } 1355 set_irq_chained_handler(bank->irq, gpio_irq_handler); 1356 set_irq_data(bank->irq, bank); 1357 } 1358 1359 /* Enable system clock for GPIO module. 1360 * The CAM_CLK_CTRL *is* really the right place. */ 1361 if (cpu_is_omap16xx()) 1362 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); 1363 1364#ifdef CONFIG_ARCH_OMAP24XX 1365 /* Enable autoidle for the OCP interface */ 1366 if (cpu_is_omap24xx()) 1367 omap_writel(1 << 0, 0x48019010); 1368#endif 1369 1370 return 0; 1371} 1372 1373#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) 1374static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) 1375{ 1376 int i; 1377 1378 if (!cpu_is_omap24xx() && !cpu_is_omap16xx()) 1379 return 0; 1380 1381 for (i = 0; i < gpio_bank_count; i++) { 1382 struct gpio_bank *bank = &gpio_bank[i]; 1383 void __iomem *wake_status; 1384 void __iomem *wake_clear; 1385 void __iomem *wake_set; 1386 1387 switch (bank->method) { 1388#ifdef CONFIG_ARCH_OMAP16XX 1389 case METHOD_GPIO_1610: 1390 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; 1391 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; 1392 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1393 break; 1394#endif 1395#ifdef CONFIG_ARCH_OMAP24XX 1396 case METHOD_GPIO_24XX: 1397 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA; 1398 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1399 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1400 break; 1401#endif 1402 default: 1403 continue; 1404 } 1405 1406 spin_lock(&bank->lock); 1407 bank->saved_wakeup = __raw_readl(wake_status); 1408 __raw_writel(0xffffffff, wake_clear); 1409 __raw_writel(bank->suspend_wakeup, wake_set); 1410 spin_unlock(&bank->lock); 1411 } 1412 1413 return 0; 1414} 1415 1416static int omap_gpio_resume(struct sys_device *dev) 1417{ 1418 int i; 1419 1420 if (!cpu_is_omap24xx() && !cpu_is_omap16xx()) 1421 return 0; 1422 1423 for (i = 0; i < gpio_bank_count; i++) { 1424 struct gpio_bank *bank = &gpio_bank[i]; 1425 void __iomem *wake_clear; 1426 void __iomem *wake_set; 1427 1428 switch (bank->method) { 1429#ifdef CONFIG_ARCH_OMAP16XX 1430 case METHOD_GPIO_1610: 1431 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; 1432 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1433 break; 1434#endif 1435#ifdef CONFIG_ARCH_OMAP24XX 1436 case METHOD_GPIO_24XX: 1437 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1438 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1439 break; 1440#endif 1441 default: 1442 continue; 1443 } 1444 1445 spin_lock(&bank->lock); 1446 __raw_writel(0xffffffff, wake_clear); 1447 __raw_writel(bank->saved_wakeup, wake_set); 1448 spin_unlock(&bank->lock); 1449 } 1450 1451 return 0; 1452} 1453 1454static struct sysdev_class omap_gpio_sysclass = { 1455 set_kset_name("gpio"), 1456 .suspend = omap_gpio_suspend, 1457 .resume = omap_gpio_resume, 1458}; 1459 1460static struct sys_device omap_gpio_device = { 1461 .id = 0, 1462 .cls = &omap_gpio_sysclass, 1463}; 1464 1465#endif 1466 1467#ifdef CONFIG_ARCH_OMAP24XX 1468 1469static int workaround_enabled; 1470 1471void omap2_gpio_prepare_for_retention(void) 1472{ 1473 int i, c = 0; 1474 1475 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious 1476 * IRQs will be generated. See OMAP2420 Errata item 1.101. */ 1477 for (i = 0; i < gpio_bank_count; i++) { 1478 struct gpio_bank *bank = &gpio_bank[i]; 1479 u32 l1, l2; 1480 1481 if (!(bank->enabled_non_wakeup_gpios)) 1482 continue; 1483 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); 1484 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1485 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); 1486 bank->saved_fallingdetect = l1; 1487 bank->saved_risingdetect = l2; 1488 l1 &= ~bank->enabled_non_wakeup_gpios; 1489 l2 &= ~bank->enabled_non_wakeup_gpios; 1490 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1491 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); 1492 c++; 1493 } 1494 if (!c) { 1495 workaround_enabled = 0; 1496 return; 1497 } 1498 workaround_enabled = 1; 1499} 1500 1501void omap2_gpio_resume_after_retention(void) 1502{ 1503 int i; 1504 1505 if (!workaround_enabled) 1506 return; 1507 for (i = 0; i < gpio_bank_count; i++) { 1508 struct gpio_bank *bank = &gpio_bank[i]; 1509 u32 l; 1510 1511 if (!(bank->enabled_non_wakeup_gpios)) 1512 continue; 1513 __raw_writel(bank->saved_fallingdetect, 1514 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1515 __raw_writel(bank->saved_risingdetect, 1516 bank->base + OMAP24XX_GPIO_RISINGDETECT); 1517 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); 1518 l ^= bank->saved_datain; 1519 l &= bank->non_wakeup_gpios; 1520 if (l) { 1521 u32 old0, old1; 1522 1523 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1524 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1525 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1526 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1527 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1528 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1529 } 1530 } 1531 1532} 1533 1534#endif 1535 1536/* 1537 * This may get called early from board specific init 1538 * for boards that have interrupts routed via FPGA. 1539 */ 1540int __init omap_gpio_init(void) 1541{ 1542 if (!initialized) 1543 return _omap_gpio_init(); 1544 else 1545 return 0; 1546} 1547 1548static int __init omap_gpio_sysinit(void) 1549{ 1550 int ret = 0; 1551 1552 if (!initialized) 1553 ret = _omap_gpio_init(); 1554 1555 mpuio_init(); 1556 1557#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) 1558 if (cpu_is_omap16xx() || cpu_is_omap24xx()) { 1559 if (ret == 0) { 1560 ret = sysdev_class_register(&omap_gpio_sysclass); 1561 if (ret == 0) 1562 ret = sysdev_register(&omap_gpio_device); 1563 } 1564 } 1565#endif 1566 1567 return ret; 1568} 1569 1570EXPORT_SYMBOL(omap_request_gpio); 1571EXPORT_SYMBOL(omap_free_gpio); 1572EXPORT_SYMBOL(omap_set_gpio_direction); 1573EXPORT_SYMBOL(omap_set_gpio_dataout); 1574EXPORT_SYMBOL(omap_get_gpio_datain); 1575 1576arch_initcall(omap_gpio_sysinit); 1577 1578 1579#ifdef CONFIG_DEBUG_FS 1580 1581#include <linux/debugfs.h> 1582#include <linux/seq_file.h> 1583 1584static int gpio_is_input(struct gpio_bank *bank, int mask) 1585{ 1586 void __iomem *reg = bank->base; 1587 1588 switch (bank->method) { 1589 case METHOD_MPUIO: 1590 reg += OMAP_MPUIO_IO_CNTL; 1591 break; 1592 case METHOD_GPIO_1510: 1593 reg += OMAP1510_GPIO_DIR_CONTROL; 1594 break; 1595 case METHOD_GPIO_1610: 1596 reg += OMAP1610_GPIO_DIRECTION; 1597 break; 1598 case METHOD_GPIO_730: 1599 reg += OMAP730_GPIO_DIR_CONTROL; 1600 break; 1601 case METHOD_GPIO_24XX: 1602 reg += OMAP24XX_GPIO_OE; 1603 break; 1604 } 1605 return __raw_readl(reg) & mask; 1606} 1607 1608 1609static int dbg_gpio_show(struct seq_file *s, void *unused) 1610{ 1611 unsigned i, j, gpio; 1612 1613 for (i = 0, gpio = 0; i < gpio_bank_count; i++) { 1614 struct gpio_bank *bank = gpio_bank + i; 1615 unsigned bankwidth = 16; 1616 u32 mask = 1; 1617 1618 if (bank_is_mpuio(bank)) 1619 gpio = OMAP_MPUIO(0); 1620 else if (cpu_is_omap24xx() || cpu_is_omap730()) 1621 bankwidth = 32; 1622 1623 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { 1624 unsigned irq, value, is_in, irqstat; 1625 1626 if (!(bank->reserved_map & mask)) 1627 continue; 1628 1629 irq = bank->virtual_irq_start + j; 1630 value = omap_get_gpio_datain(gpio); 1631 is_in = gpio_is_input(bank, mask); 1632 1633 if (bank_is_mpuio(bank)) 1634 seq_printf(s, "MPUIO %2d: ", j); 1635 else 1636 seq_printf(s, "GPIO %3d: ", gpio); 1637 seq_printf(s, "%s %s", 1638 is_in ? "in " : "out", 1639 value ? "hi" : "lo"); 1640 1641 irqstat = irq_desc[irq].status; 1642 if (is_in && ((bank->suspend_wakeup & mask) 1643 || irqstat & IRQ_TYPE_SENSE_MASK)) { 1644 char *trigger = NULL; 1645 1646 switch (irqstat & IRQ_TYPE_SENSE_MASK) { 1647 case IRQ_TYPE_EDGE_FALLING: 1648 trigger = "falling"; 1649 break; 1650 case IRQ_TYPE_EDGE_RISING: 1651 trigger = "rising"; 1652 break; 1653 case IRQ_TYPE_EDGE_BOTH: 1654 trigger = "bothedge"; 1655 break; 1656 case IRQ_TYPE_LEVEL_LOW: 1657 trigger = "low"; 1658 break; 1659 case IRQ_TYPE_LEVEL_HIGH: 1660 trigger = "high"; 1661 break; 1662 case IRQ_TYPE_NONE: 1663 trigger = "(unspecified)"; 1664 break; 1665 } 1666 seq_printf(s, ", irq-%d %s%s", 1667 irq, trigger, 1668 (bank->suspend_wakeup & mask) 1669 ? " wakeup" : ""); 1670 } 1671 seq_printf(s, "\n"); 1672 } 1673 1674 if (bank_is_mpuio(bank)) { 1675 seq_printf(s, "\n"); 1676 gpio = 0; 1677 } 1678 } 1679 return 0; 1680} 1681 1682static int dbg_gpio_open(struct inode *inode, struct file *file) 1683{ 1684 return single_open(file, dbg_gpio_show, &inode->i_private); 1685} 1686 1687static const struct file_operations debug_fops = { 1688 .open = dbg_gpio_open, 1689 .read = seq_read, 1690 .llseek = seq_lseek, 1691 .release = single_release, 1692}; 1693 1694static int __init omap_gpio_debuginit(void) 1695{ 1696 (void) debugfs_create_file("omap_gpio", S_IRUGO, 1697 NULL, NULL, &debug_fops); 1698 return 0; 1699} 1700late_initcall(omap_gpio_debuginit); 1701#endif 1702