1/*
2 *  linux/arch/arm/mm/proc-sa110.S
3 *
4 *  Copyright (C) 1997-2002 Russell King
5 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 *  MMU functions for SA110
12 *
13 *  These are the low level assembler for performing cache and TLB
14 *  functions on the StrongARM-110.
15 */
16#include <linux/linkage.h>
17#include <linux/init.h>
18#include <asm/assembler.h>
19#include <asm/asm-offsets.h>
20#include <asm/elf.h>
21#include <asm/hardware.h>
22#include <asm/pgtable-hwdef.h>
23#include <asm/pgtable.h>
24#include <asm/ptrace.h>
25
26#include "proc-macros.S"
27
28/*
29 * the cache line size of the I and D cache
30 */
31#define DCACHELINESIZE	32
32
33	.text
34
35/*
36 * cpu_sa110_proc_init()
37 */
38ENTRY(cpu_sa110_proc_init)
39	mov	r0, #0
40	mcr	p15, 0, r0, c15, c1, 2		@ Enable clock switching
41	mov	pc, lr
42
43/*
44 * cpu_sa110_proc_fin()
45 */
46ENTRY(cpu_sa110_proc_fin)
47	stmfd	sp!, {lr}
48	mov	ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
49	msr	cpsr_c, ip
50	bl	v4wb_flush_kern_cache_all	@ clean caches
511:	mov	r0, #0
52	mcr	p15, 0, r0, c15, c2, 2		@ Disable clock switching
53	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
54	bic	r0, r0, #0x1000			@ ...i............
55	bic	r0, r0, #0x000e			@ ............wca.
56	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
57	ldmfd	sp!, {pc}
58
59/*
60 * cpu_sa110_reset(loc)
61 *
62 * Perform a soft reset of the system.  Put the CPU into the
63 * same state as it would be if it had been reset, and branch
64 * to what would be the reset vector.
65 *
66 * loc: location to jump to for soft reset
67 */
68	.align	5
69ENTRY(cpu_sa110_reset)
70	mov	ip, #0
71	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
72	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
73#ifdef CONFIG_MMU
74	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
75#endif
76	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
77	bic	ip, ip, #0x000f			@ ............wcam
78	bic	ip, ip, #0x1100			@ ...i...s........
79	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
80	mov	pc, r0
81
82/*
83 * cpu_sa110_do_idle(type)
84 *
85 * Cause the processor to idle
86 *
87 * type: call type:
88 *   0 = slow idle
89 *   1 = fast idle
90 *   2 = switch to slow processor clock
91 *   3 = switch to fast processor clock
92 */
93	.align	5
94
95ENTRY(cpu_sa110_do_idle)
96	mcr	p15, 0, ip, c15, c2, 2		@ disable clock switching
97	ldr	r1, =UNCACHEABLE_ADDR		@ load from uncacheable loc
98	ldr	r1, [r1, #0]			@ force switch to MCLK
99	mov	r0, r0				@ safety
100	mov	r0, r0				@ safety
101	mov	r0, r0				@ safety
102	mcr	p15, 0, r0, c15, c8, 2		@ Wait for interrupt, cache aligned
103	mov	r0, r0				@ safety
104	mov	r0, r0				@ safety
105	mov	r0, r0				@ safety
106	mcr	p15, 0, r0, c15, c1, 2		@ enable clock switching
107	mov	pc, lr
108
109/* ================================= CACHE ================================ */
110
111/*
112 * cpu_sa110_dcache_clean_area(addr,sz)
113 *
114 * Clean the specified entry of any caches such that the MMU
115 * translation fetches will obtain correct data.
116 *
117 * addr: cache-unaligned virtual address
118 */
119	.align	5
120ENTRY(cpu_sa110_dcache_clean_area)
1211:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
122	add	r0, r0, #DCACHELINESIZE
123	subs	r1, r1, #DCACHELINESIZE
124	bhi	1b
125	mov	pc, lr
126
127/* =============================== PageTable ============================== */
128
129/*
130 * cpu_sa110_switch_mm(pgd)
131 *
132 * Set the translation base pointer to be as described by pgd.
133 *
134 * pgd: new page tables
135 */
136	.align	5
137ENTRY(cpu_sa110_switch_mm)
138#ifdef CONFIG_MMU
139	str	lr, [sp, #-4]!
140	bl	v4wb_flush_kern_cache_all	@ clears IP
141	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
142	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
143	ldr	pc, [sp], #4
144#else
145	mov	pc, lr
146#endif
147
148/*
149 * cpu_sa110_set_pte_ext(ptep, pte, ext)
150 *
151 * Set a PTE and flush it out
152 */
153	.align	5
154ENTRY(cpu_sa110_set_pte_ext)
155#ifdef CONFIG_MMU
156	str	r1, [r0], #-2048		@ linux version
157
158	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
159
160	bic	r2, r1, #PTE_SMALL_AP_MASK
161	bic	r2, r2, #PTE_TYPE_MASK
162	orr	r2, r2, #PTE_TYPE_SMALL
163
164	tst	r1, #L_PTE_USER			@ User?
165	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW
166
167	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
168	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW
169
170	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?
171	movne	r2, #0
172
173	str	r2, [r0]			@ hardware version
174	mov	r0, r0
175	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
176	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
177#endif
178	mov	pc, lr
179
180	__INIT
181
182	.type	__sa110_setup, #function
183__sa110_setup:
184	mov	r10, #0
185	mcr	p15, 0, r10, c7, c7		@ invalidate I,D caches on v4
186	mcr	p15, 0, r10, c7, c10, 4		@ drain write buffer on v4
187#ifdef CONFIG_MMU
188	mcr	p15, 0, r10, c8, c7		@ invalidate I,D TLBs on v4
189#endif
190
191	adr	r5, sa110_crval
192	ldmia	r5, {r5, r6}
193	mrc	p15, 0, r0, c1, c0		@ get control register v4
194	bic	r0, r0, r5
195	orr	r0, r0, r6
196	mov	pc, lr
197	.size	__sa110_setup, . - __sa110_setup
198
199	/*
200	 *  R
201	 * .RVI ZFRS BLDP WCAM
202	 * ..01 0001 ..11 1101
203	 *
204	 */
205	.type	sa110_crval, #object
206sa110_crval:
207	crval	clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
208
209	__INITDATA
210
211/*
212 * Purpose : Function pointers used to access above functions - all calls
213 *	     come through these
214 */
215
216	.type	sa110_processor_functions, #object
217ENTRY(sa110_processor_functions)
218	.word	v4_early_abort
219	.word	cpu_sa110_proc_init
220	.word	cpu_sa110_proc_fin
221	.word	cpu_sa110_reset
222	.word	cpu_sa110_do_idle
223	.word	cpu_sa110_dcache_clean_area
224	.word	cpu_sa110_switch_mm
225	.word	cpu_sa110_set_pte_ext
226	.size	sa110_processor_functions, . - sa110_processor_functions
227
228	.section ".rodata"
229
230	.type	cpu_arch_name, #object
231cpu_arch_name:
232	.asciz	"armv4"
233	.size	cpu_arch_name, . - cpu_arch_name
234
235	.type	cpu_elf_name, #object
236cpu_elf_name:
237	.asciz	"v4"
238	.size	cpu_elf_name, . - cpu_elf_name
239
240	.type	cpu_sa110_name, #object
241cpu_sa110_name:
242	.asciz	"StrongARM-110"
243	.size	cpu_sa110_name, . - cpu_sa110_name
244
245	.align
246
247	.section ".proc.info.init", #alloc, #execinstr
248
249	.type	__sa110_proc_info,#object
250__sa110_proc_info:
251	.long	0x4401a100
252	.long	0xfffffff0
253	.long   PMD_TYPE_SECT | \
254		PMD_SECT_BUFFERABLE | \
255		PMD_SECT_CACHEABLE | \
256		PMD_SECT_AP_WRITE | \
257		PMD_SECT_AP_READ
258	.long   PMD_TYPE_SECT | \
259		PMD_SECT_AP_WRITE | \
260		PMD_SECT_AP_READ
261	b	__sa110_setup
262	.long	cpu_arch_name
263	.long	cpu_elf_name
264	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
265	.long	cpu_sa110_name
266	.long	sa110_processor_functions
267	.long	v4wb_tlb_fns
268	.long	v4wb_user_fns
269	.long	v4wb_cache_fns
270	.size	__sa110_proc_info, . - __sa110_proc_info
271