1/*
2 * arch/arm/mach-ixp4xx/common.c
3 *
4 * Generic code shared across all IXP4XX platforms
5 *
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
10 *
11 * This file is licensed under  the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/kernel.h>
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/serial.h>
20#include <linux/sched.h>
21#include <linux/tty.h>
22#include <linux/platform_device.h>
23#include <linux/serial_core.h>
24#include <linux/bootmem.h>
25#include <linux/interrupt.h>
26#include <linux/bitops.h>
27#include <linux/time.h>
28#include <linux/timex.h>
29#include <linux/clocksource.h>
30#include <linux/clockchips.h>
31
32#include <asm/arch/udc.h>
33#include <asm/hardware.h>
34#include <asm/uaccess.h>
35#include <asm/io.h>
36#include <asm/pgtable.h>
37#include <asm/page.h>
38#include <asm/irq.h>
39
40#include <asm/mach/map.h>
41#include <asm/mach/irq.h>
42#include <asm/mach/time.h>
43
44static int __init ixp4xx_clocksource_init(void);
45static int __init ixp4xx_clockevent_init(void);
46static struct clock_event_device clockevent_ixp4xx;
47
48/*************************************************************************
49 * IXP4xx chipset I/O mapping
50 *************************************************************************/
51static struct map_desc ixp4xx_io_desc[] __initdata = {
52	{	/* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
53		.virtual	= IXP4XX_PERIPHERAL_BASE_VIRT,
54		.pfn		= __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
55		.length		= IXP4XX_PERIPHERAL_REGION_SIZE,
56		.type		= MT_DEVICE
57	}, {	/* Expansion Bus Config Registers */
58		.virtual	= IXP4XX_EXP_CFG_BASE_VIRT,
59		.pfn		= __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
60		.length		= IXP4XX_EXP_CFG_REGION_SIZE,
61		.type		= MT_DEVICE
62	}, {	/* PCI Registers */
63		.virtual	= IXP4XX_PCI_CFG_BASE_VIRT,
64		.pfn		= __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
65		.length		= IXP4XX_PCI_CFG_REGION_SIZE,
66		.type		= MT_DEVICE
67	},
68#ifdef CONFIG_DEBUG_LL
69	{	/* Debug UART mapping */
70		.virtual	= IXP4XX_DEBUG_UART_BASE_VIRT,
71		.pfn		= __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
72		.length		= IXP4XX_DEBUG_UART_REGION_SIZE,
73		.type		= MT_DEVICE
74	}
75#endif
76};
77
78void __init ixp4xx_map_io(void)
79{
80  	iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
81}
82
83
84/*************************************************************************
85 * IXP4xx chipset IRQ handling
86 *
87 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
88 *       (be it PCI or something else) configures that GPIO line
89 *       as an IRQ.
90 **************************************************************************/
91enum ixp4xx_irq_type {
92	IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
93};
94
95/* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
96static unsigned long long ixp4xx_irq_edge = 0;
97
98/*
99 * IRQ -> GPIO mapping table
100 */
101static signed char irq2gpio[32] = {
102	-1, -1, -1, -1, -1, -1,  0,  1,
103	-1, -1, -1, -1, -1, -1, -1, -1,
104	-1, -1, -1,  2,  3,  4,  5,  6,
105	 7,  8,  9, 10, 11, 12, -1, -1,
106};
107
108int gpio_to_irq(int gpio)
109{
110	int irq;
111
112	for (irq = 0; irq < 32; irq++) {
113		if (irq2gpio[irq] == gpio)
114			return irq;
115	}
116	return -EINVAL;
117}
118EXPORT_SYMBOL(gpio_to_irq);
119
120int irq_to_gpio(int irq)
121{
122	int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
123
124	if (gpio == -1)
125		return -EINVAL;
126
127	return gpio;
128}
129EXPORT_SYMBOL(irq_to_gpio);
130
131static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
132{
133	int line = irq2gpio[irq];
134	u32 int_style;
135	enum ixp4xx_irq_type irq_type;
136	volatile u32 *int_reg;
137
138	/*
139	 * Only for GPIO IRQs
140	 */
141	if (line < 0)
142		return -EINVAL;
143
144	switch (type){
145	case IRQT_BOTHEDGE:
146		int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
147		irq_type = IXP4XX_IRQ_EDGE;
148		break;
149	case IRQT_RISING:
150		int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
151		irq_type = IXP4XX_IRQ_EDGE;
152		break;
153	case IRQT_FALLING:
154		int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
155		irq_type = IXP4XX_IRQ_EDGE;
156		break;
157	case IRQT_HIGH:
158		int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
159		irq_type = IXP4XX_IRQ_LEVEL;
160		break;
161	case IRQT_LOW:
162		int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
163		irq_type = IXP4XX_IRQ_LEVEL;
164		break;
165	default:
166		return -EINVAL;
167	}
168
169	if (irq_type == IXP4XX_IRQ_EDGE)
170		ixp4xx_irq_edge |= (1 << irq);
171	else
172		ixp4xx_irq_edge &= ~(1 << irq);
173
174	if (line >= 8) {	/* pins 8-15 */
175		line -= 8;
176		int_reg = IXP4XX_GPIO_GPIT2R;
177	} else {		/* pins 0-7 */
178		int_reg = IXP4XX_GPIO_GPIT1R;
179	}
180
181	/* Clear the style for the appropriate pin */
182	*int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
183	    		(line * IXP4XX_GPIO_STYLE_SIZE));
184
185	*IXP4XX_GPIO_GPISR = (1 << line);
186
187	/* Set the new style */
188	*int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
189
190	/* Configure the line as an input */
191	gpio_line_config(line, IXP4XX_GPIO_IN);
192
193	return 0;
194}
195
196static void ixp4xx_irq_mask(unsigned int irq)
197{
198	if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
199		*IXP4XX_ICMR2 &= ~(1 << (irq - 32));
200	else
201		*IXP4XX_ICMR &= ~(1 << irq);
202}
203
204static void ixp4xx_irq_ack(unsigned int irq)
205{
206	int line = (irq < 32) ? irq2gpio[irq] : -1;
207
208	if (line >= 0)
209		*IXP4XX_GPIO_GPISR = (1 << line);
210}
211
212/*
213 * Level triggered interrupts on GPIO lines can only be cleared when the
214 * interrupt condition disappears.
215 */
216static void ixp4xx_irq_unmask(unsigned int irq)
217{
218	if (!(ixp4xx_irq_edge & (1 << irq)))
219		ixp4xx_irq_ack(irq);
220
221	if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
222		*IXP4XX_ICMR2 |= (1 << (irq - 32));
223	else
224		*IXP4XX_ICMR |= (1 << irq);
225}
226
227static struct irq_chip ixp4xx_irq_chip = {
228	.name		= "IXP4xx",
229	.ack		= ixp4xx_irq_ack,
230	.mask		= ixp4xx_irq_mask,
231	.unmask		= ixp4xx_irq_unmask,
232	.set_type	= ixp4xx_set_irq_type,
233};
234
235void __init ixp4xx_init_irq(void)
236{
237	int i = 0;
238
239	/* Route all sources to IRQ instead of FIQ */
240	*IXP4XX_ICLR = 0x0;
241
242	/* Disable all interrupt */
243	*IXP4XX_ICMR = 0x0;
244
245	if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
246		/* Route upper 32 sources to IRQ instead of FIQ */
247		*IXP4XX_ICLR2 = 0x00;
248
249		/* Disable upper 32 interrupts */
250		*IXP4XX_ICMR2 = 0x00;
251	}
252
253        /* Default to all level triggered */
254	for(i = 0; i < NR_IRQS; i++) {
255		set_irq_chip(i, &ixp4xx_irq_chip);
256		set_irq_handler(i, handle_level_irq);
257		set_irq_flags(i, IRQF_VALID);
258	}
259}
260
261
262/*************************************************************************
263 * IXP4xx timer tick
264 * We use OS timer1 on the CPU for the timer tick and the timestamp
265 * counter as a source of real clock ticks to account for missed jiffies.
266 *************************************************************************/
267
268static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
269{
270	struct clock_event_device *evt = &clockevent_ixp4xx;
271
272	/* Clear Pending Interrupt by writing '1' to it */
273	*IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
274
275	evt->event_handler(evt);
276
277	return IRQ_HANDLED;
278}
279
280static struct irqaction ixp4xx_timer_irq = {
281	.name		= "timer1",
282	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
283	.handler	= ixp4xx_timer_interrupt,
284};
285
286void __init ixp4xx_timer_init(void)
287{
288	/* Reset/disable counter */
289	*IXP4XX_OSRT1 = 0;
290
291	/* Clear Pending Interrupt by writing '1' to it */
292	*IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
293
294	/* Reset time-stamp counter */
295	*IXP4XX_OSTS = 0;
296
297	/* Connect the interrupt handler and enable the interrupt */
298	setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
299
300	ixp4xx_clocksource_init();
301	ixp4xx_clockevent_init();
302}
303
304struct sys_timer ixp4xx_timer = {
305	.init		= ixp4xx_timer_init,
306};
307
308static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
309
310void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
311{
312	memcpy(&ixp4xx_udc_info, info, sizeof *info);
313}
314
315static struct resource ixp4xx_udc_resources[] = {
316	[0] = {
317		.start  = 0xc800b000,
318		.end    = 0xc800bfff,
319		.flags  = IORESOURCE_MEM,
320	},
321	[1] = {
322		.start  = IRQ_IXP4XX_USB,
323		.end    = IRQ_IXP4XX_USB,
324		.flags  = IORESOURCE_IRQ,
325	},
326};
327
328/*
329 * USB device controller. The IXP4xx uses the same controller as PXA2XX,
330 * so we just use the same device.
331 */
332static struct platform_device ixp4xx_udc_device = {
333	.name           = "pxa2xx-udc",
334	.id             = -1,
335	.num_resources  = 2,
336	.resource       = ixp4xx_udc_resources,
337	.dev            = {
338		.platform_data = &ixp4xx_udc_info,
339	},
340};
341
342static struct platform_device *ixp4xx_devices[] __initdata = {
343	&ixp4xx_udc_device,
344};
345
346static struct resource ixp46x_i2c_resources[] = {
347	[0] = {
348		.start 	= 0xc8011000,
349		.end	= 0xc801101c,
350		.flags	= IORESOURCE_MEM,
351	},
352	[1] = {
353		.start 	= IRQ_IXP4XX_I2C,
354		.end	= IRQ_IXP4XX_I2C,
355		.flags	= IORESOURCE_IRQ
356	}
357};
358
359/*
360 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
361 * we just use the same device name.
362 */
363static struct platform_device ixp46x_i2c_controller = {
364	.name		= "IOP3xx-I2C",
365	.id		= 0,
366	.num_resources	= 2,
367	.resource	= ixp46x_i2c_resources
368};
369
370static struct platform_device *ixp46x_devices[] __initdata = {
371	&ixp46x_i2c_controller
372};
373
374unsigned long ixp4xx_exp_bus_size;
375EXPORT_SYMBOL(ixp4xx_exp_bus_size);
376
377void __init ixp4xx_sys_init(void)
378{
379	ixp4xx_exp_bus_size = SZ_16M;
380
381	platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
382
383	if (cpu_is_ixp46x()) {
384		int region;
385
386		platform_add_devices(ixp46x_devices,
387				ARRAY_SIZE(ixp46x_devices));
388
389		for (region = 0; region < 7; region++) {
390			if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
391				ixp4xx_exp_bus_size = SZ_32M;
392				break;
393			}
394		}
395	}
396
397	printk("IXP4xx: Using %luMiB expansion bus window size\n",
398			ixp4xx_exp_bus_size >> 20);
399}
400
401/*
402 * clocksource
403 */
404cycle_t ixp4xx_get_cycles(void)
405{
406	return *IXP4XX_OSTS;
407}
408
409static struct clocksource clocksource_ixp4xx = {
410	.name 		= "OSTS",
411	.rating		= 200,
412	.read		= ixp4xx_get_cycles,
413	.mask		= CLOCKSOURCE_MASK(32),
414	.shift 		= 20,
415	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
416};
417
418unsigned long ixp4xx_timer_freq = FREQ;
419static int __init ixp4xx_clocksource_init(void)
420{
421	clocksource_ixp4xx.mult =
422		clocksource_hz2mult(ixp4xx_timer_freq,
423				    clocksource_ixp4xx.shift);
424	clocksource_register(&clocksource_ixp4xx);
425
426	return 0;
427}
428
429/*
430 * clockevents
431 */
432static int ixp4xx_set_next_event(unsigned long evt,
433				 struct clock_event_device *unused)
434{
435	unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
436
437	*IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
438
439	return 0;
440}
441
442static void ixp4xx_set_mode(enum clock_event_mode mode,
443			    struct clock_event_device *evt)
444{
445	unsigned long opts, osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
446
447	switch (mode) {
448	case CLOCK_EVT_MODE_PERIODIC:
449		osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
450 		opts = IXP4XX_OST_ENABLE;
451		break;
452	case CLOCK_EVT_MODE_ONESHOT:
453		/* period set by 'set next_event' */
454		osrt = 0;
455		opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
456		break;
457	case CLOCK_EVT_MODE_SHUTDOWN:
458	case CLOCK_EVT_MODE_UNUSED:
459	default:
460		osrt = opts = 0;
461		break;
462	}
463
464	*IXP4XX_OSRT1 = osrt | opts;
465}
466
467static struct clock_event_device clockevent_ixp4xx = {
468	.name		= "ixp4xx timer1",
469	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
470	.rating         = 200,
471	.shift		= 24,
472	.set_mode	= ixp4xx_set_mode,
473	.set_next_event	= ixp4xx_set_next_event,
474};
475
476static int __init ixp4xx_clockevent_init(void)
477{
478	clockevent_ixp4xx.mult = div_sc(FREQ, NSEC_PER_SEC,
479					clockevent_ixp4xx.shift);
480	clockevent_ixp4xx.max_delta_ns =
481		clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
482	clockevent_ixp4xx.min_delta_ns =
483		clockevent_delta2ns(0xf, &clockevent_ixp4xx);
484	clockevent_ixp4xx.cpumask = cpumask_of_cpu(0);
485
486	clockevents_register_device(&clockevent_ixp4xx);
487	return 0;
488}
489