1/* 2 * SPROM format definitions for the Broadcom 47xx and 43xx chip family. 3 * 4 * $Id: sbsprom.h,v 1.6 2007/08/16 22:58:33 Exp $ 5 * Copyright(c) 2002 Broadcom Corporation 6 */ 7 8#ifndef _SBSPROM_H 9#define _SBSPROM_H 10 11#include "typedefs.h" 12#include "bcmdevs.h" 13 14/* A word is this many bytes */ 15#define SRW 2 16 17/* offset into PCI config space for write enable bit */ 18#define CFG_SROM_WRITABLE_OFFSET 0x88 19#define SROM_WRITEABLE 0x10 20 21/* enumeration space consists of N contiguous 4Kbyte core register sets */ 22#define SBCORES_BASE 0x18000000 23#define SBCORES_EACH 0x1000 24 25/* offset from BAR0 for srom space */ 26#define SROM_BASE 4096 27 28/* number of 2-byte words in srom */ 29#define SROM_SIZE 64 30 31#define SROM_BYTES (SROM_SIZE * SRW) 32 33#define MAX_FN 4 34 35/* Word 0, Hardware control */ 36#define SROM_HWCTL 0 37#define HW_FUNMSK 0x000f 38#define HW_FCLK 0x0200 39#define HW_CBM 0x0400 40#define HW_PIMSK 0xf000 41#define HW_PISHIFT 12 42#define HW_4301PISHIFT 13 43#define HW_PI4402 0x2 44#define HW_FUN4401 0x0001 45#define HW_FCLK4402 0x0000 46 47/* Word 1, common-power/boot-rom */ 48#define SROM_COMMPW 1 49/* boot rom present bit */ 50#define BR_PRESSHIFT 8 51/* 15:9 for n; boot rom size is 2^(14 + n) bytes */ 52#define BR_SIZESHIFT 9 53 54/* Word 2, SubsystemId */ 55#define SROM_SSID 2 56 57/* Word 3, VendorId */ 58#define SROM_VID 3 59 60/* Function 0 info, function info length */ 61#define SROM_FN0 4 62#define SROM_FNSZ 8 63 64/* Within each function: */ 65/* Word 0, deviceID */ 66#define SRFN_DID 0 67 68/* Words 1-2, ClassCode */ 69#define SRFN_CCL 1 70/* Word 2, D0 Power */ 71#define SRFN_CCHD0 2 72 73/* Word 3, PME and D1D2D3 power */ 74#define SRFN_PMED123 3 75 76#define PME_IL 0 77#define PME_ENET0 1 78#define PME_ENET1 2 79#define PME_CODEC 3 80 81#define PME_4402_ENET 0 82#define PME_4402_CODEC 1 83#define PME_4301_WL 2 84#define PMEREP_4402_ENET (PMERD3CV | PMERD3CA | PMERD3H | PMERD2 | PMERD1 | PMERD0 | PME) 85 86/* Word 4, Bar1 enable, pme reports */ 87#define SRFN_B1PMER 4 88#define B1E 1 89#define B1SZMSK 0xe 90#define B1SZSH 1 91#define PMERMSK 0x0ff0 92#define PME 0x0010 93#define PMERD0 0x0020 94#define PMERD1 0x0040 95#define PMERD2 0x0080 96#define PMERD3H 0x0100 97#define PMERD3CA 0x0200 98#define PMERD3CV 0x0400 99#define IGNCLKRR 0x0800 100#define B0LMSK 0xf000 101 102/* Words 4-5, Bar0 Sonics value */ 103#define SRFN_B0H 5 104/* Words 6-7, CIS Pointer */ 105#define SRFN_CISL 6 106#define SRFN_CISH 7 107 108/* Words 36-38: iLine MAC address */ 109#define SROM_I_MACHI 36 110#define SROM_I_MACMID 37 111#define SROM_I_MACLO 38 112 113/* Words 36-38: wireless0 MAC address on 43xx */ 114#define SROM_W0_MACHI 36 115#define SROM_W0_MACMID 37 116#define SROM_W0_MACLO 38 117 118/* Words 39-41: enet0 MAC address */ 119#define SROM_E0_MACHI 39 120#define SROM_E0_MACMID 40 121#define SROM_E0_MACLO 41 122 123/* Words 42-44: enet1 MAC address */ 124#define SROM_E1_MACHI 42 125#define SROM_E1_MACMID 43 126#define SROM_E1_MACLO 44 127 128/* Words 42-44: wireless1 MAC address on 4309 */ 129#define SROM_W1_MACHI 42 130#define SROM_W1_MACMID 43 131#define SROM_W1_MACLO 44 132 133#define SROM_EPHY 45 134 135/* Word 46: BdRev & Antennas0/1 & ccLock for 430x */ 136#define SROM_REV_AA_LOCK 46 137 138/* Words 47-51 wl0 PA bx */ 139#define SROM_WL0_PAB0 47 140#define SROM_WL0_PAB1 48 141#define SROM_WL0_PAB2 49 142#define SROM_WL0_PAB3 50 143#define SROM_WL0_PAB4 51 144 145/* Word 52: wl0/wl1 MaxPower */ 146#define SROM_WL_MAXPWR 52 147 148/* Words 53-55 wl1 PA bx */ 149#define SROM_WL1_PAB0 53 150#define SROM_WL1_PAB1 54 151#define SROM_WL1_PAB2 55 152 153/* Woprd 56: itt */ 154#define SROM_ITT 56 155 156/* Words 59-62: OEM Space */ 157#define SROM_WL_OEM 59 158#define SROM_OEM_SIZE 4 159 160/* Contents for the srom */ 161 162#define BU4710_SSID 0x0400 163#define VSIM4710_SSID 0x0401 164#define QT4710_SSID 0x0402 165 166#define BU4610_SSID 0x0403 167#define VSIM4610_SSID 0x0404 168 169#define BU4307_SSID 0x0405 170#define BCM94301CB_SSID 0x0406 171#define BCM94301MP_SSID 0x0407 172#define BCM94307MP_SSID 0x0408 173#define AP4307_SSID 0x0409 174 175#define BU4309_SSID 0x040a 176#define BCM94309CB_SSID 0x040b 177#define BCM94309MP_SSID 0x040c 178#define AP4309_SSID 0x040d 179 180#define BU4312_SSID 0x048a 181 182#define BU4402_SSID 0x4402 183 184#define CLASS_OTHER 0x8000 185#define CLASS_ETHER 0x0000 186#define CLASS_NET 0x0002 187#define CLASS_COMM 0x0007 188#define CLASS_MODEM 0x0300 189#define CLASS_MIPS 0x3000 190#define CLASS_PROC 0x000b 191#define CLASS_FLASH 0x0100 192#define CLASS_MEM 0x0005 193#define CLASS_SERIALBUS 0x000c 194#define CLASS_OHCI 0x0310 195 196/* Broadcom IEEE MAC addresses are 00:90:4c:xx:xx:xx */ 197#define MACHI 0x90 198 199#define MACMID_BU4710I 0x4c17 200#define MACMID_BU4710E0 0x4c18 201#define MACMID_BU4710E1 0x4c19 202 203#define MACMID_94710R1I 0x4c1a 204#define MACMID_94710R1E0 0x4c1b 205#define MACMID_94710R1E1 0x4c1c 206 207#define MACMID_94710R4I 0x4c1d 208#define MACMID_94710R4E0 0x4c1e 209#define MACMID_94710R4E1 0x4c1f 210 211#define MACMID_94710DEVI 0x4c20 212#define MACMID_94710DEVE0 0x4c21 213#define MACMID_94710DEVE1 0x4c22 214 215#define MACMID_BU4402 0x4c23 216 217#define MACMID_BU4610I 0x4c24 218#define MACMID_BU4610E0 0x4c25 219#define MACMID_BU4610E1 0x4c26 220 221#define MACMID_BU4307W 0x4c27 222#define MACMID_BU4307E 0x4c28 223 224#define MACMID_94301CB 0x4c29 225 226#define MACMID_94301MP 0x4c2a 227 228#define MACMID_94307MPW 0x4c2b 229#define MACMID_94307MPE 0x4c2c 230 231#define MACMID_AP4307W 0x4c2d 232#define MACMID_AP4307E 0x4c2e 233 234#define MACMID_BU4309W0 0x4c2f 235#define MACMID_BU4309W1 0x4c30 236#define MACMID_BU4309E 0x4c31 237 238#define MACMID_94309CBW0 0x4c32 239#define MACMID_94309CBW1 0x4c33 240 241#define MACMID_94309MPW0 0x4c34 242#define MACMID_94309MPW1 0x4c35 243#define MACMID_94309MPE 0x4c36 244 245#define MACMID_BU4401 0x4c37 246 247/* Enet phy settings one or two singles or a dual */ 248/* Bits 4-0 : MII address for enet0 (0x1f for not there */ 249/* Bits 9-5 : MII address for enet1 (0x1f for not there */ 250/* Bit 14 : Mdio for enet0 */ 251/* Bit 15 : Mdio for enet1 */ 252 253/* bu4710 with only one phy on enet1 with address 7: */ 254#define SROM_EPHY_ONE 0x80ff 255 256/* bu4710 with two individual phys, at 6 and 7, */ 257/* each mdio connected to its own mac: */ 258#define SROM_EPHY_TWO 0x80e6 259 260/* bu4710 with a dual phy addresses 0 & 1, mdio-connected to enet0 */ 261#define SROM_EPHY_DUAL 0x0001 262 263/* r1 board with a dual phy at 0, 1 (NOT swapped and mdc0 */ 264#define SROM_EPHY_R1 0x0010 265 266/* r4 board with a single phy on enet0 at address 5 and a switch */ 267/* chip on enet1 (speciall case: 0x1e */ 268#define SROM_EPHY_R4 0x83e5 269 270/* 4402 uses an internal phy at phyaddr 1; want mdcport == coreunit == 0 */ 271#define SROM_EPHY_INTERNAL 0x0001 272 273/* 4307 uses an external phy at phyaddr 0; want mdcport == coreunit == 0 */ 274#define SROM_EPHY_ZERO 0x0000 275 276#define SROM_VERS 0x0001 277 278 279#endif /* _SBSPROM_H */ 280