1/* 2 * BCM47XX Sonics SiliconBackplane embedded ram core 3 * 4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id: sbsocram.h,v 13.15.20.2 2010/03/06 03:54:16 Exp $ 19 */ 20 21#ifndef _SBSOCRAM_H 22#define _SBSOCRAM_H 23 24#ifndef _LANGUAGE_ASSEMBLY 25 26/* cpp contortions to concatenate w/arg prescan */ 27#ifndef PAD 28#define _PADLINE(line) pad ## line 29#define _XSTR(line) _PADLINE(line) 30#define PAD _XSTR(__LINE__) 31#endif /* PAD */ 32 33/* Memcsocram core registers */ 34typedef volatile struct sbsocramregs { 35 uint32 coreinfo; 36 uint32 bwalloc; 37 uint32 extracoreinfo; 38 uint32 biststat; 39 uint32 bankidx; 40 uint32 standbyctrl; 41 42 uint32 errlogstatus; /* rev 6 */ 43 uint32 errlogaddr; /* rev 6 */ 44 /* used for patching rev 3 & 5 */ 45 uint32 cambankidx; 46 uint32 cambankstandbyctrl; 47 uint32 cambankpatchctrl; 48 uint32 cambankpatchtblbaseaddr; 49 uint32 cambankcmdreg; 50 uint32 cambankdatareg; 51 uint32 cambankmaskreg; 52 uint32 PAD[1]; 53 uint32 bankinfo; /* corev 8 */ 54 uint32 PAD[15]; 55 uint32 extmemconfig; 56 uint32 extmemparitycsr; 57 uint32 extmemparityerrdata; 58 uint32 extmemparityerrcnt; 59 uint32 extmemwrctrlandsize; 60 uint32 PAD[84]; 61 uint32 workaround; 62 uint32 pwrctl; /* corerev >= 2 */ 63} sbsocramregs_t; 64 65#endif /* _LANGUAGE_ASSEMBLY */ 66 67/* Register offsets */ 68#define SR_COREINFO 0x00 69#define SR_BWALLOC 0x04 70#define SR_BISTSTAT 0x0c 71#define SR_BANKINDEX 0x10 72#define SR_BANKSTBYCTL 0x14 73#define SR_PWRCTL 0x1e8 74 75/* Coreinfo register */ 76#define SRCI_PT_MASK 0x00070000 /* corerev >= 6; port type[18:16] */ 77#define SRCI_PT_SHIFT 16 78/* port types : SRCI_PT_<processorPT>_<backplanePT> */ 79#define SRCI_PT_OCP_OCP 0 80#define SRCI_PT_AXI_OCP 1 81#define SRCI_PT_ARM7AHB_OCP 2 82#define SRCI_PT_CM3AHB_OCP 3 83#define SRCI_PT_AXI_AXI 4 84#define SRCI_PT_AHB_AXI 5 85/* corerev >= 3 */ 86#define SRCI_LSS_MASK 0x00f00000 87#define SRCI_LSS_SHIFT 20 88#define SRCI_LRS_MASK 0x0f000000 89#define SRCI_LRS_SHIFT 24 90 91/* In corerev 0, the memory size is 2 to the power of the 92 * base plus 16 plus to the contents of the memsize field plus 1. 93 */ 94#define SRCI_MS0_MASK 0xf 95#define SR_MS0_BASE 16 96 97/* 98 * In corerev 1 the bank size is 2 ^ the bank size field plus 14, 99 * the memory size is number of banks times bank size. 100 * The same applies to rom size. 101 */ 102#define SRCI_ROMNB_MASK 0xf000 103#define SRCI_ROMNB_SHIFT 12 104#define SRCI_ROMBSZ_MASK 0xf00 105#define SRCI_ROMBSZ_SHIFT 8 106#define SRCI_SRNB_MASK 0xf0 107#define SRCI_SRNB_SHIFT 4 108#define SRCI_SRBSZ_MASK 0xf 109#define SRCI_SRBSZ_SHIFT 0 110 111#define SR_BSZ_BASE 14 112 113/* Standby control register */ 114#define SRSC_SBYOVR_MASK 0x80000000 115#define SRSC_SBYOVR_SHIFT 31 116#define SRSC_SBYOVRVAL_MASK 0x60000000 117#define SRSC_SBYOVRVAL_SHIFT 29 118#define SRSC_SBYEN_MASK 0x01000000 /* rev >= 3 */ 119#define SRSC_SBYEN_SHIFT 24 120 121/* Power control register */ 122#define SRPC_PMU_STBYDIS_MASK 0x00000010 /* rev >= 3 */ 123#define SRPC_PMU_STBYDIS_SHIFT 4 124#define SRPC_STBYOVRVAL_MASK 0x00000008 125#define SRPC_STBYOVRVAL_SHIFT 3 126#define SRPC_STBYOVR_MASK 0x00000007 127#define SRPC_STBYOVR_SHIFT 0 128 129/* Extra core capability register */ 130#define SRECC_NUM_BANKS_MASK 0x000000F0 131#define SRECC_NUM_BANKS_SHIFT 4 132#define SRECC_BANKSIZE_MASK 0x0000000F 133#define SRECC_BANKSIZE_SHIFT 0 134 135#define SRECC_BANKSIZE(value) (1 << (value)) 136 137/* CAM bank patch control */ 138#define SRCBPC_PATCHENABLE 0x80000000 139 140#define SRP_ADDRESS 0x0001FFFC 141#define SRP_VALID 0x8000 142 143/* CAM bank command reg */ 144#define SRCMD_WRITE 0x00020000 145#define SRCMD_READ 0x00010000 146#define SRCMD_DONE 0x80000000 147 148#define SRCMD_DONE_DLY 1000 149 150/* bankidx and bankinfo reg defines corerev >= 8 */ 151#define SOCRAM_BANKINFO_SZMASK 0x3f 152#define SOCRAM_BANKIDX_ROM_MASK 0x100 153 154#define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8 155/* socram bankinfo memtype */ 156#define SOCRAM_MEMTYPE_RAM 0 157#define SOCRAM_MEMTYPE_R0M 1 158#define SOCRAM_MEMTYPE_DEVRAM 2 159 160#define SOCRAM_BANKINFO_REG 0x40 161#define SOCRAM_BANKIDX_REG 0x10 162#define SOCRAM_BANKINFO_STDBY_MASK 0x400 163#define SOCRAM_BANKINFO_STDBY_TIMER 0x800 164 165/* bankinfo rev >= 10 */ 166#define SOCRAM_BANKINFO_DEVRAMSEL_SHIFT 13 167#define SOCRAM_BANKINFO_DEVRAMSEL_MASK 0x2000 168#define SOCRAM_BANKINFO_DEVRAMPRO_SHIFT 14 169#define SOCRAM_BANKINFO_DEVRAMPRO_MASK 0x4000 170 171/* extracoreinfo register */ 172#define SOCRAM_DEVRAMBANK_MASK 0xF000 173#define SOCRAM_DEVRAMBANK_SHIFT 12 174 175/* bank info to calculate bank size */ 176#define SOCRAM_BANKINFO_SZBASE 8192 177#define SOCRAM_BANKSIZE_SHIFT 13 /* SOCRAM_BANKINFO_SZBASE */ 178 179 180#endif /* _SBSOCRAM_H */ 181