1/* 2 * Generic Broadcom Home Networking Division (HND) DMA engine HW interface 3 * This supports the following chips: BCM42xx, 44xx, 47xx . 4 * 5 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 14 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 16 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 17 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $Id: sbhnddma.h,v 13.20.12.3 2011/01/27 19:03:20 Exp $ 20 */ 21 22#ifndef _sbhnddma_h_ 23#define _sbhnddma_h_ 24 25/* DMA structure: 26 * support two DMA engines: 32 bits address or 64 bit addressing 27 * basic DMA register set is per channel(transmit or receive) 28 * a pair of channels is defined for convenience 29 */ 30 31 32/* 32 bits addressing */ 33 34/* dma registers per channel(xmt or rcv) */ 35typedef volatile struct { 36 uint32 control; /* enable, et al */ 37 uint32 addr; /* descriptor ring base address (4K aligned) */ 38 uint32 ptr; /* last descriptor posted to chip */ 39 uint32 status; /* current active descriptor, et al */ 40} dma32regs_t; 41 42typedef volatile struct { 43 dma32regs_t xmt; /* dma tx channel */ 44 dma32regs_t rcv; /* dma rx channel */ 45} dma32regp_t; 46 47typedef volatile struct { /* diag access */ 48 uint32 fifoaddr; /* diag address */ 49 uint32 fifodatalow; /* low 32bits of data */ 50 uint32 fifodatahigh; /* high 32bits of data */ 51 uint32 pad; /* reserved */ 52} dma32diag_t; 53 54/* 55 * DMA Descriptor 56 * Descriptors are only read by the hardware, never written back. 57 */ 58typedef volatile struct { 59 uint32 ctrl; /* misc control bits & bufcount */ 60 uint32 addr; /* data buffer address */ 61} dma32dd_t; 62 63/* 64 * Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page. 65 */ 66#define D32RINGALIGN_BITS 12 67#define D32MAXRINGSZ (1 << D32RINGALIGN_BITS) 68#define D32RINGALIGN (1 << D32RINGALIGN_BITS) 69 70#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t)) 71 72/* transmit channel control */ 73#define XC_XE ((uint32)1 << 0) /* transmit enable */ 74#define XC_SE ((uint32)1 << 1) /* transmit suspend request */ 75#define XC_LE ((uint32)1 << 2) /* loopback enable */ 76#define XC_FL ((uint32)1 << 4) /* flush request */ 77#define XC_PD ((uint32)1 << 11) /* parity check disable */ 78#define XC_AE ((uint32)3 << 16) /* address extension bits */ 79#define XC_AE_SHIFT 16 80 81/* transmit descriptor table pointer */ 82#define XP_LD_MASK 0xfff /* last valid descriptor */ 83 84/* transmit channel status */ 85#define XS_CD_MASK 0x0fff /* current descriptor pointer */ 86#define XS_XS_MASK 0xf000 /* transmit state */ 87#define XS_XS_SHIFT 12 88#define XS_XS_DISABLED 0x0000 /* disabled */ 89#define XS_XS_ACTIVE 0x1000 /* active */ 90#define XS_XS_IDLE 0x2000 /* idle wait */ 91#define XS_XS_STOPPED 0x3000 /* stopped */ 92#define XS_XS_SUSP 0x4000 /* suspend pending */ 93#define XS_XE_MASK 0xf0000 /* transmit errors */ 94#define XS_XE_SHIFT 16 95#define XS_XE_NOERR 0x00000 /* no error */ 96#define XS_XE_DPE 0x10000 /* descriptor protocol error */ 97#define XS_XE_DFU 0x20000 /* data fifo underrun */ 98#define XS_XE_BEBR 0x30000 /* bus error on buffer read */ 99#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */ 100#define XS_AD_MASK 0xfff00000 /* active descriptor */ 101#define XS_AD_SHIFT 20 102 103/* receive channel control */ 104#define RC_RE ((uint32)1 << 0) /* receive enable */ 105#define RC_RO_MASK 0xfe /* receive frame offset */ 106#define RC_RO_SHIFT 1 107#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */ 108#define RC_SH ((uint32)1 << 9) /* separate rx header descriptor enable */ 109#define RC_OC ((uint32)1 << 10) /* overflow continue */ 110#define RC_PD ((uint32)1 << 11) /* parity check disable */ 111#define RC_AE ((uint32)3 << 16) /* address extension bits */ 112#define RC_AE_SHIFT 16 113 114/* receive descriptor table pointer */ 115#define RP_LD_MASK 0xfff /* last valid descriptor */ 116 117/* receive channel status */ 118#define RS_CD_MASK 0x0fff /* current descriptor pointer */ 119#define RS_RS_MASK 0xf000 /* receive state */ 120#define RS_RS_SHIFT 12 121#define RS_RS_DISABLED 0x0000 /* disabled */ 122#define RS_RS_ACTIVE 0x1000 /* active */ 123#define RS_RS_IDLE 0x2000 /* idle wait */ 124#define RS_RS_STOPPED 0x3000 /* reserved */ 125#define RS_RE_MASK 0xf0000 /* receive errors */ 126#define RS_RE_SHIFT 16 127#define RS_RE_NOERR 0x00000 /* no error */ 128#define RS_RE_DPE 0x10000 /* descriptor protocol error */ 129#define RS_RE_DFO 0x20000 /* data fifo overflow */ 130#define RS_RE_BEBW 0x30000 /* bus error on buffer write */ 131#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */ 132#define RS_AD_MASK 0xfff00000 /* active descriptor */ 133#define RS_AD_SHIFT 20 134 135/* fifoaddr */ 136#define FA_OFF_MASK 0xffff /* offset */ 137#define FA_SEL_MASK 0xf0000 /* select */ 138#define FA_SEL_SHIFT 16 139#define FA_SEL_XDD 0x00000 /* transmit dma data */ 140#define FA_SEL_XDP 0x10000 /* transmit dma pointers */ 141#define FA_SEL_RDD 0x40000 /* receive dma data */ 142#define FA_SEL_RDP 0x50000 /* receive dma pointers */ 143#define FA_SEL_XFD 0x80000 /* transmit fifo data */ 144#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */ 145#define FA_SEL_RFD 0xc0000 /* receive fifo data */ 146#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */ 147#define FA_SEL_RSD 0xe0000 /* receive frame status data */ 148#define FA_SEL_RSP 0xf0000 /* receive frame status pointers */ 149 150/* descriptor control flags */ 151#define CTRL_BC_MASK 0x00001fff /* buffer byte count, real data len must <= 4KB */ 152#define CTRL_AE ((uint32)3 << 16) /* address extension bits */ 153#define CTRL_AE_SHIFT 16 154#define CTRL_PARITY ((uint32)3 << 18) /* parity bit */ 155#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */ 156#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */ 157#define CTRL_EOF ((uint32)1 << 30) /* end of frame */ 158#define CTRL_SOF ((uint32)1 << 31) /* start of frame */ 159 160/* control flags in the range [27:20] are core-specific and not defined here */ 161#define CTRL_CORE_MASK 0x0ff00000 162 163/* 64 bits addressing */ 164 165/* dma registers per channel(xmt or rcv) */ 166typedef volatile struct { 167 uint32 control; /* enable, et al */ 168 uint32 ptr; /* last descriptor posted to chip */ 169 uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */ 170 uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */ 171 uint32 status0; /* current descriptor, xmt state */ 172 uint32 status1; /* active descriptor, xmt error */ 173} dma64regs_t; 174 175typedef volatile struct { 176 dma64regs_t tx; /* dma64 tx channel */ 177 dma64regs_t rx; /* dma64 rx channel */ 178} dma64regp_t; 179 180typedef volatile struct { /* diag access */ 181 uint32 fifoaddr; /* diag address */ 182 uint32 fifodatalow; /* low 32bits of data */ 183 uint32 fifodatahigh; /* high 32bits of data */ 184 uint32 pad; /* reserved */ 185} dma64diag_t; 186 187/* 188 * DMA Descriptor 189 * Descriptors are only read by the hardware, never written back. 190 */ 191typedef volatile struct { 192 uint32 ctrl1; /* misc control bits & bufcount */ 193 uint32 ctrl2; /* buffer count and address extension */ 194 uint32 addrlow; /* memory address of the date buffer, bits 31:0 */ 195 uint32 addrhigh; /* memory address of the date buffer, bits 63:32 */ 196} dma64dd_t; 197 198/* 199 * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss. 200 */ 201#define D64RINGALIGN_BITS 13 202#define D64MAXRINGSZ (1 << D64RINGALIGN_BITS) 203#define D64RINGALIGN (1 << D64RINGALIGN_BITS) 204 205#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t)) 206 207/* transmit channel control */ 208#define D64_XC_XE 0x00000001 /* transmit enable */ 209#define D64_XC_SE 0x00000002 /* transmit suspend request */ 210#define D64_XC_LE 0x00000004 /* loopback enable */ 211#define D64_XC_FL 0x00000010 /* flush request */ 212#define D64_XC_PD 0x00000800 /* parity check disable */ 213#define D64_XC_AE 0x00030000 /* address extension bits */ 214#define D64_XC_AE_SHIFT 16 215 216/* transmit descriptor table pointer */ 217#define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */ 218 219/* transmit channel status */ 220#define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */ 221#define D64_XS0_XS_MASK 0xf0000000 /* transmit state */ 222#define D64_XS0_XS_SHIFT 28 223#define D64_XS0_XS_DISABLED 0x00000000 /* disabled */ 224#define D64_XS0_XS_ACTIVE 0x10000000 /* active */ 225#define D64_XS0_XS_IDLE 0x20000000 /* idle wait */ 226#define D64_XS0_XS_STOPPED 0x30000000 /* stopped */ 227#define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */ 228 229#define D64_XS1_AD_MASK 0x00001fff /* active descriptor */ 230#define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */ 231#define D64_XS1_XE_SHIFT 28 232#define D64_XS1_XE_NOERR 0x00000000 /* no error */ 233#define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */ 234#define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */ 235#define D64_XS1_XE_DTE 0x30000000 /* data transfer error */ 236#define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */ 237#define D64_XS1_XE_COREE 0x50000000 /* core error */ 238 239/* receive channel control */ 240#define D64_RC_RE 0x00000001 /* receive enable */ 241#define D64_RC_RO_MASK 0x000000fe /* receive frame offset */ 242#define D64_RC_RO_SHIFT 1 243#define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */ 244#define D64_RC_SH 0x00000200 /* separate rx header descriptor enable */ 245#define D64_RC_OC 0x00000400 /* overflow continue */ 246#define D64_RC_PD 0x00000800 /* parity check disable */ 247#define D64_RC_AE 0x00030000 /* address extension bits */ 248#define D64_RC_AE_SHIFT 16 249 250/* flags for dma controller */ 251#define DMA_CTRL_PEN (1 << 0) /* partity enable */ 252#define DMA_CTRL_ROC (1 << 1) /* rx overflow continue */ 253#define DMA_CTRL_RXMULTI (1 << 2) /* allow rx scatter to multiple descriptors */ 254#define DMA_CTRL_UNFRAMED (1 << 3) /* Unframed Rx/Tx data */ 255#define DMA_CTRL_USB_BOUNDRY4KB_WAR (1 << 4) 256#define DMA_CTRL_DMA_AVOIDANCE_WAR (1 << 5) /* DMA avoidance WAR for 4331 */ 257 258/* receive descriptor table pointer */ 259#define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */ 260 261/* receive channel status */ 262#define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */ 263#define D64_RS0_RS_MASK 0xf0000000 /* receive state */ 264#define D64_RS0_RS_SHIFT 28 265#define D64_RS0_RS_DISABLED 0x00000000 /* disabled */ 266#define D64_RS0_RS_ACTIVE 0x10000000 /* active */ 267#define D64_RS0_RS_IDLE 0x20000000 /* idle wait */ 268#define D64_RS0_RS_STOPPED 0x30000000 /* stopped */ 269#define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */ 270 271#define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */ 272#define D64_RS1_RE_MASK 0xf0000000 /* receive errors */ 273#define D64_RS1_RE_SHIFT 28 274#define D64_RS1_RE_NOERR 0x00000000 /* no error */ 275#define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */ 276#define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */ 277#define D64_RS1_RE_DTE 0x30000000 /* data transfer error */ 278#define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */ 279#define D64_RS1_RE_COREE 0x50000000 /* core error */ 280 281/* fifoaddr */ 282#define D64_FA_OFF_MASK 0xffff /* offset */ 283#define D64_FA_SEL_MASK 0xf0000 /* select */ 284#define D64_FA_SEL_SHIFT 16 285#define D64_FA_SEL_XDD 0x00000 /* transmit dma data */ 286#define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */ 287#define D64_FA_SEL_RDD 0x40000 /* receive dma data */ 288#define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */ 289#define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */ 290#define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */ 291#define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */ 292#define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */ 293#define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */ 294#define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */ 295 296/* descriptor control flags 1 */ 297#define D64_CTRL_COREFLAGS 0x0ff00000 /* core specific flags */ 298#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */ 299#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */ 300#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */ 301#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */ 302 303/* descriptor control flags 2 */ 304#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count. real data len must <= 16KB */ 305#define D64_CTRL2_AE 0x00030000 /* address extension bits */ 306#define D64_CTRL2_AE_SHIFT 16 307#define D64_CTRL2_PARITY 0x00040000 /* parity bit */ 308 309/* control flags in the range [27:20] are core-specific and not defined here */ 310#define D64_CTRL_CORE_MASK 0x0ff00000 311 312#define D64_RX_FRM_STS_LEN 0x0000ffff /* frame length mask */ 313#define D64_RX_FRM_STS_OVFL 0x00800000 /* RxOverFlow */ 314#define D64_RX_FRM_STS_DSCRCNT 0x0f000000 /* no. of descriptors used - 1, d11corerev >= 22 */ 315#define D64_RX_FRM_STS_DATATYPE 0xf0000000 /* core-dependent data type */ 316 317/* receive frame status */ 318typedef volatile struct { 319 uint16 len; 320 uint16 flags; 321} dma_rxh_t; 322 323#endif /* _sbhnddma_h_ */ 324