1/* 2 * SiliconBackplane Chipcommon core hardware definitions. 3 * 4 * The chipcommon core provides chip identification, SB control, 5 * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer, 6 * GPIO interface, extbus, and support for serial and parallel flashes. 7 * 8 * $Id: sbchipc.h,v 13.173.4.11 2011-02-11 20:59:28 Exp $ 9 * 10 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved. 11 * 12 * Permission to use, copy, modify, and/or distribute this software for any 13 * purpose with or without fee is hereby granted, provided that the above 14 * copyright notice and this permission notice appear in all copies. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 17 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 20 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 21 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 22 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 23 */ 24 25#ifndef _SBCHIPC_H 26#define _SBCHIPC_H 27 28#ifndef _LANGUAGE_ASSEMBLY 29 30/* cpp contortions to concatenate w/arg prescan */ 31#ifndef PAD 32#define _PADLINE(line) pad ## line 33#define _XSTR(line) _PADLINE(line) 34#define PAD _XSTR(__LINE__) 35#endif /* PAD */ 36 37typedef struct eci_prerev35 { 38 uint32 eci_output; 39 uint32 eci_control; 40 uint32 eci_inputlo; 41 uint32 eci_inputmi; 42 uint32 eci_inputhi; 43 uint32 eci_inputintpolaritylo; 44 uint32 eci_inputintpolaritymi; 45 uint32 eci_inputintpolarityhi; 46 uint32 eci_intmasklo; 47 uint32 eci_intmaskmi; 48 uint32 eci_intmaskhi; 49 uint32 eci_eventlo; 50 uint32 eci_eventmi; 51 uint32 eci_eventhi; 52 uint32 eci_eventmasklo; 53 uint32 eci_eventmaskmi; 54 uint32 eci_eventmaskhi; 55 uint32 PAD[3]; 56} eci_prerev35_t; 57 58typedef struct eci_rev35 { 59 uint32 eci_outputlo; 60 uint32 eci_outputhi; 61 uint32 eci_controllo; 62 uint32 eci_controlhi; 63 uint32 eci_inputlo; 64 uint32 eci_inputhi; 65 uint32 eci_inputintpolaritylo; 66 uint32 eci_inputintpolarityhi; 67 uint32 eci_intmasklo; 68 uint32 eci_intmaskhi; 69 uint32 eci_eventlo; 70 uint32 eci_eventhi; 71 uint32 eci_eventmasklo; 72 uint32 eci_eventmaskhi; 73 uint32 eci_auxtx; 74 uint32 eci_auxrx; 75 uint32 eci_datatag; 76 uint32 eci_uartescvalue; 77 uint32 eci_autobaudctr; 78 uint32 eci_uartfifolevel; 79} eci_rev35_t; 80 81typedef struct flash_config { 82 uint32 PAD[19]; 83 /* Flash struct configuration registers (0x18c) for BCM4706 (corerev = 31) */ 84 uint32 flashstrconfig; 85} flash_config_t; 86 87typedef volatile struct { 88 uint32 chipid; /* 0x0 */ 89 uint32 capabilities; 90 uint32 corecontrol; /* corerev >= 1 */ 91 uint32 bist; 92 93 /* OTP */ 94 uint32 otpstatus; /* 0x10, corerev >= 10 */ 95 uint32 otpcontrol; 96 uint32 otpprog; 97 uint32 otplayout; /* corerev >= 23 */ 98 99 /* Interrupt control */ 100 uint32 intstatus; /* 0x20 */ 101 uint32 intmask; 102 103 /* Chip specific regs */ 104 uint32 chipcontrol; /* 0x28, rev >= 11 */ 105 uint32 chipstatus; /* 0x2c, rev >= 11 */ 106 107 /* Jtag Master */ 108 uint32 jtagcmd; /* 0x30, rev >= 10 */ 109 uint32 jtagir; 110 uint32 jtagdr; 111 uint32 jtagctrl; 112 113 /* serial flash interface registers */ 114 uint32 flashcontrol; /* 0x40 */ 115 uint32 flashaddress; 116 uint32 flashdata; 117 uint32 otplayoutextension; /* rev >= 35 */ 118 119 /* Silicon backplane configuration broadcast control */ 120 uint32 broadcastaddress; /* 0x50 */ 121 uint32 broadcastdata; 122 123 /* gpio - cleared only by power-on-reset */ 124 uint32 gpiopullup; /* 0x58, corerev >= 20 */ 125 uint32 gpiopulldown; /* 0x5c, corerev >= 20 */ 126 uint32 gpioin; /* 0x60 */ 127 uint32 gpioout; /* 0x64 */ 128 uint32 gpioouten; /* 0x68 */ 129 uint32 gpiocontrol; /* 0x6C */ 130 uint32 gpiointpolarity; /* 0x70 */ 131 uint32 gpiointmask; /* 0x74 */ 132 133 /* GPIO events corerev >= 11 */ 134 uint32 gpioevent; 135 uint32 gpioeventintmask; 136 137 /* Watchdog timer */ 138 uint32 watchdog; /* 0x80 */ 139 140 /* GPIO events corerev >= 11 */ 141 uint32 gpioeventintpolarity; 142 143 /* GPIO based LED powersave registers corerev >= 16 */ 144 uint32 gpiotimerval; /* 0x88 */ 145 uint32 gpiotimeroutmask; 146 147 /* clock control */ 148 uint32 clockcontrol_n; /* 0x90 */ 149 uint32 clockcontrol_sb; /* aka m0 */ 150 uint32 clockcontrol_pci; /* aka m1 */ 151 uint32 clockcontrol_m2; /* mii/uart/mipsref */ 152 uint32 clockcontrol_m3; /* cpu */ 153 uint32 clkdiv; /* corerev >= 3 */ 154 uint32 gpiodebugsel; /* corerev >= 28 */ 155 uint32 capabilities_ext; /* 0xac */ 156 157 /* pll delay registers (corerev >= 4) */ 158 uint32 pll_on_delay; /* 0xb0 */ 159 uint32 fref_sel_delay; 160 uint32 slow_clk_ctl; /* 5 < corerev < 10 */ 161 uint32 PAD; 162 163 /* Instaclock registers (corerev >= 10) */ 164 uint32 system_clk_ctl; /* 0xc0 */ 165 uint32 clkstatestretch; 166 uint32 PAD[2]; 167 168 /* Indirect backplane access (corerev >= 22) */ 169 uint32 bp_addrlow; /* 0xd0 */ 170 uint32 bp_addrhigh; 171 uint32 bp_data; 172 uint32 PAD; 173 uint32 bp_indaccess; 174 uint32 PAD[3]; 175 176 /* More clock dividers (corerev >= 32) */ 177 uint32 clkdiv2; 178 uint32 PAD[2]; 179 180 /* In AI chips, pointer to erom */ 181 uint32 eromptr; /* 0xfc */ 182 183 /* ExtBus control registers (corerev >= 3) */ 184 uint32 pcmcia_config; /* 0x100 */ 185 uint32 pcmcia_memwait; 186 uint32 pcmcia_attrwait; 187 uint32 pcmcia_iowait; 188 uint32 ide_config; 189 uint32 ide_memwait; 190 uint32 ide_attrwait; 191 uint32 ide_iowait; 192 uint32 prog_config; 193 uint32 prog_waitcount; 194 uint32 flash_config; 195 uint32 flash_waitcount; 196 uint32 SECI_config; /* 0x130 SECI configuration */ 197 uint32 SECI_status; 198 uint32 SECI_statusmask; 199 uint32 SECI_rxnibchanged; 200 201 union { /* 0x140 */ 202 /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */ 203 struct eci_prerev35 lt35; 204 struct eci_rev35 ge35; 205 /* Other interfaces */ 206 struct flash_config flashconf; 207 uint32 PAD[20]; 208 } eci; 209 210 /* SROM interface (corerev >= 32) */ 211 uint32 sromcontrol; /* 0x190 */ 212 uint32 sromaddress; 213 uint32 sromdata; 214 uint32 PAD[1]; /* 0x19C */ 215 /* NAND flash registers for BCM4706 (corerev = 31) */ 216 uint32 nflashctrl; /* 0x1a0 */ 217 uint32 nflashconf; 218 uint32 nflashcoladdr; 219 uint32 nflashrowaddr; 220 uint32 nflashdata; 221 uint32 nflashwaitcnt0; /* 0x1b4 */ 222 uint32 PAD[2]; 223 224 uint32 seci_uart_data; /* 0x1C0 */ 225 uint32 seci_uart_bauddiv; 226 uint32 seci_uart_fcr; 227 uint32 seci_uart_lcr; 228 uint32 seci_uart_mcr; 229 uint32 seci_uart_lsr; 230 uint32 seci_uart_msr; 231 uint32 seci_uart_baudadj; 232 /* Clock control and hardware workarounds (corerev >= 20) */ 233 uint32 clk_ctl_st; /* 0x1e0 */ 234 uint32 hw_war; 235 uint32 PAD[70]; 236 237 /* UARTs */ 238 uint8 uart0data; /* 0x300 */ 239 uint8 uart0imr; 240 uint8 uart0fcr; 241 uint8 uart0lcr; 242 uint8 uart0mcr; 243 uint8 uart0lsr; 244 uint8 uart0msr; 245 uint8 uart0scratch; 246 uint8 PAD[248]; /* corerev >= 1 */ 247 248 uint8 uart1data; /* 0x400 */ 249 uint8 uart1imr; 250 uint8 uart1fcr; 251 uint8 uart1lcr; 252 uint8 uart1mcr; 253 uint8 uart1lsr; 254 uint8 uart1msr; 255 uint8 uart1scratch; 256 uint32 PAD[126]; 257 258 /* PMU registers (corerev >= 20) */ 259 uint32 pmucontrol; /* 0x600 */ 260 uint32 pmucapabilities; 261 uint32 pmustatus; 262 uint32 res_state; 263 uint32 res_pending; 264 uint32 pmutimer; 265 uint32 min_res_mask; 266 uint32 max_res_mask; 267 uint32 res_table_sel; 268 uint32 res_dep_mask; 269 uint32 res_updn_timer; 270 uint32 res_timer; 271 uint32 clkstretch; 272 uint32 pmuwatchdog; 273 uint32 gpiosel; /* 0x638, rev >= 1 */ 274 uint32 gpioenable; /* 0x63c, rev >= 1 */ 275 uint32 res_req_timer_sel; 276 uint32 res_req_timer; 277 uint32 res_req_mask; 278 uint32 PAD; 279 uint32 chipcontrol_addr; /* 0x650 */ 280 uint32 chipcontrol_data; /* 0x654 */ 281 uint32 regcontrol_addr; 282 uint32 regcontrol_data; 283 uint32 pllcontrol_addr; 284 uint32 pllcontrol_data; 285 uint32 pmustrapopt; /* 0x668, corerev >= 28 */ 286 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ 287 uint32 PAD[100]; 288 uint16 sromotp[512]; /* 0x800 */ 289 /* Nand flash MLC controller registers (corerev >= 38) */ 290 uint32 nand_revision; /* 0xC00 */ 291 uint32 nand_cmd_start; 292 uint32 nand_cmd_addr_x; 293 uint32 nand_cmd_addr; 294 uint32 nand_cmd_end_addr; 295 uint32 nand_cs_nand_select; 296 uint32 nand_cs_nand_xor; 297 uint32 PAD; 298 uint32 nand_spare_rd0; 299 uint32 nand_spare_rd4; 300 uint32 nand_spare_rd8; 301 uint32 nand_spare_rd12; 302 uint32 nand_spare_wr0; 303 uint32 nand_spare_wr4; 304 uint32 nand_spare_wr8; 305 uint32 nand_spare_wr12; 306 uint32 nand_acc_control; 307 uint32 PAD; 308 uint32 nand_config; 309 uint32 PAD; 310 uint32 nand_timing_1; 311 uint32 nand_timing_2; 312 uint32 nand_semaphore; 313 uint32 PAD; 314 uint32 nand_devid; 315 uint32 nand_devid_x; 316 uint32 nand_block_lock_status; 317 uint32 nand_intfc_status; 318 uint32 nand_ecc_corr_addr_x; 319 uint32 nand_ecc_corr_addr; 320 uint32 nand_ecc_unc_addr_x; 321 uint32 nand_ecc_unc_addr; 322 uint32 nand_read_error_count; 323 uint32 nand_corr_stat_threshold; 324 uint32 PAD[2]; 325 uint32 nand_read_addr_x; 326 uint32 nand_read_addr; 327 uint32 nand_page_program_addr_x; 328 uint32 nand_page_program_addr; 329 uint32 nand_copy_back_addr_x; 330 uint32 nand_copy_back_addr; 331 uint32 nand_block_erase_addr_x; 332 uint32 nand_block_erase_addr; 333 uint32 nand_inv_read_addr_x; 334 uint32 nand_inv_read_addr; 335 uint32 PAD[2]; 336 uint32 nand_blk_wr_protect; 337 uint32 PAD[3]; 338 uint32 nand_acc_control_cs1; 339 uint32 nand_config_cs1; 340 uint32 nand_timing_1_cs1; 341 uint32 nand_timing_2_cs1; 342 uint32 PAD[20]; 343 uint32 nand_spare_rd16; 344 uint32 nand_spare_rd20; 345 uint32 nand_spare_rd24; 346 uint32 nand_spare_rd28; 347 uint32 nand_cache_addr; 348 uint32 nand_cache_data; 349 uint32 nand_ctrl_config; 350 uint32 nand_ctrl_status; 351} chipcregs_t; 352 353#endif /* _LANGUAGE_ASSEMBLY */ 354 355#if defined(IL_BIGENDIAN) && defined(BCMHND74K) 356/* Selective swapped defines for those registers we need in 357 * big-endian code. 358 */ 359#define CC_CHIPID 4 360#define CC_CAPABILITIES 0 361#define CC_CHIPST 0x28 362#define CC_EROMPTR 0xf8 363 364#else /* !IL_BIGENDIAN || !BCMHND74K */ 365 366#define CC_CHIPID 0 367#define CC_CAPABILITIES 4 368#define CC_CHIPST 0x2c 369#define CC_EROMPTR 0xfc 370 371#endif /* IL_BIGENDIAN && BCMHND74K */ 372 373#define CC_OTPST 0x10 374#define CC_JTAGCMD 0x30 375#define CC_JTAGIR 0x34 376#define CC_JTAGDR 0x38 377#define CC_JTAGCTRL 0x3c 378#define CC_GPIOPU 0x58 379#define CC_GPIOPD 0x5c 380#define CC_GPIOIN 0x60 381#define CC_GPIOOUT 0x64 382#define CC_GPIOOUTEN 0x68 383#define CC_GPIOCTRL 0x6c 384#define CC_GPIOPOL 0x70 385#define CC_GPIOINTM 0x74 386#define CC_WATCHDOG 0x80 387#define CC_CLKC_N 0x90 388#define CC_CLKC_M0 0x94 389#define CC_CLKC_M1 0x98 390#define CC_CLKC_M2 0x9c 391#define CC_CLKC_M3 0xa0 392#define CC_CLKDIV 0xa4 393#define CC_SYS_CLK_CTL 0xc0 394#define CC_CLK_CTL_ST SI_CLK_CTL_ST 395#define PMU_CTL 0x600 396#define PMU_CAP 0x604 397#define PMU_ST 0x608 398#define PMU_RES_STATE 0x60c 399#define PMU_TIMER 0x614 400#define PMU_MIN_RES_MASK 0x618 401#define PMU_MAX_RES_MASK 0x61c 402#define CC_CHIPCTL_ADDR 0x650 403#define CC_CHIPCTL_DATA 0x654 404#define PMU_REG_CONTROL_ADDR 0x658 405#define PMU_REG_CONTROL_DATA 0x65C 406#define PMU_PLL_CONTROL_ADDR 0x660 407#define PMU_PLL_CONTROL_DATA 0x664 408#define CC_SROM_OTP 0x800 /* SROM/OTP address space */ 409 410#ifdef NFLASH_SUPPORT 411/* NAND flash support */ 412#define CC_NAND_REVISION 0xC00 413#define CC_NAND_CMD_START 0xC04 414#define CC_NAND_CMD_ADDR 0xC0C 415#define CC_NAND_SPARE_RD_0 0xC20 416#define CC_NAND_SPARE_RD_4 0xC24 417#define CC_NAND_SPARE_RD_8 0xC28 418#define CC_NAND_SPARE_RD_C 0xC2C 419#define CC_NAND_CONFIG 0xC48 420#define CC_NAND_DEVID 0xC60 421#define CC_NAND_DEVID_EXT 0xC64 422#define CC_NAND_INTFC_STATUS 0xC6C 423#endif /* NFLASH_SUPPORT */ 424 425/* chipid */ 426#define CID_ID_MASK 0x0000ffff /* Chip Id mask */ 427#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */ 428#define CID_REV_SHIFT 16 /* Chip Revision shift */ 429#define CID_PKG_MASK 0x00f00000 /* Package Option mask */ 430#define CID_PKG_SHIFT 20 /* Package Option shift */ 431#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */ 432#define CID_CC_SHIFT 24 433#define CID_TYPE_MASK 0xf0000000 /* Chip Type */ 434#define CID_TYPE_SHIFT 28 435 436/* capabilities */ 437#define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */ 438#define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */ 439#define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */ 440#define CC_CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */ 441#define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */ 442#define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */ 443#define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */ 444#define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */ 445#define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */ 446#define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */ 447#define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ 448#define CC_CAP_PWR_CTL 0x00040000 /* Power control */ 449#define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */ 450#define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */ 451#define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */ 452#define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ 453#define CC_CAP_ROM 0x00800000 /* Internal boot rom active */ 454#define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */ 455#define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */ 456#define CC_CAP_ECI 0x20000000 /* ECI Present, rev >= 21 */ 457#define CC_CAP_SROM 0x40000000 /* Srom Present, rev >= 32 */ 458#define CC_CAP_NFLASH 0x80000000 /* Nand flash present, rev >= 35 */ 459 460#define CC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */ 461#define CC_CAP2_GSIO 0x00000002 /* GSIO (spi/i2c) present, rev >= 37 */ 462 463/* capabilities extension */ 464#define CC_CAP_EXT_SECI_PRESENT 0x00000001 /* SECI present */ 465 466/* PLL type */ 467#define PLL_NONE 0x00000000 468#define PLL_TYPE1 0x00010000 /* 48MHz base, 3 dividers */ 469#define PLL_TYPE2 0x00020000 /* 48MHz, 4 dividers */ 470#define PLL_TYPE3 0x00030000 /* 25MHz, 2 dividers */ 471#define PLL_TYPE4 0x00008000 /* 48MHz, 4 dividers */ 472#define PLL_TYPE5 0x00018000 /* 25MHz, 4 dividers */ 473#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */ 474#define PLL_TYPE7 0x00038000 /* 25MHz, 4 dividers */ 475 476/* ILP clock */ 477#define ILP_CLOCK 32000 478 479/* ALP clock on pre-PMU chips */ 480#define ALP_CLOCK 20000000 481 482/* HT clock */ 483#define HT_CLOCK 80000000 484 485/* corecontrol */ 486#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */ 487#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ 488#define CC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */ 489 490/* chipcontrol */ 491#define CHIPCTRL_4321A0_DEFAULT 0x3a4 492#define CHIPCTRL_4321A1_DEFAULT 0x0a4 493#define CHIPCTRL_4321_PLL_DOWN 0x800000 /* serdes PLL down override */ 494 495/* Fields in the otpstatus register in rev >= 21 */ 496#define OTPS_OL_MASK 0x000000ff 497#define OTPS_OL_MFG 0x00000001 /* manuf row is locked */ 498#define OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */ 499#define OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */ 500#define OTPS_OL_GU 0x00000008 /* general use region is locked */ 501#define OTPS_GUP_MASK 0x00000f00 502#define OTPS_GUP_SHIFT 8 503#define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */ 504#define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */ 505#define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */ 506#define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */ 507#define OTPS_READY 0x00001000 508#define OTPS_RV(x) (1 << (16 + (x))) /* redundancy entry valid */ 509#define OTPS_RV_MASK 0x0fff0000 510 511/* Fields in the otpcontrol register in rev >= 21 */ 512#define OTPC_PROGSEL 0x00000001 513#define OTPC_PCOUNT_MASK 0x0000000e 514#define OTPC_PCOUNT_SHIFT 1 515#define OTPC_VSEL_MASK 0x000000f0 516#define OTPC_VSEL_SHIFT 4 517#define OTPC_TMM_MASK 0x00000700 518#define OTPC_TMM_SHIFT 8 519#define OTPC_ODM 0x00000800 520#define OTPC_PROGEN 0x80000000 521 522/* Fields in otpprog in rev >= 21 and HND OTP */ 523#define OTPP_COL_MASK 0x000000ff 524#define OTPP_COL_SHIFT 0 525#define OTPP_ROW_MASK 0x0000ff00 526#define OTPP_ROW_SHIFT 8 527#define OTPP_OC_MASK 0x0f000000 528#define OTPP_OC_SHIFT 24 529#define OTPP_READERR 0x10000000 530#define OTPP_VALUE_MASK 0x20000000 531#define OTPP_VALUE_SHIFT 29 532#define OTPP_START_BUSY 0x80000000 533#define OTPP_READ 0x40000000 /* HND OTP */ 534 535/* otplayout reg corerev >= 36 */ 536#define OTP_CISFORMAT_NEW 0x80000000 537 538/* Opcodes for OTPP_OC field */ 539#define OTPPOC_READ 0 540#define OTPPOC_BIT_PROG 1 541#define OTPPOC_VERIFY 3 542#define OTPPOC_INIT 4 543#define OTPPOC_SET 5 544#define OTPPOC_RESET 6 545#define OTPPOC_OCST 7 546#define OTPPOC_ROW_LOCK 8 547#define OTPPOC_PRESCN_TEST 9 548 549/* Fields in otplayoutextension */ 550#define OTPLAYOUTEXT_FUSE_MASK 0x3FF 551 552 553/* Jtagm characteristics that appeared at a given corerev */ 554#define JTAGM_CREV_OLD 10 /* Old command set, 16bit max IR */ 555#define JTAGM_CREV_IRP 22 /* Able to do pause-ir */ 556#define JTAGM_CREV_RTI 28 /* Able to do return-to-idle */ 557 558/* jtagcmd */ 559#define JCMD_START 0x80000000 560#define JCMD_BUSY 0x80000000 561#define JCMD_STATE_MASK 0x60000000 562#define JCMD_STATE_TLR 0x00000000 /* Test-logic-reset */ 563#define JCMD_STATE_PIR 0x20000000 /* Pause IR */ 564#define JCMD_STATE_PDR 0x40000000 /* Pause DR */ 565#define JCMD_STATE_RTI 0x60000000 /* Run-test-idle */ 566#define JCMD0_ACC_MASK 0x0000f000 567#define JCMD0_ACC_IRDR 0x00000000 568#define JCMD0_ACC_DR 0x00001000 569#define JCMD0_ACC_IR 0x00002000 570#define JCMD0_ACC_RESET 0x00003000 571#define JCMD0_ACC_IRPDR 0x00004000 572#define JCMD0_ACC_PDR 0x00005000 573#define JCMD0_IRW_MASK 0x00000f00 574#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */ 575#define JCMD_ACC_IRDR 0x00000000 576#define JCMD_ACC_DR 0x00010000 577#define JCMD_ACC_IR 0x00020000 578#define JCMD_ACC_RESET 0x00030000 579#define JCMD_ACC_IRPDR 0x00040000 580#define JCMD_ACC_PDR 0x00050000 581#define JCMD_ACC_PIR 0x00060000 582#define JCMD_ACC_IRDR_I 0x00070000 /* rev 28: return to run-test-idle */ 583#define JCMD_ACC_DR_I 0x00080000 /* rev 28: return to run-test-idle */ 584#define JCMD_IRW_MASK 0x00001f00 585#define JCMD_IRW_SHIFT 8 586#define JCMD_DRW_MASK 0x0000003f 587 588/* jtagctrl */ 589#define JCTRL_FORCE_CLK 4 /* Force clock */ 590#define JCTRL_EXT_EN 2 /* Enable external targets */ 591#define JCTRL_EN 1 /* Enable Jtag master */ 592 593/* Fields in clkdiv */ 594#define CLKD_SFLASH 0x0f000000 595#define CLKD_SFLASH_SHIFT 24 596#define CLKD_OTP 0x000f0000 597#define CLKD_OTP_SHIFT 16 598#define CLKD_JTAG 0x00000f00 599#define CLKD_JTAG_SHIFT 8 600#define CLKD_UART 0x000000ff 601 602#define CLKD2_SROM 0x00000003 603 604/* intstatus/intmask */ 605#define CI_GPIO 0x00000001 /* gpio intr */ 606#define CI_EI 0x00000002 /* extif intr (corerev >= 3) */ 607#define CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */ 608#define CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */ 609#define CI_ECI 0x00000010 /* eci intr (corerev >= 21) */ 610#define CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */ 611#define CI_UART 0x00000040 /* uart intr (corerev >= 21) */ 612#define CI_WDRESET 0x80000000 /* watchdog reset occurred */ 613 614/* slow_clk_ctl */ 615#define SCC_SS_MASK 0x00000007 /* slow clock source mask */ 616#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */ 617#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */ 618#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */ 619#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ 620#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 621 * 0: LPO is enabled 622 */ 623#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 624 * 0: power logic control 625 */ 626#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors 627 * PLL clock disable requests from core 628 */ 629#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't 630 * disable crystal when appropriate 631 */ 632#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ 633#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ 634#define SCC_CD_SHIFT 16 635 636/* system_clk_ctl */ 637#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */ 638#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */ 639#define SYCC_FP 0x00000004 /* ForcePLLOn */ 640#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */ 641#define SYCC_HR 0x00000010 /* Force HT */ 642#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */ 643#define SYCC_CD_SHIFT 16 644 645/* Indirect backplane access */ 646#define BPIA_BYTEEN 0x0000000f 647#define BPIA_SZ1 0x00000001 648#define BPIA_SZ2 0x00000003 649#define BPIA_SZ4 0x00000007 650#define BPIA_SZ8 0x0000000f 651#define BPIA_WRITE 0x00000100 652#define BPIA_START 0x00000200 653#define BPIA_BUSY 0x00000200 654#define BPIA_ERROR 0x00000400 655 656/* pcmcia/prog/flash_config */ 657#define CF_EN 0x00000001 /* enable */ 658#define CF_EM_MASK 0x0000000e /* mode */ 659#define CF_EM_SHIFT 1 660#define CF_EM_FLASH 0 /* flash/asynchronous mode */ 661#define CF_EM_SYNC 2 /* synchronous mode */ 662#define CF_EM_PCMCIA 4 /* pcmcia mode */ 663#define CF_DS 0x00000010 /* destsize: 0=8bit, 1=16bit */ 664#define CF_BS 0x00000020 /* byteswap */ 665#define CF_CD_MASK 0x000000c0 /* clock divider */ 666#define CF_CD_SHIFT 6 667#define CF_CD_DIV2 0x00000000 /* backplane/2 */ 668#define CF_CD_DIV3 0x00000040 /* backplane/3 */ 669#define CF_CD_DIV4 0x00000080 /* backplane/4 */ 670#define CF_CE 0x00000100 /* clock enable */ 671#define CF_SB 0x00000200 /* size/bytestrobe (synch only) */ 672 673/* pcmcia_memwait */ 674#define PM_W0_MASK 0x0000003f /* waitcount0 */ 675#define PM_W1_MASK 0x00001f00 /* waitcount1 */ 676#define PM_W1_SHIFT 8 677#define PM_W2_MASK 0x001f0000 /* waitcount2 */ 678#define PM_W2_SHIFT 16 679#define PM_W3_MASK 0x1f000000 /* waitcount3 */ 680#define PM_W3_SHIFT 24 681 682/* pcmcia_attrwait */ 683#define PA_W0_MASK 0x0000003f /* waitcount0 */ 684#define PA_W1_MASK 0x00001f00 /* waitcount1 */ 685#define PA_W1_SHIFT 8 686#define PA_W2_MASK 0x001f0000 /* waitcount2 */ 687#define PA_W2_SHIFT 16 688#define PA_W3_MASK 0x1f000000 /* waitcount3 */ 689#define PA_W3_SHIFT 24 690 691/* pcmcia_iowait */ 692#define PI_W0_MASK 0x0000003f /* waitcount0 */ 693#define PI_W1_MASK 0x00001f00 /* waitcount1 */ 694#define PI_W1_SHIFT 8 695#define PI_W2_MASK 0x001f0000 /* waitcount2 */ 696#define PI_W2_SHIFT 16 697#define PI_W3_MASK 0x1f000000 /* waitcount3 */ 698#define PI_W3_SHIFT 24 699 700/* prog_waitcount */ 701#define PW_W0_MASK 0x0000001f /* waitcount0 */ 702#define PW_W1_MASK 0x00001f00 /* waitcount1 */ 703#define PW_W1_SHIFT 8 704#define PW_W2_MASK 0x001f0000 /* waitcount2 */ 705#define PW_W2_SHIFT 16 706#define PW_W3_MASK 0x1f000000 /* waitcount3 */ 707#define PW_W3_SHIFT 24 708 709#define PW_W0 0x0000000c 710#define PW_W1 0x00000a00 711#define PW_W2 0x00020000 712#define PW_W3 0x01000000 713 714/* flash_waitcount */ 715#define FW_W0_MASK 0x0000003f /* waitcount0 */ 716#define FW_W1_MASK 0x00001f00 /* waitcount1 */ 717#define FW_W1_SHIFT 8 718#define FW_W2_MASK 0x001f0000 /* waitcount2 */ 719#define FW_W2_SHIFT 16 720#define FW_W3_MASK 0x1f000000 /* waitcount3 */ 721#define FW_W3_SHIFT 24 722 723/* When Srom support present, fields in sromcontrol */ 724#define SRC_START 0x80000000 725#define SRC_BUSY 0x80000000 726#define SRC_OPCODE 0x60000000 727#define SRC_OP_READ 0x00000000 728#define SRC_OP_WRITE 0x20000000 729#define SRC_OP_WRDIS 0x40000000 730#define SRC_OP_WREN 0x60000000 731#define SRC_OTPSEL 0x00000010 732#define SRC_LOCK 0x00000008 733#define SRC_SIZE_MASK 0x00000006 734#define SRC_SIZE_1K 0x00000000 735#define SRC_SIZE_4K 0x00000002 736#define SRC_SIZE_16K 0x00000004 737#define SRC_SIZE_SHIFT 1 738#define SRC_PRESENT 0x00000001 739 740/* Fields in pmucontrol */ 741#define PCTL_ILP_DIV_MASK 0xffff0000 742#define PCTL_ILP_DIV_SHIFT 16 743#define PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */ 744#define PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */ 745#define PCTL_HT_REQ_EN 0x00000100 746#define PCTL_ALP_REQ_EN 0x00000080 747#define PCTL_XTALFREQ_MASK 0x0000007c 748#define PCTL_XTALFREQ_SHIFT 2 749#define PCTL_ILP_DIV_EN 0x00000002 750#define PCTL_LPO_SEL 0x00000001 751 752/* Fields in clkstretch */ 753#define CSTRETCH_HT 0xffff0000 754#define CSTRETCH_ALP 0x0000ffff 755 756/* gpiotimerval */ 757#define GPIO_ONTIME_SHIFT 16 758 759/* clockcontrol_n */ 760#define CN_N1_MASK 0x3f /* n1 control */ 761#define CN_N2_MASK 0x3f00 /* n2 control */ 762#define CN_N2_SHIFT 8 763#define CN_PLLC_MASK 0xf0000 /* pll control */ 764#define CN_PLLC_SHIFT 16 765 766/* clockcontrol_sb/pci/uart */ 767#define CC_M1_MASK 0x3f /* m1 control */ 768#define CC_M2_MASK 0x3f00 /* m2 control */ 769#define CC_M2_SHIFT 8 770#define CC_M3_MASK 0x3f0000 /* m3 control */ 771#define CC_M3_SHIFT 16 772#define CC_MC_MASK 0x1f000000 /* mux control */ 773#define CC_MC_SHIFT 24 774 775/* N3M Clock control magic field values */ 776#define CC_F6_2 0x02 /* A factor of 2 in */ 777#define CC_F6_3 0x03 /* 6-bit fields like */ 778#define CC_F6_4 0x05 /* N1, M1 or M3 */ 779#define CC_F6_5 0x09 780#define CC_F6_6 0x11 781#define CC_F6_7 0x21 782 783#define CC_F5_BIAS 5 /* 5-bit fields get this added */ 784 785#define CC_MC_BYPASS 0x08 786#define CC_MC_M1 0x04 787#define CC_MC_M1M2 0x02 788#define CC_MC_M1M2M3 0x01 789#define CC_MC_M1M3 0x11 790 791/* Type 2 Clock control magic field values */ 792#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */ 793#define CC_T2M2_BIAS 3 /* m2 bias */ 794 795#define CC_T2MC_M1BYP 1 796#define CC_T2MC_M2BYP 2 797#define CC_T2MC_M3BYP 4 798 799/* Type 6 Clock control magic field values */ 800#define CC_T6_MMASK 1 /* bits of interest in m */ 801#define CC_T6_M0 120000000 /* sb clock for m = 0 */ 802#define CC_T6_M1 100000000 /* sb clock for m = 1 */ 803#define SB2MIPS_T6(sb) (2 * (sb)) 804 805/* Common clock base */ 806#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */ 807#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLLs */ 808 809/* Clock control values for 200MHz in 5350 */ 810#define CLKC_5350_N 0x0311 811#define CLKC_5350_M 0x04020009 812 813/* Flash types in the chipcommon capabilities register */ 814#define FLASH_NONE 0x000 /* No flash */ 815#define SFLASH_ST 0x100 /* ST serial flash */ 816#define SFLASH_AT 0x200 /* Atmel serial flash */ 817#define NFLASH 0x300 818#define PFLASH 0x700 /* Parallel flash */ 819 820/* Bits in the ExtBus config registers */ 821#define CC_CFG_EN 0x0001 /* Enable */ 822#define CC_CFG_EM_MASK 0x000e /* Extif Mode */ 823#define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */ 824#define CC_CFG_EM_SYNC 0x0002 /* Synchronous */ 825#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */ 826#define CC_CFG_EM_IDE 0x0006 /* IDE */ 827#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ 828#define CC_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */ 829#define CC_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */ 830#define CC_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */ 831#define CC_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */ 832 833/* ExtBus address space */ 834#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */ 835#define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */ 836#define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */ 837#define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */ 838#define CC_EB_IDE 0x1a800000 /* IDE memory base */ 839#define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */ 840#define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */ 841#define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */ 842#define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */ 843 844 845/* Start/busy bit in flashcontrol */ 846#define SFLASH_OPCODE 0x000000ff 847#define SFLASH_ACTION 0x00000700 848#define SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ 849#define SFLASH_START 0x80000000 850#define SFLASH_BUSY SFLASH_START 851 852/* flashcontrol action codes */ 853#define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */ 854#define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */ 855#define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 addr bytes */ 856#define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addr & 1 data bytes */ 857#define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addr & 4 data bytes */ 858#define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addr, 4 don't care & 4 data bytes */ 859#define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addr, 1 don't care & 4 data bytes */ 860 861/* flashcontrol action+opcodes for ST flashes */ 862#define SFLASH_ST_WREN 0x0006 /* Write Enable */ 863#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */ 864#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */ 865#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */ 866#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */ 867#define SFLASH_ST_PP 0x0302 /* Page Program */ 868#define SFLASH_ST_SE 0x02d8 /* Sector Erase */ 869#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */ 870#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */ 871#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */ 872#define SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */ 873#define SFLASH_ST_SSE 0x0220 /* Sub-sector Erase */ 874 875/* Status register bits for ST flashes */ 876#define SFLASH_ST_WIP 0x01 /* Write In Progress */ 877#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */ 878#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */ 879#define SFLASH_ST_BP_SHIFT 2 880#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */ 881 882/* flashcontrol action+opcodes for Atmel flashes */ 883#define SFLASH_AT_READ 0x07e8 884#define SFLASH_AT_PAGE_READ 0x07d2 885#define SFLASH_AT_BUF1_READ 886#define SFLASH_AT_BUF2_READ 887#define SFLASH_AT_STATUS 0x01d7 888#define SFLASH_AT_BUF1_WRITE 0x0384 889#define SFLASH_AT_BUF2_WRITE 0x0387 890#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 891#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 892#define SFLASH_AT_BUF1_PROGRAM 0x0288 893#define SFLASH_AT_BUF2_PROGRAM 0x0289 894#define SFLASH_AT_PAGE_ERASE 0x0281 895#define SFLASH_AT_BLOCK_ERASE 0x0250 896#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 897#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 898#define SFLASH_AT_BUF1_LOAD 0x0253 899#define SFLASH_AT_BUF2_LOAD 0x0255 900#define SFLASH_AT_BUF1_COMPARE 0x0260 901#define SFLASH_AT_BUF2_COMPARE 0x0261 902#define SFLASH_AT_BUF1_REPROGRAM 0x0258 903#define SFLASH_AT_BUF2_REPROGRAM 0x0259 904 905/* Status register bits for Atmel flashes */ 906#define SFLASH_AT_READY 0x80 907#define SFLASH_AT_MISMATCH 0x40 908#define SFLASH_AT_ID_MASK 0x38 909#define SFLASH_AT_ID_SHIFT 3 910 911/* 912 * These are the UART port assignments, expressed as offsets from the base 913 * register. These assignments should hold for any serial port based on 914 * a 8250, 16450, or 16550(A). 915 */ 916 917#define UART_RX 0 /* In: Receive buffer (DLAB=0) */ 918#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ 919#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ 920#define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */ 921#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ 922#define UART_IIR 2 /* In: Interrupt Identity Register */ 923#define UART_FCR 2 /* Out: FIFO Control Register */ 924#define UART_LCR 3 /* Out: Line Control Register */ 925#define UART_MCR 4 /* Out: Modem Control Register */ 926#define UART_LSR 5 /* In: Line Status Register */ 927#define UART_MSR 6 /* In: Modem Status Register */ 928#define UART_SCR 7 /* I/O: Scratch Register */ 929#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 930#define UART_LCR_WLEN8 0x03 /* Word length: 8 bits */ 931#define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */ 932#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 933#define UART_LSR_RX_FIFO 0x80 /* Receive FIFO error */ 934#define UART_LSR_TDHR 0x40 /* Data-hold-register empty */ 935#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 936#define UART_LSR_BREAK 0x10 /* Break interrupt */ 937#define UART_LSR_FRAMING 0x08 /* Framing error */ 938#define UART_LSR_PARITY 0x04 /* Parity error */ 939#define UART_LSR_OVERRUN 0x02 /* Overrun error */ 940#define UART_LSR_RXRDY 0x01 /* Receiver ready */ 941#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */ 942 943/* Interrupt Identity Register (IIR) bits */ 944#define UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */ 945#define UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */ 946#define UART_IIR_MDM_CHG 0x0 /* Modem status changed */ 947#define UART_IIR_NOINT 0x1 /* No interrupt pending */ 948#define UART_IIR_THRE 0x2 /* THR empty */ 949#define UART_IIR_RCVD_DATA 0x4 /* Received data available */ 950#define UART_IIR_RCVR_STATUS 0x6 /* Receiver status */ 951#define UART_IIR_CHAR_TIME 0xc /* Character time */ 952 953/* Interrupt Enable Register (IER) bits */ 954#define UART_IER_EDSSI 8 /* enable modem status interrupt */ 955#define UART_IER_ELSI 4 /* enable receiver line status interrupt */ 956#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */ 957#define UART_IER_ERBFI 1 /* enable data available interrupt */ 958 959/* pmustatus */ 960#define PST_EXTLPOAVAIL 0x0100 961#define PST_WDRESET 0x0080 962#define PST_INTPEND 0x0040 963#define PST_SBCLKST 0x0030 964#define PST_SBCLKST_ILP 0x0010 965#define PST_SBCLKST_ALP 0x0020 966#define PST_SBCLKST_HT 0x0030 967#define PST_ALPAVAIL 0x0008 968#define PST_HTAVAIL 0x0004 969#define PST_RESINIT 0x0003 970 971/* pmucapabilities */ 972#define PCAP_REV_MASK 0x000000ff 973#define PCAP_RC_MASK 0x00001f00 974#define PCAP_RC_SHIFT 8 975#define PCAP_TC_MASK 0x0001e000 976#define PCAP_TC_SHIFT 13 977#define PCAP_PC_MASK 0x001e0000 978#define PCAP_PC_SHIFT 17 979#define PCAP_VC_MASK 0x01e00000 980#define PCAP_VC_SHIFT 21 981#define PCAP_CC_MASK 0x1e000000 982#define PCAP_CC_SHIFT 25 983#define PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */ 984#define PCAP5_PC_SHIFT 17 985#define PCAP5_VC_MASK 0x07c00000 986#define PCAP5_VC_SHIFT 22 987#define PCAP5_CC_MASK 0xf8000000 988#define PCAP5_CC_SHIFT 27 989 990/* PMU Resource Request Timer registers */ 991/* This is based on PmuRev0 */ 992#define PRRT_TIME_MASK 0x03ff 993#define PRRT_INTEN 0x0400 994#define PRRT_REQ_ACTIVE 0x0800 995#define PRRT_ALP_REQ 0x1000 996#define PRRT_HT_REQ 0x2000 997 998/* PMU resource bit position */ 999#define PMURES_BIT(bit) (1 << (bit)) 1000 1001/* PMU resource number limit */ 1002#define PMURES_MAX_RESNUM 30 1003 1004/* PMU chip control0 register */ 1005#define PMU_CHIPCTL0 0 1006 1007/* PMU chip control1 register */ 1008#define PMU_CHIPCTL1 1 1009#define PMU_CC1_RXC_DLL_BYPASS 0x00010000 1010 1011#define PMU_CC1_IF_TYPE_MASK 0x00000030 1012#define PMU_CC1_IF_TYPE_RMII 0x00000000 1013#define PMU_CC1_IF_TYPE_MII 0x00000010 1014#define PMU_CC1_IF_TYPE_RGMII 0x00000020 1015 1016#define PMU_CC1_SW_TYPE_MASK 0x000000c0 1017#define PMU_CC1_SW_TYPE_EPHY 0x00000000 1018#define PMU_CC1_SW_TYPE_EPHYMII 0x00000040 1019#define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 1020#define PMU_CC1_SW_TYPE_RGMII 0x000000c0 1021 1022 1023/* PMU corerev and chip specific PLL controls. 1024 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number 1025 * to differentiate different PLLs controlled by the same PMU rev. 1026 */ 1027/* pllcontrol registers */ 1028/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ 1029#define PMU0_PLL0_PLLCTL0 0 1030#define PMU0_PLL0_PC0_PDIV_MASK 1 1031#define PMU0_PLL0_PC0_PDIV_FREQ 25000 1032#define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 1033#define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 1034#define PMU0_PLL0_PC0_DIV_ARM_BASE 8 1035 1036/* PC0_DIV_ARM for PLLOUT_ARM */ 1037#define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 1038#define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 1039#define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 1040#define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ 1041#define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 1042#define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 1043#define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 1044#define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 1045 1046/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ 1047#define PMU0_PLL0_PLLCTL1 1 1048#define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 1049#define PMU0_PLL0_PC1_WILD_INT_SHIFT 28 1050#define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 1051#define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 1052#define PMU0_PLL0_PC1_STOP_MOD 0x00000040 1053 1054/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ 1055#define PMU0_PLL0_PLLCTL2 2 1056#define PMU0_PLL0_PC2_WILD_INT_MASK 0xf 1057#define PMU0_PLL0_PC2_WILD_INT_SHIFT 4 1058 1059/* pllcontrol registers */ 1060/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 1061#define PMU1_PLL0_PLLCTL0 0 1062#define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 1063#define PMU1_PLL0_PC0_P1DIV_SHIFT 20 1064#define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 1065#define PMU1_PLL0_PC0_P2DIV_SHIFT 24 1066 1067/* m<x>div */ 1068#define PMU1_PLL0_PLLCTL1 1 1069#define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff 1070#define PMU1_PLL0_PC1_M1DIV_SHIFT 0 1071#define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 1072#define PMU1_PLL0_PC1_M2DIV_SHIFT 8 1073#define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 1074#define PMU1_PLL0_PC1_M3DIV_SHIFT 16 1075#define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 1076#define PMU1_PLL0_PC1_M4DIV_SHIFT 24 1077 1078#define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 1079#define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 1080#define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 1081 1082/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 1083#define PMU1_PLL0_PLLCTL2 2 1084#define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff 1085#define PMU1_PLL0_PC2_M5DIV_SHIFT 0 1086#define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 1087#define PMU1_PLL0_PC2_M6DIV_SHIFT 8 1088#define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 1089#define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 1090#define PMU1_PLL0_PC2_NDIV_MODE_MASH 1 1091#define PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */ 1092#define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 1093#define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 1094#define PMU1_PLL0_PC2_NDIV_MODE_INT 0 1095 1096/* ndiv_frac */ 1097#define PMU1_PLL0_PLLCTL3 3 1098#define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff 1099#define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 1100 1101/* pll_ctrl */ 1102#define PMU1_PLL0_PLLCTL4 4 1103#define PMU1_PLL0_PC4_KVCO_XS_MASK 0x38000000 1104#define PMU1_PLL0_PC4_KVCO_XS_SHIFT 27 1105 1106/* pll_ctrl, vco_rng, clkdrive_ch<x> */ 1107#define PMU1_PLL0_PLLCTL5 5 1108#define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 1109#define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 1110#define PMU1_PLL0_PC5_PLL_CTRL_37_32_MASK 0x0000003f 1111#define PMU1_PLL0_PC5_PLL_CTRL_37_32_SHIFT 0 1112#define PMU1_PLL0_PC5_VCO_RNG_MASK 0x000000C0 1113#define PMU1_PLL0_PC5_VCO_RNG_SHIFT 6 1114 1115/* PMU rev 2 control words */ 1116#define PMU2_PHY_PLL_PLLCTL 4 1117#define PMU2_SI_PLL_PLLCTL 10 1118 1119/* PMU rev 2 */ 1120/* pllcontrol registers */ 1121/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 1122#define PMU2_PLL_PLLCTL0 0 1123#define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 1124#define PMU2_PLL_PC0_P1DIV_SHIFT 20 1125#define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 1126#define PMU2_PLL_PC0_P2DIV_SHIFT 24 1127#define PMU1_PLL0_PC0_BYPASS_SDMOD_MASK 0x10000000 1128#define PMU1_PLL0_PC0_BYPASS_SDMOD_SHIFT 28 1129 1130/* m<x>div */ 1131#define PMU2_PLL_PLLCTL1 1 1132#define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff 1133#define PMU2_PLL_PC1_M1DIV_SHIFT 0 1134#define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 1135#define PMU2_PLL_PC1_M2DIV_SHIFT 8 1136#define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 1137#define PMU2_PLL_PC1_M3DIV_SHIFT 16 1138#define PMU2_PLL_PC1_M4DIV_MASK 0xff000000 1139#define PMU2_PLL_PC1_M4DIV_SHIFT 24 1140 1141/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 1142#define PMU2_PLL_PLLCTL2 2 1143#define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff 1144#define PMU2_PLL_PC2_M5DIV_SHIFT 0 1145#define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 1146#define PMU2_PLL_PC2_M6DIV_SHIFT 8 1147#define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 1148#define PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 1149#define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 1150#define PMU2_PLL_PC2_NDIV_INT_SHIFT 20 1151 1152/* ndiv_frac */ 1153#define PMU2_PLL_PLLCTL3 3 1154#define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff 1155#define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 1156 1157/* pll_ctrl */ 1158#define PMU2_PLL_PLLCTL4 4 1159 1160/* pll_ctrl, vco_rng, clkdrive_ch<x> */ 1161#define PMU2_PLL_PLLCTL5 5 1162#define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 1163#define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 1164#define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 1165#define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 1166#define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 1167#define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 1168#define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 1169#define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 1170#define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 1171#define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 1172#define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 1173#define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 1174 1175/* PMU rev 5 (& 6) */ 1176#define PMU5_PLL_P1P2_OFF 0 1177#define PMU5_PLL_P1_MASK 0x0f000000 1178#define PMU5_PLL_P1_SHIFT 24 1179#define PMU5_PLL_P2_MASK 0x00f00000 1180#define PMU5_PLL_P2_SHIFT 20 1181#define PMU5_PLL_M14_OFF 1 1182#define PMU5_PLL_MDIV_MASK 0x000000ff 1183#define PMU5_PLL_MDIV_WIDTH 8 1184#define PMU5_PLL_NM5_OFF 2 1185#define PMU5_PLL_NDIV_MASK 0xfff00000 1186#define PMU5_PLL_NDIV_SHIFT 20 1187#define PMU5_PLL_NDIV_MODE_MASK 0x000e0000 1188#define PMU5_PLL_NDIV_MODE_SHIFT 17 1189#define PMU5_PLL_FMAB_OFF 3 1190#define PMU5_PLL_MRAT_MASK 0xf0000000 1191#define PMU5_PLL_MRAT_SHIFT 28 1192#define PMU5_PLL_ABRAT_MASK 0x08000000 1193#define PMU5_PLL_ABRAT_SHIFT 27 1194#define PMU5_PLL_FDIV_MASK 0x07ffffff 1195#define PMU5_PLL_PLLCTL_OFF 4 1196#define PMU5_PLL_PCHI_OFF 5 1197#define PMU5_PLL_PCHI_MASK 0x0000003f 1198 1199/* pmu XtalFreqRatio */ 1200#define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF 1201#define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 1202#define PMU_XTALFREQ_REG_MEASURE_SHIFT 31 1203 1204/* Divider allocation in 4716/47162/5356/5357 */ 1205#define PMU5_MAINPLL_CPU 1 1206#define PMU5_MAINPLL_MEM 2 1207#define PMU5_MAINPLL_SI 3 1208 1209/* 4706 PMU */ 1210#define PMU4706_MAINPLL_PLL0 0 1211#define PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */ 1212#define PMU6_4706_PROC_P1DIV_MASK 0x000f0000 1213#define PMU6_4706_PROC_P1DIV_SHIFT 16 1214#define PMU6_4706_PROC_P2DIV_MASK 0x0000f000 1215#define PMU6_4706_PROC_P2DIV_SHIFT 12 1216#define PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8 1217#define PMU6_4706_PROC_NDIV_INT_SHIFT 3 1218#define PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007 1219#define PMU6_4706_PROC_NDIV_MODE_SHIFT 0 1220 1221#define PMU7_PLL_PLLCTL7 7 1222#define PMU7_PLL_PLLCTL8 8 1223#define PMU7_PLL_PLLCTL11 11 1224 1225/* PLL usage in 4716/47162 */ 1226#define PMU4716_MAINPLL_PLL0 12 1227 1228/* PLL usage in 5356/5357 */ 1229#define PMU5356_MAINPLL_PLL0 0 1230#define PMU5357_MAINPLL_PLL0 0 1231 1232/* 4716/47162 resources */ 1233#define RES4716_PROC_PLL_ON 0x00000040 1234#define RES4716_PROC_HT_AVAIL 0x00000080 1235 1236/* 4716/4717/4718 Chip specific ChipControl register bits */ 1237#define CCTRL471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared with pflash */ 1238 1239/* 4716/4717/4718 Chip specific ChipControl register bits */ 1240#define CCTRL_471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared w/ pflash */ 1241 1242/* 5357 Chip specific ChipControl register bits */ 1243/* 2nd - 32-bit reg */ 1244#define CCTRL_5357_I2S_PINS_ENABLE 0x00040000 /* I2S pins enable */ 1245#define CCTRL_5357_I2CSPI_PINS_ENABLE 0x00080000 /* I2C/SPI pins enable */ 1246 1247/* 5354 resources */ 1248#define RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */ 1249#define RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */ 1250#define RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */ 1251#define RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ 1252#define RES5354_ILP_REQUEST 4 /* 0x00010 */ 1253#define RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */ 1254#define RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */ 1255#define RES5354_ROM_SWITCH 7 /* 0x00080 */ 1256#define RES5354_PA_REF_LDO 8 /* 0x00100 */ 1257#define RES5354_RADIO_LDO 9 /* 0x00200 */ 1258#define RES5354_AFE_LDO 10 /* 0x00400 */ 1259#define RES5354_PLL_LDO 11 /* 0x00800 */ 1260#define RES5354_BG_FILTBYP 12 /* 0x01000 */ 1261#define RES5354_TX_FILTBYP 13 /* 0x02000 */ 1262#define RES5354_RX_FILTBYP 14 /* 0x04000 */ 1263#define RES5354_XTAL_PU 15 /* 0x08000 */ 1264#define RES5354_XTAL_EN 16 /* 0x10000 */ 1265#define RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */ 1266#define RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */ 1267#define RES5354_BB_PLL_PU 19 /* 0x80000 */ 1268 1269/* 5357 Chip specific ChipControl register bits */ 1270#define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */ 1271#define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */ 1272#define CCTRL5357_NFLASH (1<<16) /* Nandflash in ChipControl 1, bit 16 */ 1273 1274/* 4328 resources */ 1275#define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */ 1276#define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */ 1277#define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */ 1278#define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ 1279#define RES4328_ILP_REQUEST 4 /* 0x00010 */ 1280#define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */ 1281#define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */ 1282#define RES4328_ROM_SWITCH 7 /* 0x00080 */ 1283#define RES4328_PA_REF_LDO 8 /* 0x00100 */ 1284#define RES4328_RADIO_LDO 9 /* 0x00200 */ 1285#define RES4328_AFE_LDO 10 /* 0x00400 */ 1286#define RES4328_PLL_LDO 11 /* 0x00800 */ 1287#define RES4328_BG_FILTBYP 12 /* 0x01000 */ 1288#define RES4328_TX_FILTBYP 13 /* 0x02000 */ 1289#define RES4328_RX_FILTBYP 14 /* 0x04000 */ 1290#define RES4328_XTAL_PU 15 /* 0x08000 */ 1291#define RES4328_XTAL_EN 16 /* 0x10000 */ 1292#define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */ 1293#define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */ 1294#define RES4328_BB_PLL_PU 19 /* 0x80000 */ 1295 1296/* 4325 A0/A1 resources */ 1297#define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */ 1298#define RES4325_CBUCK_BURST 1 /* 0x00000002 */ 1299#define RES4325_CBUCK_PWM 2 /* 0x00000004 */ 1300#define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */ 1301#define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */ 1302#define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */ 1303#define RES4325_ILP_REQUEST 6 /* 0x00000040 */ 1304#define RES4325_ABUCK_BURST 7 /* 0x00000080 */ 1305#define RES4325_ABUCK_PWM 8 /* 0x00000100 */ 1306#define RES4325_LNLDO1_PU 9 /* 0x00000200 */ 1307#define RES4325_OTP_PU 10 /* 0x00000400 */ 1308#define RES4325_LNLDO3_PU 11 /* 0x00000800 */ 1309#define RES4325_LNLDO4_PU 12 /* 0x00001000 */ 1310#define RES4325_XTAL_PU 13 /* 0x00002000 */ 1311#define RES4325_ALP_AVAIL 14 /* 0x00004000 */ 1312#define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */ 1313#define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */ 1314#define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1315#define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1316#define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */ 1317#define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1318#define RES4325_HT_AVAIL 21 /* 0x00200000 */ 1319 1320/* 4325 B0/C0 resources */ 1321#define RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */ 1322#define RES4325B0_CBUCK_BURST 2 /* 0x00000004 */ 1323#define RES4325B0_CBUCK_PWM 3 /* 0x00000008 */ 1324#define RES4325B0_CLDO_PU 4 /* 0x00000010 */ 1325 1326/* 4325 C1 resources */ 1327#define RES4325C1_LNLDO2_PU 12 /* 0x00001000 */ 1328 1329/* 4325 chip-specific ChipStatus register bits */ 1330#define CST4325_SPROM_OTP_SEL_MASK 0x00000003 1331#define CST4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ 1332#define CST4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ 1333#define CST4325_OTP_SEL 2 /* OTP is powered up, no SPROM */ 1334#define CST4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */ 1335#define CST4325_SDIO_USB_MODE_MASK 0x00000004 1336#define CST4325_SDIO_USB_MODE_SHIFT 2 1337#define CST4325_RCAL_VALID_MASK 0x00000008 1338#define CST4325_RCAL_VALID_SHIFT 3 1339#define CST4325_RCAL_VALUE_MASK 0x000001f0 1340#define CST4325_RCAL_VALUE_SHIFT 4 1341#define CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */ 1342#define CST4325_PMUTOP_2B_SHIFT 9 1343 1344#define RES4329_RESERVED0 0 /* 0x00000001 */ 1345#define RES4329_CBUCK_LPOM 1 /* 0x00000002 */ 1346#define RES4329_CBUCK_BURST 2 /* 0x00000004 */ 1347#define RES4329_CBUCK_PWM 3 /* 0x00000008 */ 1348#define RES4329_CLDO_PU 4 /* 0x00000010 */ 1349#define RES4329_PALDO_PU 5 /* 0x00000020 */ 1350#define RES4329_ILP_REQUEST 6 /* 0x00000040 */ 1351#define RES4329_RESERVED7 7 /* 0x00000080 */ 1352#define RES4329_RESERVED8 8 /* 0x00000100 */ 1353#define RES4329_LNLDO1_PU 9 /* 0x00000200 */ 1354#define RES4329_OTP_PU 10 /* 0x00000400 */ 1355#define RES4329_RESERVED11 11 /* 0x00000800 */ 1356#define RES4329_LNLDO2_PU 12 /* 0x00001000 */ 1357#define RES4329_XTAL_PU 13 /* 0x00002000 */ 1358#define RES4329_ALP_AVAIL 14 /* 0x00004000 */ 1359#define RES4329_RX_PWRSW_PU 15 /* 0x00008000 */ 1360#define RES4329_TX_PWRSW_PU 16 /* 0x00010000 */ 1361#define RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1362#define RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1363#define RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */ 1364#define RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1365#define RES4329_HT_AVAIL 21 /* 0x00200000 */ 1366 1367#define CST4329_SPROM_OTP_SEL_MASK 0x00000003 1368#define CST4329_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ 1369#define CST4329_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ 1370#define CST4329_OTP_SEL 2 /* OTP is powered up, no SPROM */ 1371#define CST4329_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */ 1372#define CST4329_SPI_SDIO_MODE_MASK 0x00000004 1373#define CST4329_SPI_SDIO_MODE_SHIFT 2 1374 1375/* 4312 chip-specific ChipStatus register bits */ 1376#define CST4312_SPROM_OTP_SEL_MASK 0x00000003 1377#define CST4312_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ 1378#define CST4312_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ 1379#define CST4312_OTP_SEL 2 /* OTP is powered up, no SPROM */ 1380#define CST4312_OTP_BAD 3 /* OTP is broken, SPROM is present */ 1381 1382/* 4312 resources (all PMU chips with little memory constraint) */ 1383#define RES4312_SWITCHER_BURST 0 /* 0x00000001 */ 1384#define RES4312_SWITCHER_PWM 1 /* 0x00000002 */ 1385#define RES4312_PA_REF_LDO 2 /* 0x00000004 */ 1386#define RES4312_CORE_LDO_BURST 3 /* 0x00000008 */ 1387#define RES4312_CORE_LDO_PWM 4 /* 0x00000010 */ 1388#define RES4312_RADIO_LDO 5 /* 0x00000020 */ 1389#define RES4312_ILP_REQUEST 6 /* 0x00000040 */ 1390#define RES4312_BG_FILTBYP 7 /* 0x00000080 */ 1391#define RES4312_TX_FILTBYP 8 /* 0x00000100 */ 1392#define RES4312_RX_FILTBYP 9 /* 0x00000200 */ 1393#define RES4312_XTAL_PU 10 /* 0x00000400 */ 1394#define RES4312_ALP_AVAIL 11 /* 0x00000800 */ 1395#define RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */ 1396#define RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */ 1397#define RES4312_HT_AVAIL 14 /* 0x00004000 */ 1398 1399/* 4322 resources */ 1400#define RES4322_RF_LDO 0 1401#define RES4322_ILP_REQUEST 1 1402#define RES4322_XTAL_PU 2 1403#define RES4322_ALP_AVAIL 3 1404#define RES4322_SI_PLL_ON 4 1405#define RES4322_HT_SI_AVAIL 5 1406#define RES4322_PHY_PLL_ON 6 1407#define RES4322_HT_PHY_AVAIL 7 1408#define RES4322_OTP_PU 8 1409 1410/* 4322 chip-specific ChipStatus register bits */ 1411#define CST4322_XTAL_FREQ_20_40MHZ 0x00000020 1412#define CST4322_SPROM_OTP_SEL_MASK 0x000000c0 1413#define CST4322_SPROM_OTP_SEL_SHIFT 6 1414#define CST4322_NO_SPROM_OTP 0 /* no OTP, no SPROM */ 1415#define CST4322_SPROM_PRESENT 1 /* SPROM is present */ 1416#define CST4322_OTP_PRESENT 2 /* OTP is present */ 1417#define CST4322_PCI_OR_USB 0x00000100 1418#define CST4322_BOOT_MASK 0x00000600 1419#define CST4322_BOOT_SHIFT 9 1420#define CST4322_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ 1421#define CST4322_BOOT_FROM_ROM 1 /* boot from ROM */ 1422#define CST4322_BOOT_FROM_FLASH 2 /* boot from FLASH */ 1423#define CST4322_BOOT_FROM_INVALID 3 1424#define CST4322_ILP_DIV_EN 0x00000800 1425#define CST4322_FLASH_TYPE_MASK 0x00001000 1426#define CST4322_FLASH_TYPE_SHIFT 12 1427#define CST4322_FLASH_TYPE_SHIFT_ST 0 /* ST serial FLASH */ 1428#define CST4322_FLASH_TYPE_SHIFT_ATMEL 1 /* ATMEL flash */ 1429#define CST4322_ARM_TAP_SEL 0x00002000 1430#define CST4322_RES_INIT_MODE_MASK 0x0000c000 1431#define CST4322_RES_INIT_MODE_SHIFT 14 1432#define CST4322_RES_INIT_MODE_ILPAVAIL 0 /* resinitmode: ILP available */ 1433#define CST4322_RES_INIT_MODE_ILPREQ 1 /* resinitmode: ILP request */ 1434#define CST4322_RES_INIT_MODE_ALPAVAIL 2 /* resinitmode: ALP available */ 1435#define CST4322_RES_INIT_MODE_HTAVAIL 3 /* resinitmode: HT available */ 1436#define CST4322_PCIPLLCLK_GATING 0x00010000 1437#define CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000 1438#define CST4322_PCI_CARDBUS_MODE 0x00040000 1439 1440/* 43224 chip-specific ChipControl register bits */ 1441#define CCTRL43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */ 1442#define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ 1443#define CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ 1444 1445/* 43236 resources */ 1446#define RES43236_REGULATOR 0 1447#define RES43236_ILP_REQUEST 1 1448#define RES43236_XTAL_PU 2 1449#define RES43236_ALP_AVAIL 3 1450#define RES43236_SI_PLL_ON 4 1451#define RES43236_HT_SI_AVAIL 5 1452 1453/* 43236 chip-specific ChipControl register bits */ 1454#define CCTRL43236_BT_COEXIST (1<<0) /* 0 disable */ 1455#define CCTRL43236_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ 1456#define CCTRL43236_EXT_LNA (1<<2) /* 0 disable */ 1457#define CCTRL43236_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */ 1458#define CCTRL43236_GSIO (1<<4) /* 0 disable */ 1459 1460/* 43236 Chip specific ChipStatus register bits */ 1461#define CST43236_SFLASH_MASK 0x00000040 1462#define CST43236_OTP_SEL_MASK 0x00000080 1463#define CST43236_OTP_SEL_SHIFT 7 1464#define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */ 1465#define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */ 1466#define CST43236_BOOT_MASK 0x00001800 1467#define CST43236_BOOT_SHIFT 11 1468#define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ 1469#define CST43236_BOOT_FROM_ROM 1 /* boot from ROM */ 1470#define CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */ 1471#define CST43236_BOOT_FROM_INVALID 3 1472 1473/* 43237 resources */ 1474#define RES43237_REGULATOR 0 1475#define RES43237_ILP_REQUEST 1 1476#define RES43237_XTAL_PU 2 1477#define RES43237_ALP_AVAIL 3 1478#define RES43237_SI_PLL_ON 4 1479#define RES43237_HT_SI_AVAIL 5 1480 1481/* 43237 chip-specific ChipControl register bits */ 1482#define CCTRL43237_BT_COEXIST (1<<0) /* 0 disable */ 1483#define CCTRL43237_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ 1484#define CCTRL43237_EXT_LNA (1<<2) /* 0 disable */ 1485#define CCTRL43237_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */ 1486#define CCTRL43237_GSIO (1<<4) /* 0 disable */ 1487 1488/* 43237 Chip specific ChipStatus register bits */ 1489#define CST43237_SFLASH_MASK 0x00000040 1490#define CST43237_OTP_SEL_MASK 0x00000080 1491#define CST43237_OTP_SEL_SHIFT 7 1492#define CST43237_HSIC_MASK 0x00000100 /* USB/HSIC */ 1493#define CST43237_BP_CLK 0x00000200 /* 120/96Mbps */ 1494#define CST43237_BOOT_MASK 0x00001800 1495#define CST43237_BOOT_SHIFT 11 1496#define CST43237_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ 1497#define CST43237_BOOT_FROM_ROM 1 /* boot from ROM */ 1498#define CST43237_BOOT_FROM_FLASH 2 /* boot from FLASH */ 1499#define CST43237_BOOT_FROM_INVALID 3 1500 1501/* 4331 resources */ 1502#define RES4331_REGULATOR 0 1503#define RES4331_ILP_REQUEST 1 1504#define RES4331_XTAL_PU 2 1505#define RES4331_ALP_AVAIL 3 1506#define RES4331_SI_PLL_ON 4 1507#define RES4331_HT_SI_AVAIL 5 1508 1509/* 4331 chip-specific ChipControl register bits */ 1510#define CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */ 1511#define CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ 1512#define CCTRL4331_EXT_LNA_G (1<<2) /* 0 disable */ 1513#define CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */ 1514#define CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */ 1515#define CCTRL4331_GPIOCLK_ON_SPROMCS <1<<5) /* set drive out GPIO_CLK on sprom_cs pin */ 1516#define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */ 1517#define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */ 1518#define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */ 1519#define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */ 1520#define CCTRL4331_PCIE_AUXCLKEN <1<<10) /* pcie_auxclkenable */ 1521#define CCTRL4331_PCIE_PIPE_PLLDOWN <1<<11) /* pcie_pipe_pllpowerdown */ 1522#define CCTRL4331_EXTPA_EN2 (1<<12) /* 0 ext pa disable, 1 ext pa enabled */ 1523#define CCTRL4331_EXT_LNA_A (1<<13) /* 0 disable */ 1524#define CCTRL4331_BT_SHD0_ON_GPIO4 <1<<16) /* enable bt_shd0 at gpio4 */ 1525#define CCTRL4331_BT_SHD1_ON_GPIO5 <1<<17) /* enable bt_shd1 at gpio5 */ 1526#define CCTRL4331_EXTPA_ANA_EN (1<<24) /* 0 ext pa disable, 1 ext pa enabled */ 1527 1528/* 4331 Chip specific ChipStatus register bits */ 1529#define CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */ 1530#define CST4331_SPROM_OTP_SEL_MASK 0x00000006 1531#define CST4331_SPROM_OTP_SEL_SHIFT 1 1532#define CST4331_SPROM_PRESENT 0x00000002 1533#define CST4331_OTP_PRESENT 0x00000004 1534#define CST4331_LDO_RF 0x00000008 1535#define CST4331_LDO_PAR 0x00000010 1536 1537/* 4315 resource */ 1538#define RES4315_CBUCK_LPOM 1 /* 0x00000002 */ 1539#define RES4315_CBUCK_BURST 2 /* 0x00000004 */ 1540#define RES4315_CBUCK_PWM 3 /* 0x00000008 */ 1541#define RES4315_CLDO_PU 4 /* 0x00000010 */ 1542#define RES4315_PALDO_PU 5 /* 0x00000020 */ 1543#define RES4315_ILP_REQUEST 6 /* 0x00000040 */ 1544#define RES4315_LNLDO1_PU 9 /* 0x00000200 */ 1545#define RES4315_OTP_PU 10 /* 0x00000400 */ 1546#define RES4315_LNLDO2_PU 12 /* 0x00001000 */ 1547#define RES4315_XTAL_PU 13 /* 0x00002000 */ 1548#define RES4315_ALP_AVAIL 14 /* 0x00004000 */ 1549#define RES4315_RX_PWRSW_PU 15 /* 0x00008000 */ 1550#define RES4315_TX_PWRSW_PU 16 /* 0x00010000 */ 1551#define RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1552#define RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1553#define RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */ 1554#define RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1555#define RES4315_HT_AVAIL 21 /* 0x00200000 */ 1556 1557/* 4315 chip-specific ChipStatus register bits */ 1558#define CST4315_SPROM_OTP_SEL_MASK 0x00000003 /* gpio [7:6], SDIO CIS selection */ 1559#define CST4315_DEFCIS_SEL 0x00000000 /* use default CIS, OTP is powered up */ 1560#define CST4315_SPROM_SEL 0x00000001 /* use SPROM, OTP is powered up */ 1561#define CST4315_OTP_SEL 0x00000002 /* use OTP, OTP is powered up */ 1562#define CST4315_OTP_PWRDN 0x00000003 /* use SPROM, OTP is powered down */ 1563#define CST4315_SDIO_MODE 0x00000004 /* gpio [8], sdio/usb mode */ 1564#define CST4315_RCAL_VALID 0x00000008 1565#define CST4315_RCAL_VALUE_MASK 0x000001f0 1566#define CST4315_RCAL_VALUE_SHIFT 4 1567#define CST4315_PALDO_EXTPNP 0x00000200 /* PALDO is configured with external PNP */ 1568#define CST4315_CBUCK_MODE_MASK 0x00000c00 1569#define CST4315_CBUCK_MODE_BURST 0x00000400 1570#define CST4315_CBUCK_MODE_LPBURST 0x00000c00 1571 1572/* 4319 resources */ 1573#define RES4319_CBUCK_LPOM 1 /* 0x00000002 */ 1574#define RES4319_CBUCK_BURST 2 /* 0x00000004 */ 1575#define RES4319_CBUCK_PWM 3 /* 0x00000008 */ 1576#define RES4319_CLDO_PU 4 /* 0x00000010 */ 1577#define RES4319_PALDO_PU 5 /* 0x00000020 */ 1578#define RES4319_ILP_REQUEST 6 /* 0x00000040 */ 1579#define RES4319_LNLDO1_PU 9 /* 0x00000200 */ 1580#define RES4319_OTP_PU 10 /* 0x00000400 */ 1581#define RES4319_LNLDO2_PU 12 /* 0x00001000 */ 1582#define RES4319_XTAL_PU 13 /* 0x00002000 */ 1583#define RES4319_ALP_AVAIL 14 /* 0x00004000 */ 1584#define RES4319_RX_PWRSW_PU 15 /* 0x00008000 */ 1585#define RES4319_TX_PWRSW_PU 16 /* 0x00010000 */ 1586#define RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1587#define RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1588#define RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */ 1589#define RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1590#define RES4319_HT_AVAIL 21 /* 0x00200000 */ 1591 1592/* 4319 chip-specific ChipStatus register bits */ 1593#define CST4319_SPI_CPULESSUSB 0x00000001 1594#define CST4319_SPI_CLK_POL 0x00000002 1595#define CST4319_SPI_CLK_PH 0x00000008 1596#define CST4319_SPROM_OTP_SEL_MASK 0x000000c0 /* gpio [7:6], SDIO CIS selection */ 1597#define CST4319_SPROM_OTP_SEL_SHIFT 6 1598#define CST4319_DEFCIS_SEL 0x00000000 /* use default CIS, OTP is powered up */ 1599#define CST4319_SPROM_SEL 0x00000040 /* use SPROM, OTP is powered up */ 1600#define CST4319_OTP_SEL 0x00000080 /* use OTP, OTP is powered up */ 1601#define CST4319_OTP_PWRDN 0x000000c0 /* use SPROM, OTP is powered down */ 1602#define CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */ 1603#define CST4319_REMAP_SEL_MASK 0x00000600 1604#define CST4319_ILPDIV_EN 0x00000800 1605#define CST4319_XTAL_PD_POL 0x00001000 1606#define CST4319_LPO_SEL 0x00002000 1607#define CST4319_RES_INIT_MODE 0x0000c000 1608#define CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */ 1609#define CST4319_CBUCK_MODE_MASK 0x00060000 1610#define CST4319_CBUCK_MODE_BURST 0x00020000 1611#define CST4319_CBUCK_MODE_LPBURST 0x00060000 1612#define CST4319_RCAL_VALID 0x01000000 1613#define CST4319_RCAL_VALUE_MASK 0x3e000000 1614#define CST4319_RCAL_VALUE_SHIFT 25 1615 1616#define PMU1_PLL0_CHIPCTL0 0 1617#define PMU1_PLL0_CHIPCTL1 1 1618#define PMU1_PLL0_CHIPCTL2 2 1619#define CCTL_4319USB_XTAL_SEL_MASK 0x00180000 1620#define CCTL_4319USB_XTAL_SEL_SHIFT 19 1621#define CCTL_4319USB_48MHZ_PLL_SEL 1 1622#define CCTL_4319USB_24MHZ_PLL_SEL 2 1623 1624/* PMU resources for 4336 */ 1625#define RES4336_CBUCK_LPOM 0 1626#define RES4336_CBUCK_BURST 1 1627#define RES4336_CBUCK_LP_PWM 2 1628#define RES4336_CBUCK_PWM 3 1629#define RES4336_CLDO_PU 4 1630#define RES4336_DIS_INT_RESET_PD 5 1631#define RES4336_ILP_REQUEST 6 1632#define RES4336_LNLDO_PU 7 1633#define RES4336_LDO3P3_PU 8 1634#define RES4336_OTP_PU 9 1635#define RES4336_XTAL_PU 10 1636#define RES4336_ALP_AVAIL 11 1637#define RES4336_RADIO_PU 12 1638#define RES4336_BG_PU 13 1639#define RES4336_VREG1p4_PU_PU 14 1640#define RES4336_AFE_PWRSW_PU 15 1641#define RES4336_RX_PWRSW_PU 16 1642#define RES4336_TX_PWRSW_PU 17 1643#define RES4336_BB_PWRSW_PU 18 1644#define RES4336_SYNTH_PWRSW_PU 19 1645#define RES4336_MISC_PWRSW_PU 20 1646#define RES4336_LOGEN_PWRSW_PU 21 1647#define RES4336_BBPLL_PWRSW_PU 22 1648#define RES4336_MACPHY_CLKAVAIL 23 1649#define RES4336_HT_AVAIL 24 1650#define RES4336_RSVD 25 1651 1652/* 4336 chip-specific ChipStatus register bits */ 1653#define CST4336_SPI_MODE_MASK 0x00000001 1654#define CST4336_SPROM_PRESENT 0x00000002 1655#define CST4336_OTP_PRESENT 0x00000004 1656#define CST4336_ARMREMAP_0 0x00000008 1657#define CST4336_ILPDIV_EN_MASK 0x00000010 1658#define CST4336_ILPDIV_EN_SHIFT 4 1659#define CST4336_XTAL_PD_POL_MASK 0x00000020 1660#define CST4336_XTAL_PD_POL_SHIFT 5 1661#define CST4336_LPO_SEL_MASK 0x00000040 1662#define CST4336_LPO_SEL_SHIFT 6 1663#define CST4336_RES_INIT_MODE_MASK 0x00000180 1664#define CST4336_RES_INIT_MODE_SHIFT 7 1665#define CST4336_CBUCK_MODE_MASK 0x00000600 1666#define CST4336_CBUCK_MODE_SHIFT 9 1667 1668/* 4330 resources */ 1669#define RES4330_CBUCK_LPOM 0 1670#define RES4330_CBUCK_BURST 1 1671#define RES4330_CBUCK_LP_PWM 2 1672#define RES4330_CBUCK_PWM 3 1673#define RES4330_CLDO_PU 4 1674#define RES4330_DIS_INT_RESET_PD 5 1675#define RES4330_ILP_REQUEST 6 1676#define RES4330_LNLDO_PU 7 1677#define RES4330_LDO3P3_PU 8 1678#define RES4330_OTP_PU 9 1679#define RES4330_XTAL_PU 10 1680#define RES4330_ALP_AVAIL 11 1681#define RES4330_RADIO_PU 12 1682#define RES4330_BG_PU 13 1683#define RES4330_VREG1p4_PU_PU 14 1684#define RES4330_AFE_PWRSW_PU 15 1685#define RES4330_RX_PWRSW_PU 16 1686#define RES4330_TX_PWRSW_PU 17 1687#define RES4330_BB_PWRSW_PU 18 1688#define RES4330_SYNTH_PWRSW_PU 19 1689#define RES4330_MISC_PWRSW_PU 20 1690#define RES4330_LOGEN_PWRSW_PU 21 1691#define RES4330_BBPLL_PWRSW_PU 22 1692#define RES4330_MACPHY_CLKAVAIL 23 1693#define RES4330_HT_AVAIL 24 1694#define RES4330_5gRX_PWRSW_PU 25 1695#define RES4330_5gTX_PWRSW_PU 26 1696#define RES4330_5g_LOGEN_PWRSW_PU 27 1697 1698/* 4330 chip-specific ChipStatus register bits */ 1699#define CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */ 1700#define CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */ 1701#define CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */ 1702#define CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */ 1703#define CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */ 1704#define CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */ 1705#define CST4330_OTP_PRESENT 0x00000010 1706#define CST4330_LPO_AUTODET_EN 0x00000020 1707#define CST4330_ARMREMAP_0 0x00000040 1708#define CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */ 1709#define CST4330_ILPDIV_EN 0x00000100 1710#define CST4330_LPO_SEL 0x00000200 1711#define CST4330_RES_INIT_MODE_SHIFT 10 1712#define CST4330_RES_INIT_MODE_MASK 0x00000c00 1713#define CST4330_CBUCK_MODE_SHIFT 12 1714#define CST4330_CBUCK_MODE_MASK 0x00003000 1715#define CST4330_CBUCK_POWER_OK 0x00004000 1716#define CST4330_BB_PLL_LOCKED 0x00008000 1717#define SOCDEVRAM_4330_BP_ADDR 0x1E000000 1718#define SOCDEVRAM_4330_ARM_ADDR 0x00800000 1719 1720/* 4313 resources */ 1721#define RES4313_BB_PU_RSRC 0 1722#define RES4313_ILP_REQ_RSRC 1 1723#define RES4313_XTAL_PU_RSRC 2 1724#define RES4313_ALP_AVAIL_RSRC 3 1725#define RES4313_RADIO_PU_RSRC 4 1726#define RES4313_BG_PU_RSRC 5 1727#define RES4313_VREG1P4_PU_RSRC 6 1728#define RES4313_AFE_PWRSW_RSRC 7 1729#define RES4313_RX_PWRSW_RSRC 8 1730#define RES4313_TX_PWRSW_RSRC 9 1731#define RES4313_BB_PWRSW_RSRC 10 1732#define RES4313_SYNTH_PWRSW_RSRC 11 1733#define RES4313_MISC_PWRSW_RSRC 12 1734#define RES4313_BB_PLL_PWRSW_RSRC 13 1735#define RES4313_HT_AVAIL_RSRC 14 1736#define RES4313_MACPHY_CLK_AVAIL_RSRC 15 1737 1738/* 4313 chip-specific ChipStatus register bits */ 1739#define CST4313_SPROM_PRESENT 1 1740#define CST4313_OTP_PRESENT 2 1741#define CST4313_SPROM_OTP_SEL_MASK 0x00000002 1742#define CST4313_SPROM_OTP_SEL_SHIFT 0 1743 1744/* 4313 Chip specific ChipControl register bits */ 1745#define CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ 1746 1747/* 43228 resources */ 1748#define RES43228_NOT_USED 0 1749#define RES43228_ILP_REQUEST 1 1750#define RES43228_XTAL_PU 2 1751#define RES43228_ALP_AVAIL 3 1752#define RES43228_PLL_EN 4 1753#define RES43228_HT_PHY_AVAIL 5 1754 1755/* 43228 chipstatus reg bits */ 1756#define CST43228_ILP_DIV_EN 0x1 1757#define CST43228_OTP_PRESENT 0x2 1758#define CST43228_SERDES_REFCLK_PADSEL 0x4 1759#define CST43228_SDIO_MODE 0x8 1760#define CST43228_SDIO_OTP_PRESENT 0x10 1761#define CST43228_SDIO_RESET 0x20 1762 1763/* 4706 chipstatus reg bits */ 1764#define CST4706_PKG_OPTION (1<<0) /* 0: full-featured package 1: low-cost package */ 1765#define CST4706_SFLASH_PRESENT (1<<1) /* 0: parallel, 1: serial flash is present */ 1766#define CST4706_SFLASH_TYPE (1<<2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */ 1767#define CST4706_MIPS_BENDIAN (1<<3) /* 0: little, 1: big endian */ 1768#define CST4706_PCIE1_DISABLE (1<<5) /* PCIE1 enable strap pin */ 1769 1770/* 4706 flashstrconfig reg bits */ 1771#define FLSTRCF4706_MASK 0x000000ff 1772#define FLSTRCF4706_SF1 0x00000001 /* 2nd serial flash present */ 1773#define FLSTRCF4706_PF1 0x00000002 /* 2nd parallel flash present */ 1774#define FLSTRCF4706_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */ 1775#define FLSTRCF4706_NF1 0x00000008 /* 2nd NAND flash present */ 1776#define FLSTRCF4706_1ST_MADDR_SEG_MASK 0x000000f0 /* Valid value mask */ 1777#define FLSTRCF4706_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */ 1778#define FLSTRCF4706_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */ 1779#define FLSTRCF4706_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */ 1780#define FLSTRCF4706_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */ 1781#define FLSTRCF4706_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */ 1782#define FLSTRCF4706_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */ 1783#define FLSTRCF4706_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */ 1784 1785 1786/* 1787* Maximum delay for the PMU state transition in us. 1788* This is an upper bound intended for spinwaits etc. 1789*/ 1790#define PMU_MAX_TRANSITION_DLY 15000 1791 1792/* PMU resource up transition time in ILP cycles */ 1793#define PMURES_UP_TRANSITION 2 1794 1795/* 1796* Information from BT to WLAN over eci_inputlo, eci_inputmi & 1797* eci_inputhi register. Rev >=21 1798*/ 1799/* Fields in eci_inputlo register - [0:31] */ 1800#define ECI_INLO_TASKTYPE_MASK 0x0000000f /* [3:0] - 4 bits */ 1801#define ECI_INLO_TASKTYPE_SHIFT 0 1802#define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */ 1803#define ECI_INLO_PKTDUR_SHIFT 4 1804#define ECI_INLO_ROLE_MASK 0x00000100 /* [8] - 1 bits */ 1805#define ECI_INLO_ROLE_SHIFT 8 1806#define ECI_INLO_MLP_MASK 0x00000e00 /* [11:9] - 3 bits */ 1807#define ECI_INLO_MLP_SHIFT 9 1808#define ECI_INLO_TXPWR_MASK 0x000ff000 /* [19:12] - 8 bits */ 1809#define ECI_INLO_TXPWR_SHIFT 12 1810#define ECI_INLO_RSSI_MASK 0x0ff00000 /* [27:20] - 8 bits */ 1811#define ECI_INLO_RSSI_SHIFT 20 1812#define ECI_INLO_VAD_MASK 0x10000000 /* [28] - 1 bits */ 1813#define ECI_INLO_VAD_SHIFT 28 1814 1815/* 1816* Register eci_inputlo bitfield values. 1817* - BT packet type information bits [7:0] 1818*/ 1819/* [3:0] - Task (link) type */ 1820#define BT_ACL 0x00 1821#define BT_SCO 0x01 1822#define BT_eSCO 0x02 1823#define BT_A2DP 0x03 1824#define BT_SNIFF 0x04 1825#define BT_PAGE_SCAN 0x05 1826#define BT_INQUIRY_SCAN 0x06 1827#define BT_PAGE 0x07 1828#define BT_INQUIRY 0x08 1829#define BT_MSS 0x09 1830#define BT_PARK 0x0a 1831#define BT_RSSISCAN 0x0b 1832#define BT_MD_ACL 0x0c 1833#define BT_MD_eSCO 0x0d 1834#define BT_SCAN_WITH_SCO_LINK 0x0e 1835#define BT_SCAN_WITHOUT_SCO_LINK 0x0f 1836/* [7:4] = packet duration code */ 1837/* [8] - Master / Slave */ 1838#define BT_MASTER 0 1839#define BT_SLAVE 1 1840/* [11:9] - multi-level priority */ 1841#define BT_LOWEST_PRIO 0x0 1842#define BT_HIGHEST_PRIO 0x3 1843/* [19:12] - BT transmit power */ 1844/* [27:20] - BT RSSI */ 1845/* [28] - VAD silence */ 1846/* [31:29] - Undefined */ 1847/* Register eci_inputmi values - [32:63] - none defined */ 1848/* [63:32] - Undefined */ 1849 1850/* Information from WLAN to BT over eci_output register. */ 1851/* Fields in eci_output register - [0:31] */ 1852#define ECI48_OUT_MASKMAGIC_HIWORD 0x55550000 1853#define ECI_OUT_CHANNEL_MASK(ccrev) ((ccrev) < 35 ? 0xf : (ECI48_OUT_MASKMAGIC_HIWORD | 0xf000)) 1854#define ECI_OUT_CHANNEL_SHIFT(ccrev) ((ccrev) < 35 ? 0 : 12) 1855#define ECI_OUT_BW_MASK(ccrev) ((ccrev) < 35 ? 0x70 : (ECI48_OUT_MASKMAGIC_HIWORD | 0xe00)) 1856#define ECI_OUT_BW_SHIFT(ccrev) ((ccrev) < 35 ? 4 : 9) 1857#define ECI_OUT_ANTENNA_MASK(ccrev) ((ccrev) < 35 ? 0x80 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x100)) 1858#define ECI_OUT_ANTENNA_SHIFT(ccrev) ((ccrev) < 35 ? 7 : 8) 1859#define ECI_OUT_SIMUL_TXRX_MASK(ccrev) \ 1860 ((ccrev) < 35 ? 0x10000 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x80)) 1861#define ECI_OUT_SIMUL_TXRX_SHIFT(ccrev) ((ccrev) < 35 ? 16 : 7) 1862#define ECI_OUT_FM_DISABLE_MASK(ccrev) \ 1863 ((ccrev) < 35 ? 0x40000 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x40)) 1864#define ECI_OUT_FM_DISABLE_SHIFT(ccrev) ((ccrev) < 35 ? 18 : 6) 1865 1866/* Indicate control of ECI bits between s/w and dot11mac. 1867 * 0 => FW control, 1=> MAC/ucode control 1868 1869 * Current assignment (ccrev >= 35): 1870 * 0 - TxConf (ucode) 1871 * 38 - FM disable (wl) 1872 * 39 - Allow sim rx (ucode) 1873 * 40 - Num antennas (wl) 1874 * 43:41 - WLAN channel exclusion BW (wl) 1875 * 47:44 - WLAN channel (wl) 1876 * 1877 * (ccrev < 35) 1878 * 15:0 - wl 1879 * 16 - 1880 * 18 - FM disable 1881 * 30 - wl interrupt 1882 * 31 - ucode interrupt 1883 * others - unassigned (presumed to be with dot11mac/ucode) 1884 */ 1885#define ECI_MACCTRL_BITS 0xbffb0000 1886#define ECI_MACCTRLLO_BITS 0x1 1887#define ECI_MACCTRLHI_BITS 0x80 1888 1889 1890/* SECI configuration */ 1891#define SECI_MODE_UART 0x0 1892#define SECI_MODE_SECI 0x1 1893#define SECI_MODE_LEGACY_3WIRE_BT 0x2 1894#define SECI_MODE_LEGACY_3WIRE_WLAN 0x3 1895#define SECI_MODE_HALF_SECI 0x4 1896 1897#define SECI_RESET (1 << 0) 1898#define SECI_RESET_BAR_UART (1 << 1) 1899#define SECI_ENAB_SECI_ECI (1 << 2) 1900#define SECI_ENAB_SECIOUT_DIS (1 << 3) 1901#define SECI_MODE_MASK 0x7 1902#define SECI_MODE_SHIFT 4 /* (bits 5, 6, 7) */ 1903#define SECI_UPD_SECI (1 << 7) 1904 1905/* seci clk_ctl_st bits */ 1906#define CLKCTL_STS_SECI_CLK_REQ (1 << 8) 1907#define CLKCTL_STS_SECI_CLK_AVAIL (1 << 24) 1908 1909#define SECI_UART_MSR_CTS_STATE (1 << 0) 1910#define SECI_UART_MSR_RTS_STATE (1 << 1) 1911#define SECI_UART_SECI_IN_STATE (1 << 2) 1912#define SECI_UART_SECI_IN2_STATE (1 << 3) 1913 1914/* SECI UART LCR/MCR register bits */ 1915#define SECI_UART_LCR_STOP_BITS (1 << 0) /* 0 - 1bit, 1 - 2bits */ 1916#define SECI_UART_LCR_PARITY_EN (1 << 1) 1917#define SECI_UART_LCR_PARITY (1 << 2) /* 0 - odd, 1 - even */ 1918#define SECI_UART_LCR_RX_EN (1 << 3) 1919#define SECI_UART_LCR_LBRK_CTRL (1 << 4) /* 1 => SECI_OUT held low */ 1920#define SECI_UART_LCR_TXO_EN (1 << 5) 1921#define SECI_UART_LCR_RTSO_EN (1 << 6) 1922#define SECI_UART_LCR_SLIPMODE_EN (1 << 7) 1923#define SECI_UART_LCR_RXCRC_CHK (1 << 8) 1924#define SECI_UART_LCR_TXCRC_INV (1 << 9) 1925#define SECI_UART_LCR_TXCRC_LSBF (1 << 10) 1926#define SECI_UART_LCR_TXCRC_EN (1 << 11) 1927 1928#define SECI_UART_MCR_TX_EN (1 << 0) 1929#define SECI_UART_MCR_PRTS (1 << 1) 1930#define SECI_UART_MCR_SWFLCTRL_EN (1 << 2) 1931#define SECI_UART_MCR_HIGHRATE_EN (1 << 3) 1932#define SECI_UART_MCR_LOOPBK_EN (1 << 4) 1933#define SECI_UART_MCR_AUTO_RTS (1 << 5) 1934#define SECI_UART_MCR_AUTO_TX_DIS (1 << 6) 1935#define SECI_UART_MCR_BAUD_ADJ_EN (1 << 7) 1936#define SECI_UART_MCR_XONOFF_RPT (1 << 9) 1937 1938/* WLAN channel numbers - used from wifi.h */ 1939 1940/* WLAN BW */ 1941#define ECI_BW_20 0x0 1942#define ECI_BW_25 0x1 1943#define ECI_BW_30 0x2 1944#define ECI_BW_35 0x3 1945#define ECI_BW_40 0x4 1946#define ECI_BW_45 0x5 1947#define ECI_BW_50 0x6 1948#define ECI_BW_ALL 0x7 1949 1950/* WLAN - number of antenna */ 1951#define WLAN_NUM_ANT1 TXANT_0 1952#define WLAN_NUM_ANT2 TXANT_1 1953 1954#endif /* _SBCHIPC_H */ 1955