1/*
2 * BCM43XX PCI/E core sw API definitions.
3 *
4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * $Id: nicpci.h,v 13.10.12.3 2011/01/27 19:03:20 Exp $
19 */
20
21#ifndef	_NICPCI_H
22#define	_NICPCI_H
23
24#if defined(BCMDHDUSB) || (defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS))
25#define pcicore_find_pci_capability(a, b, c, d) (0)
26#define pcie_readreg(a, b, c, d) (0)
27#define pcie_writereg(a, b, c, d, e) (0)
28
29#define pcie_clkreq(a, b, c)	(0)
30#define pcie_lcreg(a, b, c)	(0)
31
32#define pcicore_init(a, b, c) (0x0dadbeef)
33#define pcicore_deinit(a)	do { } while (0)
34#define pcicore_attach(a, b, c)	do { } while (0)
35#define pcicore_hwup(a)		do { } while (0)
36#define pcicore_up(a, b)	do { } while (0)
37#define pcicore_sleep(a)	do { } while (0)
38#define pcicore_down(a, b)	do { } while (0)
39
40#define pcie_war_ovr_aspm_update(a, b)	do { } while (0)
41#define pcie_power_save_enable(a, b)	do { } while (0)
42
43#define pcicore_pcieserdesreg(a, b, c, d, e) (0)
44#define pcicore_pciereg(a, b, c, d, e) (0)
45#if defined(BCMDBG_DUMP)
46#define pcicore_dump_pcieregs(a, b) (0)
47#endif
48
49#define pcicore_pmecap_fast(a)	(FALSE)
50#define pcicore_pmeen(a)	do { } while (0)
51#define pcicore_pmeclr(a)	do { } while (0)
52#define pcicore_pmestat(a)	(FALSE)
53#define pcie_set_request_size(pch, size) do { } while (0)
54#define pcie_get_request_size(pch) (0)
55#else
56struct sbpcieregs;
57
58extern uint8 pcicore_find_pci_capability(osl_t *osh, uint8 req_cap_id,
59                                         uchar *buf, uint32 *buflen);
60extern uint pcie_readreg(osl_t *osh, struct sbpcieregs *pcieregs, uint addrtype, uint offset);
61extern uint pcie_writereg(osl_t *osh, struct sbpcieregs *pcieregs, uint addrtype, uint offset,
62                          uint val);
63
64extern uint8 pcie_clkreq(void *pch, uint32 mask, uint32 val);
65extern uint32 pcie_lcreg(void *pch, uint32 mask, uint32 val);
66
67extern void *pcicore_init(si_t *sih, osl_t *osh, void *regs);
68extern void pcicore_deinit(void *pch);
69extern void pcicore_attach(void *pch, char *pvars, int state);
70extern void pcicore_hwup(void *pch);
71extern void pcicore_up(void *pch, int state);
72extern void pcicore_sleep(void *pch);
73extern void pcicore_down(void *pch, int state);
74
75extern void pcie_war_ovr_aspm_update(void *pch, uint8 aspm);
76extern void pcie_power_save_enable(void *pch, bool enable);
77
78extern uint32 pcicore_pcieserdesreg(void *pch, uint32 mdioslave, uint32 offset,
79                                    uint32 mask, uint32 val);
80
81extern uint32 pcicore_pciereg(void *pch, uint32 offset, uint32 mask, uint32 val, uint type);
82
83#if defined(BCMDBG_DUMP)
84extern int pcicore_dump_pcieregs(void *pch, struct bcmstrbuf *b);
85#endif
86
87
88extern bool pcicore_pmecap_fast(osl_t *osh);
89extern void pcicore_pmeen(void *pch);
90extern void pcicore_pmeclr(void *pch);
91extern bool pcicore_pmestat(void *pch);
92extern void pcie_set_request_size(void *pch, uint16 size);
93extern uint16 pcie_get_request_size(void *pch);
94#endif
95
96#endif	/* _NICPCI_H */
97