1/* 2 * Definitiosn for Jtag taps in HND chips. 3 * 4 * $Id: hndjtagdefs.h,v 13.3 2009/07/02 20:33:03 Exp $ 5 * 6 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 15 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 17 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 18 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#ifndef _HNDJTAGDEFS_H 22#define _HNDJTAGDEFS_H 23 24/* Jtag access regs are all 32 bits */ 25#define JRBITS 32 26 27/* MIPS mode defines: */ 28 29#define MIPS_IR_SIZE 5 30#define MIPS_DR_SIZE 32 31 32#define MIPS_IDCODE 1 33#define MIPS_BYPASS 0x1f 34 35/* Register addresses */ 36#define MIPS_ADDR 0x08 37#define MIPS_DATA 0x09 38#define MIPS_CTRL 0x0a 39 40/* DMA related bits in the Control register */ 41#define DMA_SZ1 0x00000000 42#define DMA_SZ2 0x00000080 43#define DMA_SZ4 0x00000100 44#define DMA_SZ3 0x00000180 45#define DMA_READ 0x00000200 46#define DMA_ERROR 0x00000400 47#define DMA_START 0x00000800 48#define DMA_BREAK 0x00001000 49#define DMA_ACC 0x00020000 50 51/* CC mode defines: */ 52 53#define CCJT_IR_SIZE 8 54#define CCJT_DR_SIZE 32 55 56#define CCJT_USER_BASE 0x20 57 58#define CCJT_IDCODE 1 59#define CCJT_BYPASS 0xff 60 61/* Register addresses */ 62#define CHIPC_ADDR 0x30 63#define CHIPC_DATA 0x32 64#define CHIPC_CTRL 0x34 65 66#define CHIPC_RO 1 /* Or in this to get the read-only address */ 67 68/* Control register bits */ 69#define CCC_BE0 0x00000001 70#define CCC_BE1 0x00000002 71#define CCC_BE2 0x00000004 72#define CCC_BE3 0x00000008 73#define CCC_SZ1 (CCC_BE0) 74#define CCC_SZ2 (CCC_BE1 | CCC_BE0) 75#define CCC_SZ4 (CCC_BE3 | CCC_BE2 | CCC_BE1 | CCC_BE0) 76#define CCC_READ 0x00000010 77#define CCC_START 0x00000020 78#define CCC_ERROR 0x00000040 79 80/* Bits written into the control register need to be shifted */ 81#define CCC_WR_SHIFT 25 82 83/* LV mode defines: */ 84 85#define LV_IR_SIZE 32 86#define LV_DR_SIZE 32 87 88#define LV_BASE 0xfe03ff3a 89#define LV_REG_MASK 0x01f00000 90#define LV_REG_SHIFT 20 91#define LV_RO 0x00080000 92#define LV_USER_BASE 0x10 93 94/* Keystone base */ 95#define LV_BASE_KY 0xfe07ff3a 96 97/* Register addresses */ 98#define LV_CAP 0 99#define LV_CHAIN_CTL 1 100#define LV_ADDR 2 101#define LV_ADDRH 3 102#define LV_DATA 4 103#define LV_CTRL 5 104#define LV_OTP_CTL 6 105#define LV_OTP_STAT 7 106 107#define LV_REG_IR(reg) (LV_BASE | (((reg) << LV_REG_SHIFT) & LV_REG_MASK)) 108#define LV_REG_ROIR(reg) (LV_BASE | LV_RO | (((reg) << LV_REG_SHIFT) & LV_REG_MASK)) 109#define LV_UREG_IR(reg) (LV_BASE | ((((reg) + LV_USER_BASE) << LV_REG_SHIFT) & LV_REG_MASK)) 110#define LV_UREG_ROIR(reg) \ 111 (LV_BASE | LV_RO | ((((reg) + LV_USER_BASE) << LV_REG_SHIFT) & LV_REG_MASK)) 112 113#define LV_REG_IR_KY(reg) (LV_BASE_KY | (((reg) << LV_REG_SHIFT) & LV_REG_MASK)) 114 115#define LV_IDCODE 0xfffffffe 116#define LV_BYPASS 0xffffffff 117 118#define IDC_MFG_MASK 0x00000fff 119#define IDC_PART_MASK 0x0ffff000 120#define IDC_PART_SHIFT 12 121#define IDC_REV_MASK 0xf0000000 122#define IDC_REV_SHIFT 28 123 124#define JEDEC_BRCM 0x17f 125 126#endif /* _HNDJTAGDEFS_H */ 127