1/* 2 * SROM format definition. 3 * 4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id: bcmsrom_fmt.h,v 13.21.4.7 2011-02-05 19:11:33 Exp $ 19 */ 20 21#ifndef _bcmsrom_fmt_h_ 22#define _bcmsrom_fmt_h_ 23 24#define SROM_MAXREV 9 /* max revisiton supported by driver */ 25 26/* Maximum srom: 6 Kilobits == 768 bytes */ 27#define SROM_MAX 768 28#define SROM_MAXW 384 29#define VARS_MAX 4096 30 31/* PCI fields */ 32#define PCI_F0DEVID 48 33 34 35#define SROM_WORDS 64 36 37#define SROM3_SWRGN_OFF 28 /* s/w region offset in words */ 38 39#define SROM_SSID 2 40 41#define SROM_WL1LHMAXP 29 42 43#define SROM_WL1LPAB0 30 44#define SROM_WL1LPAB1 31 45#define SROM_WL1LPAB2 32 46 47#define SROM_WL1HPAB0 33 48#define SROM_WL1HPAB1 34 49#define SROM_WL1HPAB2 35 50 51#define SROM_MACHI_IL0 36 52#define SROM_MACMID_IL0 37 53#define SROM_MACLO_IL0 38 54#define SROM_MACHI_ET0 39 55#define SROM_MACMID_ET0 40 56#define SROM_MACLO_ET0 41 57#define SROM_MACHI_ET1 42 58#define SROM_MACMID_ET1 43 59#define SROM_MACLO_ET1 44 60#define SROM3_MACHI 37 61#define SROM3_MACMID 38 62#define SROM3_MACLO 39 63 64#define SROM_BXARSSI2G 40 65#define SROM_BXARSSI5G 41 66 67#define SROM_TRI52G 42 68#define SROM_TRI5GHL 43 69 70#define SROM_RXPO52G 45 71 72#define SROM2_ENETPHY 45 73 74#define SROM_AABREV 46 75/* Fields in AABREV */ 76#define SROM_BR_MASK 0x00ff 77#define SROM_CC_MASK 0x0f00 78#define SROM_CC_SHIFT 8 79#define SROM_AA0_MASK 0x3000 80#define SROM_AA0_SHIFT 12 81#define SROM_AA1_MASK 0xc000 82#define SROM_AA1_SHIFT 14 83 84#define SROM_WL0PAB0 47 85#define SROM_WL0PAB1 48 86#define SROM_WL0PAB2 49 87 88#define SROM_LEDBH10 50 89#define SROM_LEDBH32 51 90 91#define SROM_WL10MAXP 52 92 93#define SROM_WL1PAB0 53 94#define SROM_WL1PAB1 54 95#define SROM_WL1PAB2 55 96 97#define SROM_ITT 56 98 99#define SROM_BFL 57 100#define SROM_BFL2 28 101#define SROM3_BFL2 61 102 103#define SROM_AG10 58 104 105#define SROM_CCODE 59 106 107#define SROM_OPO 60 108 109#define SROM3_LEDDC 62 110 111#define SROM_CRCREV 63 112 113/* SROM Rev 4: Reallocate the software part of the srom to accomodate 114 * MIMO features. It assumes up to two PCIE functions and 440 bytes 115 * of useable srom i.e. the useable storage in chips with OTP that 116 * implements hardware redundancy. 117 */ 118 119#define SROM4_WORDS 220 120 121#define SROM4_SIGN 32 122#define SROM4_SIGNATURE 0x5372 123 124#define SROM4_BREV 33 125 126#define SROM4_BFL0 34 127#define SROM4_BFL1 35 128#define SROM4_BFL2 36 129#define SROM4_BFL3 37 130#define SROM5_BFL0 37 131#define SROM5_BFL1 38 132#define SROM5_BFL2 39 133#define SROM5_BFL3 40 134 135#define SROM4_MACHI 38 136#define SROM4_MACMID 39 137#define SROM4_MACLO 40 138#define SROM5_MACHI 41 139#define SROM5_MACMID 42 140#define SROM5_MACLO 43 141 142#define SROM4_CCODE 41 143#define SROM4_REGREV 42 144#define SROM5_CCODE 34 145#define SROM5_REGREV 35 146 147#define SROM4_LEDBH10 43 148#define SROM4_LEDBH32 44 149#define SROM5_LEDBH10 59 150#define SROM5_LEDBH32 60 151 152#define SROM4_LEDDC 45 153#define SROM5_LEDDC 45 154 155#define SROM4_AA 46 156#define SROM4_AA2G_MASK 0x00ff 157#define SROM4_AA2G_SHIFT 0 158#define SROM4_AA5G_MASK 0xff00 159#define SROM4_AA5G_SHIFT 8 160 161#define SROM4_AG10 47 162#define SROM4_AG32 48 163 164#define SROM4_TXPID2G 49 165#define SROM4_TXPID5G 51 166#define SROM4_TXPID5GL 53 167#define SROM4_TXPID5GH 55 168 169#define SROM4_TXRXC 61 170#define SROM4_TXCHAIN_MASK 0x000f 171#define SROM4_TXCHAIN_SHIFT 0 172#define SROM4_RXCHAIN_MASK 0x00f0 173#define SROM4_RXCHAIN_SHIFT 4 174#define SROM4_SWITCH_MASK 0xff00 175#define SROM4_SWITCH_SHIFT 8 176 177 178/* Per-path fields */ 179#define MAX_PATH_SROM 4 180#define SROM4_PATH0 64 181#define SROM4_PATH1 87 182#define SROM4_PATH2 110 183#define SROM4_PATH3 133 184 185#define SROM4_2G_ITT_MAXP 0 186#define SROM4_2G_PA 1 187#define SROM4_5G_ITT_MAXP 5 188#define SROM4_5GLH_MAXP 6 189#define SROM4_5G_PA 7 190#define SROM4_5GL_PA 11 191#define SROM4_5GH_PA 15 192 193/* Fields in the ITT_MAXP and 5GLH_MAXP words */ 194#define B2G_MAXP_MASK 0xff 195#define B2G_ITT_SHIFT 8 196#define B5G_MAXP_MASK 0xff 197#define B5G_ITT_SHIFT 8 198#define B5GH_MAXP_MASK 0xff 199#define B5GL_MAXP_SHIFT 8 200 201/* All the miriad power offsets */ 202#define SROM4_2G_CCKPO 156 203#define SROM4_2G_OFDMPO 157 204#define SROM4_5G_OFDMPO 159 205#define SROM4_5GL_OFDMPO 161 206#define SROM4_5GH_OFDMPO 163 207#define SROM4_2G_MCSPO 165 208#define SROM4_5G_MCSPO 173 209#define SROM4_5GL_MCSPO 181 210#define SROM4_5GH_MCSPO 189 211#define SROM4_CDDPO 197 212#define SROM4_STBCPO 198 213#define SROM4_BW40PO 199 214#define SROM4_BWDUPPO 200 215 216#define SROM4_CRCREV 219 217 218 219/* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6. 220 * This is acombined srom for both MIMO and SISO boards, usable in 221 * the .130 4Kilobit OTP with hardware redundancy. 222 */ 223 224#define SROM8_SIGN 64 225 226#define SROM8_BREV 65 227 228#define SROM8_BFL0 66 229#define SROM8_BFL1 67 230#define SROM8_BFL2 68 231#define SROM8_BFL3 69 232 233#define SROM8_MACHI 70 234#define SROM8_MACMID 71 235#define SROM8_MACLO 72 236 237#define SROM8_CCODE 73 238#define SROM8_REGREV 74 239 240#define SROM8_LEDBH10 75 241#define SROM8_LEDBH32 76 242 243#define SROM8_LEDDC 77 244 245#define SROM8_AA 78 246 247#define SROM8_AG10 79 248#define SROM8_AG32 80 249 250#define SROM8_TXRXC 81 251 252#define SROM8_BXARSSI2G 82 253#define SROM8_BXARSSI5G 83 254#define SROM8_TRI52G 84 255#define SROM8_TRI5GHL 85 256#define SROM8_RXPO52G 86 257 258#define SROM8_FEM2G 87 259#define SROM8_FEM5G 88 260#define SROM8_FEM_ANTSWLUT_MASK 0xf800 261#define SROM8_FEM_ANTSWLUT_SHIFT 11 262#define SROM8_FEM_TR_ISO_MASK 0x0700 263#define SROM8_FEM_TR_ISO_SHIFT 8 264#define SROM8_FEM_PDET_RANGE_MASK 0x00f8 265#define SROM8_FEM_PDET_RANGE_SHIFT 3 266#define SROM8_FEM_EXTPA_GAIN_MASK 0x0006 267#define SROM8_FEM_EXTPA_GAIN_SHIFT 1 268#define SROM8_FEM_TSSIPOS_MASK 0x0001 269#define SROM8_FEM_TSSIPOS_SHIFT 0 270 271#define SROM8_THERMAL 89 272 273/* Temp sense related entries */ 274#define SROM8_MPWR_RAWTS 90 275#define SROM8_TS_SLP_OPT_CORRX 91 276/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */ 277#define SROM8_FOC_HWIQ_IQSWP 92 278 279#define SROM8_EXTLNAGAIN 93 280 281/* Temperature delta for PHY calibration */ 282#define SROM8_PHYCAL_TEMPDELTA 94 283 284/* Measured power 1 & 2, 0-13 bits at offset 95, MSB 2 bits are unused for now. */ 285#define SROM8_MPWR_1_AND_2 95 286 287 288/* Per-path offsets & fields */ 289#define SROM8_PATH0 96 290#define SROM8_PATH1 112 291#define SROM8_PATH2 128 292#define SROM8_PATH3 144 293 294#define SROM8_2G_ITT_MAXP 0 295#define SROM8_2G_PA 1 296#define SROM8_5G_ITT_MAXP 4 297#define SROM8_5GLH_MAXP 5 298#define SROM8_5G_PA 6 299#define SROM8_5GL_PA 9 300#define SROM8_5GH_PA 12 301 302/* All the miriad power offsets */ 303#define SROM8_2G_CCKPO 160 304 305#define SROM8_2G_OFDMPO 161 306#define SROM8_5G_OFDMPO 163 307#define SROM8_5GL_OFDMPO 165 308#define SROM8_5GH_OFDMPO 167 309 310#define SROM8_2G_MCSPO 169 311#define SROM8_5G_MCSPO 177 312#define SROM8_5GL_MCSPO 185 313#define SROM8_5GH_MCSPO 193 314 315#define SROM8_CDDPO 201 316#define SROM8_STBCPO 202 317#define SROM8_BW40PO 203 318#define SROM8_BWDUPPO 204 319 320/* SISO PA parameters are in the path0 spaces */ 321#define SROM8_SISO 96 322 323/* Legacy names for SISO PA paramters */ 324#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP) 325#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA) 326#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1) 327#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2) 328#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP) 329#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP) 330#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA) 331#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1) 332#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2) 333#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA) 334#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1) 335#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2) 336#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA) 337#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1) 338#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2) 339 340#define SROM8_CRCREV 219 341 342/* SROM REV 9 */ 343#define SROM9_2GPO_CCKBW20 160 344#define SROM9_2GPO_CCKBW20UL 161 345#define SROM9_2GPO_LOFDMBW20 162 346#define SROM9_2GPO_LOFDMBW20UL 164 347 348#define SROM9_5GLPO_LOFDMBW20 166 349#define SROM9_5GLPO_LOFDMBW20UL 168 350#define SROM9_5GMPO_LOFDMBW20 170 351#define SROM9_5GMPO_LOFDMBW20UL 172 352#define SROM9_5GHPO_LOFDMBW20 174 353#define SROM9_5GHPO_LOFDMBW20UL 176 354 355#define SROM9_2GPO_MCSBW20 178 356#define SROM9_2GPO_MCSBW20UL 180 357#define SROM9_2GPO_MCSBW40 182 358 359#define SROM9_5GLPO_MCSBW20 184 360#define SROM9_5GLPO_MCSBW20UL 186 361#define SROM9_5GLPO_MCSBW40 188 362#define SROM9_5GMPO_MCSBW20 190 363#define SROM9_5GMPO_MCSBW20UL 192 364#define SROM9_5GMPO_MCSBW40 194 365#define SROM9_5GHPO_MCSBW20 196 366#define SROM9_5GHPO_MCSBW20UL 198 367#define SROM9_5GHPO_MCSBW40 200 368 369#define SROM9_PO_MCS32 202 370#define SROM9_PO_LOFDM40DUP 203 371#define SROM8_RXGAINERR_2G 205 372#define SROM8_RXGAINERR_5GL 206 373#define SROM8_RXGAINERR_5GM 207 374#define SROM8_RXGAINERR_5GH 208 375#define SROM8_RXGAINERR_5GU 209 376#define SROM8_PCIEINGRESS_WAR 211 377#define SROM9_SAR 212 378 379#define SROM8_NOISELVL_2G 213 380#define SROM8_NOISELVL_5GL 214 381#define SROM8_NOISELVL_5GM 215 382#define SROM8_NOISELVL_5GH 216 383#define SROM8_NOISELVL_5GU 217 384 385#define SROM9_REV_CRC 219 386 387typedef struct { 388 uint8 tssipos; /* TSSI positive slope, 1: positive, 0: negative */ 389 uint8 extpagain; /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */ 390 uint8 pdetrange; /* support 32 combinations of different Pdet dynamic ranges */ 391 uint8 triso; /* TR switch isolation */ 392 uint8 antswctrllut; /* antswctrl lookup table configuration: 32 possible choices */ 393} srom_fem_t; 394 395#endif /* _bcmsrom_fmt_h_ */ 396