1/* 2 * Copyright (c) 2004-2007 Atheros Communications Inc. 3 * All rights reserved. 4 * 5 * $ATH_LICENSE_HOSTSDK0_C$ 6 * 7 * This file contains the definitions for AR6001 registers 8 * that may be directly manipulated by Host software. 9 */ 10 11#ifndef __AR6KHWREG_H__ 12#define __AR6KHWREG_H__ 13 14#ifdef __cplusplus 15extern "C" { 16#endif 17 18/* Host registers */ 19#define HOST_INT_STATUS_ADDRESS 0x00000400 20#define CPU_INT_STATUS_ADDRESS 0x00000401 21#define ERROR_INT_STATUS_ADDRESS 0x00000402 22#define INT_STATUS_ENABLE_ADDRESS 0x00000418 23#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 24#define COUNT_ADDRESS 0x00000420 25#define COUNT_DEC_ADDRESS 0x00000440 26#define WINDOW_DATA_ADDRESS 0x00000474 27#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 28#define WINDOW_READ_ADDR_ADDRESS 0x0000047c 29 30/* Target addresses */ 31#define RESET_CONTROL_ADDRESS 0x0c000000 32#define MC_REMAP_VALID_ADDRESS 0x0c004080 33#define MC_REMAP_SIZE_ADDRESS 0x0c004100 34#define MC_REMAP_COMPARE_ADDRESS 0x0c004180 35#define MC_REMAP_TARGET_ADDRESS 0x0c004200 36#define LOCAL_COUNT_ADDRESS 0x0c014080 37#define LOCAL_SCRATCH_ADDRESS 0x0c0140c0 38 39 40#define INT_STATUS_ENABLE_ERROR_MSB 7 41#define INT_STATUS_ENABLE_ERROR_LSB 7 42#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080 43#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB) 44#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) 45 46#define INT_STATUS_ENABLE_CPU_MSB 6 47#define INT_STATUS_ENABLE_CPU_LSB 6 48#define INT_STATUS_ENABLE_CPU_MASK 0x00000040 49#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB) 50#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) 51 52#define INT_STATUS_ENABLE_COUNTER_MSB 4 53#define INT_STATUS_ENABLE_COUNTER_LSB 4 54#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 55#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB) 56#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK) 57 58#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3 59#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0 60#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f 61#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB) 62#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK) 63 64#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1 65#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 66#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 67#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) 68#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 69 70#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0 71#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 72#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 73#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) 74#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 75 76 77#define CPU_INT_STATUS_ENABLE_BIT_MSB 7 78#define CPU_INT_STATUS_ENABLE_BIT_LSB 0 79#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 80#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB) 81#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK) 82 83#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7 84#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 85#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 86#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB) 87#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) 88 89#define ERROR_INT_STATUS_WAKEUP_MSB 2 90#define ERROR_INT_STATUS_WAKEUP_LSB 2 91#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 92#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB) 93#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK) 94 95#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1 96#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 97#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 98#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 99#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) 100 101#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0 102#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 103#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 104#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB) 105#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) 106 107#define HOST_INT_STATUS_ERROR_MSB 7 108#define HOST_INT_STATUS_ERROR_LSB 7 109#define HOST_INT_STATUS_ERROR_MASK 0x00000080 110#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) 111#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK) 112 113#define HOST_INT_STATUS_CPU_MSB 6 114#define HOST_INT_STATUS_CPU_LSB 6 115#define HOST_INT_STATUS_CPU_MASK 0x00000040 116#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) 117#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK) 118 119#define HOST_INT_STATUS_COUNTER_MSB 4 120#define HOST_INT_STATUS_COUNTER_LSB 4 121#define HOST_INT_STATUS_COUNTER_MASK 0x00000010 122#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) 123#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK) 124 125#define RESET_CONTROL_WARM_RST_MSB 7 126#define RESET_CONTROL_WARM_RST_LSB 7 127#define RESET_CONTROL_WARM_RST_MASK 0x00000080 128#define RESET_CONTROL_WARM_RST_GET(x) (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB) 129#define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK) 130 131#define RESET_CONTROL_COLD_RST_MSB 8 132#define RESET_CONTROL_COLD_RST_LSB 8 133#define RESET_CONTROL_COLD_RST_MASK 0x00000100 134#define RESET_CONTROL_COLD_RST_GET(x) (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB) 135#define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK) 136 137#define RESET_CAUSE_LAST_MSB 2 138#define RESET_CAUSE_LAST_LSB 0 139#define RESET_CAUSE_LAST_MASK 0x00000007 140#define RESET_CAUSE_LAST_GET(x) (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB) 141#define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK) 142 143#ifdef __cplusplus 144} 145#endif 146 147#endif /* __AR6KHWREG_H__ */ 148