1/* 2 * Ralink RT305x SoC specific setup 3 * 4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 6 * 7 * Parts of this file are based on Ralink's 2.6.21 BSP 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published 11 * by the Free Software Foundation. 12 */ 13 14#include <linux/kernel.h> 15#include <linux/init.h> 16#include <linux/module.h> 17 18#include <asm/mipsregs.h> 19 20#include <asm/mach-ralink/common.h> 21#include <asm/mach-ralink/ramips_gpio.h> 22#include <asm/mach-ralink/rt305x.h> 23#include <asm/mach-ralink/rt305x_regs.h> 24 25void __iomem * rt305x_sysc_base; 26void __iomem * rt305x_memc_base; 27enum rt305x_soc_type rt305x_soc; 28 29static unsigned long rt5350_get_mem_size(void) 30{ 31 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); 32 unsigned long ret; 33 u32 t; 34 35 t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG); 36 t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) & 37 RT5350_SYSCFG0_DRAM_SIZE_MASK; 38 39 switch (t) { 40 case RT5350_SYSCFG0_DRAM_SIZE_2M: 41 ret = 2 * 1024 * 1024; 42 break; 43 case RT5350_SYSCFG0_DRAM_SIZE_8M: 44 ret = 8 * 1024 * 1024; 45 break; 46 case RT5350_SYSCFG0_DRAM_SIZE_16M: 47 ret = 16 * 1024 * 1024; 48 break; 49 case RT5350_SYSCFG0_DRAM_SIZE_32M: 50 ret = 32 * 1024 * 1024; 51 break; 52 case RT5350_SYSCFG0_DRAM_SIZE_64M: 53 ret = 64 * 1024 * 1024; 54 break; 55 default: 56 panic("rt5350: invalid DRAM size: %u", t); 57 break; 58 } 59 60 return ret; 61} 62 63void __init ramips_soc_prom_init(void) 64{ 65 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); 66 const char *name = "unknown"; 67 u32 n0; 68 u32 n1; 69 u32 id; 70 71 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); 72 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); 73 74 if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) { 75 unsigned long icache_sets; 76 77 icache_sets = (read_c0_config1() >> 22) & 7; 78 if (icache_sets == 1) { 79 rt305x_soc = RT305X_SOC_RT3050; 80 name = "RT3050"; 81 } else { 82 rt305x_soc = RT305X_SOC_RT3052; 83 name = "RT3052"; 84 } 85 } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) { 86 rt305x_soc = RT305X_SOC_RT3350; 87 name = "RT3350"; 88 } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { 89 rt305x_soc = RT305X_SOC_RT3352; 90 name = "RT3352"; 91 } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { 92 rt305x_soc = RT305X_SOC_RT5350; 93 name = "RT5350"; 94 } else { 95 panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); 96 } 97 98 id = __raw_readl(sysc + SYSC_REG_CHIP_ID); 99 100 snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN, 101 "Ralink %s id:%u rev:%u", 102 name, 103 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, 104 (id & CHIP_ID_REV_MASK)); 105 106 ramips_mem_base = RT305X_SDRAM_BASE; 107 108 if (soc_is_rt5350()) { 109 ramips_get_mem_size = rt5350_get_mem_size; 110 } else if (soc_is_rt305x() || soc_is_rt3350() ) { 111 ramips_mem_size_min = RT305X_MEM_SIZE_MIN; 112 ramips_mem_size_max = RT305X_MEM_SIZE_MAX; 113 } else if (soc_is_rt3352()) { 114 ramips_mem_size_min = RT3352_MEM_SIZE_MIN; 115 ramips_mem_size_max = RT3352_MEM_SIZE_MAX; 116 } else { 117 BUG(); 118 } 119} 120 121static struct ramips_gpio_chip rt305x_gpio_chips[] = { 122 { 123 .chip = { 124 .label = "RT305X-GPIO0", 125 .base = 0, 126 .ngpio = 24, 127 }, 128 .regs = { 129 [RAMIPS_GPIO_REG_INT] = 0x00, 130 [RAMIPS_GPIO_REG_EDGE] = 0x04, 131 [RAMIPS_GPIO_REG_RENA] = 0x08, 132 [RAMIPS_GPIO_REG_FENA] = 0x0c, 133 [RAMIPS_GPIO_REG_DATA] = 0x20, 134 [RAMIPS_GPIO_REG_DIR] = 0x24, 135 [RAMIPS_GPIO_REG_POL] = 0x28, 136 [RAMIPS_GPIO_REG_SET] = 0x2c, 137 [RAMIPS_GPIO_REG_RESET] = 0x30, 138 [RAMIPS_GPIO_REG_TOGGLE] = 0x34, 139 }, 140 .map_base = RT305X_PIO_BASE, 141 .map_size = RT305X_PIO_SIZE, 142 }, 143 { 144 .chip = { 145 .label = "RT305X-GPIO1", 146 .base = 24, 147 .ngpio = 16, 148 }, 149 .regs = { 150 [RAMIPS_GPIO_REG_INT] = 0x38, 151 [RAMIPS_GPIO_REG_EDGE] = 0x3c, 152 [RAMIPS_GPIO_REG_RENA] = 0x40, 153 [RAMIPS_GPIO_REG_FENA] = 0x44, 154 [RAMIPS_GPIO_REG_DATA] = 0x48, 155 [RAMIPS_GPIO_REG_DIR] = 0x4c, 156 [RAMIPS_GPIO_REG_POL] = 0x50, 157 [RAMIPS_GPIO_REG_SET] = 0x54, 158 [RAMIPS_GPIO_REG_RESET] = 0x58, 159 [RAMIPS_GPIO_REG_TOGGLE] = 0x5c, 160 }, 161 .map_base = RT305X_PIO_BASE, 162 .map_size = RT305X_PIO_SIZE, 163 }, 164 { 165 .chip = { 166 .label = "RT305X-GPIO2", 167 .base = 40, 168 .ngpio = 12, 169 }, 170 .regs = { 171 [RAMIPS_GPIO_REG_INT] = 0x60, 172 [RAMIPS_GPIO_REG_EDGE] = 0x64, 173 [RAMIPS_GPIO_REG_RENA] = 0x68, 174 [RAMIPS_GPIO_REG_FENA] = 0x6c, 175 [RAMIPS_GPIO_REG_DATA] = 0x70, 176 [RAMIPS_GPIO_REG_DIR] = 0x74, 177 [RAMIPS_GPIO_REG_POL] = 0x78, 178 [RAMIPS_GPIO_REG_SET] = 0x7c, 179 [RAMIPS_GPIO_REG_RESET] = 0x80, 180 [RAMIPS_GPIO_REG_TOGGLE] = 0x84, 181 }, 182 .map_base = RT305X_PIO_BASE, 183 .map_size = RT305X_PIO_SIZE, 184 }, 185}; 186 187static struct ramips_gpio_data rt305x_gpio_data = { 188 .chips = rt305x_gpio_chips, 189 .num_chips = ARRAY_SIZE(rt305x_gpio_chips), 190}; 191 192static void rt305x_gpio_reserve(int first, int last) 193{ 194 for (; first <= last; first++) 195 gpio_request(first, "reserved"); 196} 197 198void __init rt305x_gpio_init(u32 mode) 199{ 200 u32 t; 201 202 rt305x_sysc_wr(mode, SYSC_REG_GPIO_MODE); 203 204 ramips_gpio_init(&rt305x_gpio_data); 205 if ((mode & RT305X_GPIO_MODE_I2C) == 0) 206 rt305x_gpio_reserve(RT305X_GPIO_I2C_SD, RT305X_GPIO_I2C_SCLK); 207 208 if ((mode & RT305X_GPIO_MODE_SPI) == 0) 209 rt305x_gpio_reserve(RT305X_GPIO_SPI_EN, RT305X_GPIO_SPI_CLK); 210 211 t = mode >> RT305X_GPIO_MODE_UART0_SHIFT; 212 t &= RT305X_GPIO_MODE_UART0_MASK; 213 switch (t) { 214 case RT305X_GPIO_MODE_UARTF: 215 case RT305X_GPIO_MODE_PCM_UARTF: 216 case RT305X_GPIO_MODE_PCM_I2S: 217 case RT305X_GPIO_MODE_I2S_UARTF: 218 rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_14); 219 break; 220 case RT305X_GPIO_MODE_PCM_GPIO: 221 rt305x_gpio_reserve(RT305X_GPIO_10, RT305X_GPIO_14); 222 break; 223 case RT305X_GPIO_MODE_GPIO_UARTF: 224 case RT305X_GPIO_MODE_GPIO_I2S: 225 rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_10); 226 break; 227 } 228 229 if ((mode & RT305X_GPIO_MODE_UART1) == 0) 230 rt305x_gpio_reserve(RT305X_GPIO_UART1_TXD, 231 RT305X_GPIO_UART1_RXD); 232 233 if ((mode & RT305X_GPIO_MODE_JTAG) == 0) 234 rt305x_gpio_reserve(RT305X_GPIO_JTAG_TDO, RT305X_GPIO_JTAG_TDI); 235 236 if ((mode & RT305X_GPIO_MODE_MDIO) == 0) 237 rt305x_gpio_reserve(RT305X_GPIO_MDIO_MDC, 238 RT305X_GPIO_MDIO_MDIO); 239 240 if ((mode & RT305X_GPIO_MODE_SDRAM) == 0) 241 rt305x_gpio_reserve(RT305X_GPIO_SDRAM_MD16, 242 RT305X_GPIO_SDRAM_MD31); 243 244 if ((mode & RT305X_GPIO_MODE_RGMII) == 0) 245 rt305x_gpio_reserve(RT305X_GPIO_GE0_TXD0, 246 RT305X_GPIO_GE0_RXCLK); 247} 248