1/* 2 * Moschip MCS814x generic interrupt controller routines 3 * 4 * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org> 5 * 6 * Licensed under the GPLv2 7 */ 8#include <linux/init.h> 9#include <linux/irq.h> 10#include <linux/io.h> 11#include <linux/of.h> 12#include <linux/of_address.h> 13#include <linux/irqdomain.h> 14 15#include <asm/exception.h> 16#include <asm/mach/irq.h> 17#include <mach/mcs814x.h> 18 19void __iomem *mcs814x_intc_base; 20 21static void __init mcs814x_alloc_gc(void __iomem *base, unsigned int irq_start, 22 unsigned int num) 23{ 24 struct irq_chip_generic *gc; 25 struct irq_chip_type *ct; 26 27 gc = irq_alloc_generic_chip("mcs814x-intc", 1, 28 irq_start, base, handle_level_irq); 29 if (!gc) 30 panic("unable to allocate generic irq chip"); 31 32 ct = gc->chip_types; 33 ct->chip.irq_ack = irq_gc_unmask_enable_reg; 34 ct->chip.irq_mask = irq_gc_mask_clr_bit; 35 ct->chip.irq_unmask = irq_gc_mask_set_bit; 36 ct->regs.mask = MCS814X_IRQ_MASK; 37 ct->regs.enable = MCS814X_IRQ_ICR; 38 39 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, 40 IRQ_NOREQUEST, 0); 41 42 /* Clear all interrupts */ 43 writel_relaxed(0xffffffff, base + MCS814X_IRQ_ICR); 44} 45 46static const struct of_device_id mcs814x_intc_ids[] = { 47 { .compatible = "moschip,mcs814x-intc" }, 48 { /* sentinel */ }, 49}; 50 51void __init mcs814x_of_irq_init(void) 52{ 53 struct device_node *np; 54 55 np = of_find_matching_node(NULL, mcs814x_intc_ids); 56 if (!np) 57 panic("unable to find compatible intc node in dtb\n"); 58 59 mcs814x_intc_base = of_iomap(np, 0); 60 if (!mcs814x_intc_base) 61 panic("unable to map intc cpu registers\n"); 62 63 irq_domain_add_simple(np, 0); 64 65 of_node_put(np); 66 67 mcs814x_alloc_gc(mcs814x_intc_base, 0, 32); 68} 69 70