1/******************************************************************************
2**
3** FILE NAME    : dwc_otg_ifx.h
4** PROJECT      : Twinpass/Danube
5** MODULES      : DWC OTG USB
6**
7** DATE         : 12 April 2007
8** AUTHOR       : Sung Winder
9** DESCRIPTION  : Platform specific initialization.
10** COPYRIGHT    :       Copyright (c) 2007
11**                      Infineon Technologies AG
12**                      2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
13**                      Hsin-chu City, 300 Taiwan.
14**
15**    This program is free software; you can redistribute it and/or modify
16**    it under the terms of the GNU General Public License as published by
17**    the Free Software Foundation; either version 2 of the License, or
18**    (at your option) any later version.
19**
20** HISTORY
21** $Date          $Author         $Comment
22** 12 April 2007   Sung Winder     Initiate Version
23*******************************************************************************/
24#if !defined(__DWC_OTG_IFX_H__)
25#define __DWC_OTG_IFX_H__
26
27#include <linux/irq.h>
28#include <irq.h>
29
30// 20070316, winder added.
31#ifndef SZ_256K
32#define SZ_256K                         0x00040000
33#endif
34
35extern void dwc_otg_power_on (void);
36
37/* FIXME: The current Linux-2.6 do not have these header files, but anyway, we need these. */
38// #include <asm/danube/danube.h>
39// #include <asm/ifx/irq.h>
40
41/* winder, I used the Danube parameter as default. *
42 * We could change this through module param.      */
43#define IFX_USB_IOMEM_BASE 0x1e101000
44#define IFX_USB_IOMEM_SIZE SZ_256K
45#define IFX_USB_IRQ LTQ_USB_INT
46
47/**
48 * This function is called to set correct clock gating and power.
49 * For Twinpass/Danube board.
50 */
51#ifndef DANUBE_RCU_BASE_ADDR
52#define DANUBE_RCU_BASE_ADDR            (0xBF203000)
53#endif
54
55#ifndef DANUBE_CGU
56#define DANUBE_CGU                          (0xBF103000)
57#endif
58#ifndef DANUBE_CGU_IFCCR
59/***CGU Interface Clock Control Register***/
60#define DANUBE_CGU_IFCCR                        ((volatile u32*)(DANUBE_CGU+ 0x0018))
61#endif
62
63#ifndef DANUBE_PMU
64#define DANUBE_PMU                              (KSEG1+0x1F102000)
65#endif
66#ifndef DANUBE_PMU_PWDCR
67/* PMU Power down Control Register */
68#define DANUBE_PMU_PWDCR                        ((volatile u32*)(DANUBE_PMU+0x001C))
69#endif
70
71
72#define DANUBE_RCU_UBSCFG  ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x18))
73#define DANUBE_USBCFG_HDSEL_BIT    11	// 0:host, 1:device
74#define DANUBE_USBCFG_HOST_END_BIT 10	// 0:little_end, 1:big_end
75#define DANUBE_USBCFG_SLV_END_BIT  9	// 0:little_end, 1:big_end
76
77extern void ltq_mask_and_ack_irq(struct irq_data *d);
78
79static void inline mask_and_ack_ifx_irq(int x)
80{
81	struct irq_data d;
82	d.irq = x;
83	ltq_mask_and_ack_irq(&d);
84}
85#endif //__DWC_OTG_IFX_H__
86