1/******************************************************************************
2**
3** FILE NAME    : dwc_otg_cil_ifx.h
4** PROJECT      : Twinpass/Danube
5** MODULES      : DWC OTG USB
6**
7** DATE         : 07 Sep. 2007
8** AUTHOR       : Sung Winder
9** DESCRIPTION  : Default param value.
10** COPYRIGHT    :       Copyright (c) 2007
11**                      Infineon Technologies AG
12**                      2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
13**                      Hsin-chu City, 300 Taiwan.
14**
15**    This program is free software; you can redistribute it and/or modify
16**    it under the terms of the GNU General Public License as published by
17**    the Free Software Foundation; either version 2 of the License, or
18**    (at your option) any later version.
19**
20** HISTORY
21** $Date          $Author         $Comment
22** 12 April 2007   Sung Winder     Initiate Version
23*******************************************************************************/
24#if !defined(__DWC_OTG_CIL_IFX_H__)
25#define __DWC_OTG_CIL_IFX_H__
26
27/* ================ Default param value ================== */
28#define dwc_param_opt_default 1
29#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE
30#define dwc_param_dma_enable_default 1
31#define dwc_param_dma_burst_size_default 32
32#define dwc_param_speed_default DWC_SPEED_PARAM_HIGH
33#define dwc_param_host_support_fs_ls_low_power_default 0
34#define dwc_param_host_ls_low_power_phy_clk_default DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ
35#define dwc_param_enable_dynamic_fifo_default 1
36#define dwc_param_data_fifo_size_default 2048
37#define dwc_param_dev_rx_fifo_size_default 1024
38#define dwc_param_dev_nperio_tx_fifo_size_default 1024
39#define dwc_param_dev_perio_tx_fifo_size_default 768
40#define dwc_param_host_rx_fifo_size_default 640
41#define dwc_param_host_nperio_tx_fifo_size_default 640
42#define dwc_param_host_perio_tx_fifo_size_default 768
43#define dwc_param_max_transfer_size_default 65535
44#define dwc_param_max_packet_count_default 511
45#define dwc_param_host_channels_default 16
46#define dwc_param_dev_endpoints_default 6
47#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
48#define dwc_param_phy_utmi_width_default 16
49#define dwc_param_phy_ulpi_ddr_default 0
50#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
51#define dwc_param_i2c_enable_default 0
52#define dwc_param_ulpi_fs_ls_default 0
53#define dwc_param_ts_dline_default 0
54
55/* ======================================================= */
56
57#endif // __DWC_OTG_CIL_IFX_H__
58
59