1/******************************************************************************* 2Copyright (C) Marvell International Ltd. and its affiliates 3 4This software file (the "File") is owned and distributed by Marvell 5International Ltd. and/or its affiliates ("Marvell") under the following 6alternative licensing terms. Once you have made an election to distribute the 7File under one of the following license alternatives, please (i) delete this 8introductory statement regarding license alternatives, (ii) delete the two 9license alternatives that you have not elected to use and (iii) preserve the 10Marvell copyright notice above. 11 12******************************************************************************** 13Marvell Commercial License Option 14 15If you received this File from Marvell and you have entered into a commercial 16license agreement (a "Commercial License") with Marvell, the File is licensed 17to you under the terms of the applicable Commercial License. 18 19******************************************************************************** 20Marvell GPL License Option 21 22If you received this File from Marvell, you may opt to use, redistribute and/or 23modify this File in accordance with the terms and conditions of the General 24Public License Version 2, June 1991 (the "GPL License"), a copy of which is 25available along with the File in the license.txt file or by writing to the Free 26Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or 27on the worldwide web at http://www.gnu.org/licenses/gpl.txt. 28 29THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED 30WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY 31DISCLAIMED. The GPL License provides additional details about this warranty 32disclaimer. 33******************************************************************************** 34Marvell BSD License Option 35 36If you received this File from Marvell, you may opt to use, redistribute and/or 37modify this File under the following licensing terms. 38Redistribution and use in source and binary forms, with or without modification, 39are permitted provided that the following conditions are met: 40 41 * Redistributions of source code must retain the above copyright notice, 42 this list of conditions and the following disclaimer. 43 44 * Redistributions in binary form must reproduce the above copyright 45 notice, this list of conditions and the following disclaimer in the 46 documentation and/or other materials provided with the distribution. 47 48 * Neither the name of Marvell nor the names of its contributors may be 49 used to endorse or promote products derived from this software without 50 specific prior written permission. 51 52THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 53ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 54WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 55DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 56ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 57(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 58LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 59ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 61SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 63*******************************************************************************/ 64 65#ifndef __INCmvSFlashSpecH 66#define __INCmvSFlashSpecH 67 68/* Constants */ 69#define MV_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */ 70#define MV_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */ 71#define MV_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */ 72#define MV_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */ 73#define MV_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */ 74#define MV_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */ 75#define MV_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */ 76#define MV_SFLASH_RDID_REPLY_LENGTH 3 /* 1B manf ID and 2B device ID */ 77#define MV_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */ 78#define MV_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */ 79#define MV_SFLASH_WRSR_CMND_LENGTH 2 /* 1B opcode + 1B status value */ 80#define MV_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */ 81#define MV_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */ 82 83/* Status Register Bit Masks */ 84#define MV_SFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0; write in progress */ 85#define MV_SFLASH_STATUS_REG_WP_OFFSET 2 /* bit 2-4; write protect option */ 86#define MV_SFLASH_STATUS_REG_SRWD_OFFSET 7 /* bit 7; lock status register write */ 87#define MV_SFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET) 88#define MV_SFLASH_STATUS_REG_SRWD_MASK (0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET) 89 90#define MV_SFLASH_MAX_WAIT_LOOP 1000000 91#define MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000 92 93#define MV_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ 94#define MV_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ 95#define MV_SFLASH_NO_SPECIFIC_OPCD 0x00 96 97/********************************/ 98/* ST M25Pxxx Device Specific */ 99/********************************/ 100 101/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ 102#define MV_M25PXXX_ST_MANF_ID 0x20 103#define MV_M25P32_DEVICE_ID 0x2016 104#define MV_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */ 105#define MV_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ 106#define MV_M25P32_FAST_READ_DUMMY_BYTES 1 107#define MV_M25P64_DEVICE_ID 0x2017 108#define MV_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */ 109#define MV_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ 110#define MV_M25P64_FAST_READ_DUMMY_BYTES 1 111#define MV_M25P128_DEVICE_ID 0x2018 112#define MV_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */ 113#define MV_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ 114#define MV_M25P128_FAST_READ_DUMMY_BYTES 1 115 116 117/* Sector Sizes and population per device model*/ 118#define MV_M25P32_SECTOR_SIZE 0x10000 /* 64K */ 119#define MV_M25P64_SECTOR_SIZE 0x10000 /* 64K */ 120#define MV_M25P128_SECTOR_SIZE 0x40000 /* 256K */ 121#define MV_M25P32_SECTOR_NUMBER 64 122#define MV_M25P64_SECTOR_NUMBER 128 123#define MV_M25P128_SECTOR_NUMBER 64 124#define MV_M25P_PAGE_SIZE 0x100 /* 256 byte */ 125 126#define MV_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */ 127#define MV_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */ 128#define MV_M25P_RDID_CMND_OPCD 0x9F /* Read ID */ 129#define MV_M25P_RDSR_CMND_OPCD 0x05 /* Read Status Register */ 130#define MV_M25P_WRSR_CMND_OPCD 0x01 /* Write Status Register */ 131#define MV_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */ 132#define MV_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ 133#define MV_M25P_PP_CMND_OPCD 0x02 /* Page Program */ 134#define MV_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */ 135#define MV_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */ 136#define MV_M25P_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ 137 138/* Status Register Write Protect Bit Masks - 3bits */ 139#define MV_M25P_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) 140#define MV_M25P_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) 141#define MV_M25P_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) 142#define MV_M25P_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) 143#define MV_M25P_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) 144#define MV_M25P_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) 145#define MV_M25P_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) 146#define MV_M25P_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) 147#define MV_M25P_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) 148 149/************************************/ 150/* MXIC MX25L6405 Device Specific */ 151/************************************/ 152 153/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ 154#define MV_MXIC_MANF_ID 0xC2 155#define MV_MX25L6405_DEVICE_ID 0x2017 156#define MV_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */ 157#define MV_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ 158#define MV_MX25L6405_FAST_READ_DUMMY_BYTES 1 159#define MV_MXIC_DP_EXIT_DELAY 30 /* 30 ms */ 160 161/* Sector Sizes and population per device model*/ 162#define MV_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */ 163#define MV_MX25L6405_SECTOR_NUMBER 128 164#define MV_MXIC_PAGE_SIZE 0x100 /* 256 byte */ 165 166#define MV_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */ 167#define MV_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */ 168#define MV_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */ 169#define MV_MX25L_RDSR_CMND_OPCD 0x05 /* Read Status Register */ 170#define MV_MX25L_WRSR_CMND_OPCD 0x01 /* Write Status Register */ 171#define MV_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */ 172#define MV_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ 173#define MV_MX25L_PP_CMND_OPCD 0x02 /* Page Program */ 174#define MV_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */ 175#define MV_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */ 176#define MV_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */ 177#define MV_MX25L_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ 178 179/* Status Register Write Protect Bit Masks - 4bits */ 180#define MV_MX25L_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) 181#define MV_MX25L_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) 182#define MV_MX25L_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) 183#define MV_MX25L_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) 184#define MV_MX25L_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) 185#define MV_MX25L_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) 186#define MV_MX25L_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) 187#define MV_MX25L_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) 188#define MV_MX25L_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) 189#define MV_MX25L_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) 190 191/************************************/ 192/* SPANSION S25FL128P Device Specific */ 193/************************************/ 194 195/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ 196#define MV_SPANSION_MANF_ID 0x01 197#define MV_S25FL128_DEVICE_ID 0x2018 198#define MV_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */ 199#define MV_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */ 200#define MV_S25FL128_FAST_READ_DUMMY_BYTES 1 201 202/* Sector Sizes and population per device model*/ 203#define MV_S25FL128_SECTOR_SIZE 0x40000 /* 256K */ 204#define MV_S25FL128_SECTOR_NUMBER 64 205#define MV_S25FL_PAGE_SIZE 0x100 /* 256 byte */ 206 207#define MV_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */ 208#define MV_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */ 209#define MV_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */ 210#define MV_S25FL_RDSR_CMND_OPCD 0x05 /* Read Status Register */ 211#define MV_S25FL_WRSR_CMND_OPCD 0x01 /* Write Status Register */ 212#define MV_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */ 213#define MV_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ 214#define MV_S25FL_PP_CMND_OPCD 0x02 /* Page Program */ 215#define MV_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */ 216#define MV_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */ 217#define MV_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */ 218#define MV_S25FL_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ 219 220/* Status Register Write Protect Bit Masks - 4bits */ 221#define MV_S25FL_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) 222#define MV_S25FL_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) 223#define MV_S25FL_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) 224#define MV_S25FL_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) 225#define MV_S25FL_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) 226#define MV_S25FL_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) 227#define MV_S25FL_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) 228#define MV_S25FL_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) 229#define MV_S25FL_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) 230#define MV_S25FL_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) 231 232#endif /* __INCmvSFlashSpecH */ 233 234