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The GPL License provides additional details about this warranty 32disclaimer. 33******************************************************************************** 34Marvell BSD License Option 35 36If you received this File from Marvell, you may opt to use, redistribute and/or 37modify this File under the following licensing terms. 38Redistribution and use in source and binary forms, with or without modification, 39are permitted provided that the following conditions are met: 40 41 * Redistributions of source code must retain the above copyright notice, 42 this list of conditions and the following disclaimer. 43 44 * Redistributions in binary form must reproduce the above copyright 45 notice, this list of conditions and the following disclaimer in the 46 documentation and/or other materials provided with the distribution. 47 48 * Neither the name of Marvell nor the names of its contributors may be 49 used to endorse or promote products derived from this software without 50 specific prior written permission. 51 52THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 53ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 54WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 55DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 56ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 57(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 58LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 59ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 61SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 63*******************************************************************************/ 64 65#ifndef __INCmvPciUtilsh 66#define __INCmvPciUtilsh 67 68/* 69This module only support scanning of Header type 00h of pci devices 70There is no suppotr for Header type 01h of pci devices ( PCI bridges ) 71*/ 72 73/* includes */ 74#include "mvSysHwConfig.h" 75#include "pci-if/mvPciIf.h" 76#include "pci/mvPciRegs.h" 77 78 79 80/* PCI base address low bar mask */ 81#define PCI_ERROR_CODE 0xffffffff 82 83#define PCI_BRIDGE_CLASS 0x6 84#define P2P_BRIDGE_SUB_CLASS_CODE 0x4 85 86 87#define P2P_BUSSES_NUM 0x18 88#define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C 89#define P2P_MEM_BASE_LIMIT 0x20 90#define P2P_PREF_MEM_BASE_LIMIT 0x24 91#define P2P_PREF_BASE_UPPER_32 0x28 92#define P2P_PREF_LIMIT_UPPER_32 0x2C 93#define P2P_IO_BASE_LIMIT_UPPER_16 0x30 94#define P2P_EXP_ROM 0x38 95 96/* P2P_BUSSES_NUM (PBM) */ 97 98#define PBM_PRIME_BUS_NUM_OFFS 0 99#define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS) 100 101#define PBM_SEC_BUS_NUM_OFFS 8 102#define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS) 103 104#define PBM_SUB_BUS_NUM_OFFS 16 105#define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS) 106 107#define PBM_SEC_LAT_TMR_OFFS 24 108#define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS) 109 110/* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */ 111 112#define PIBLSS_IO_BASE_OFFS 0 113#define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS) 114 115#define PIBLSS_ADD_CAP_OFFS 0 116#define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS) 117#define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS) 118#define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS) 119 120#define PIBLSS_LOW_ADDR_OFFS 0 121#define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS) 122 123#define PIBLSS_HIGH_ADDR_OFFS 12 124#define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS) 125 126#define PIBLSS_IO_LIMIT_OFFS 8 127#define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS) 128 129#define PIBLSS_SEC_STATUS_OFFS 16 130#define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS) 131 132 133/* P2P_MEM_BASE_LIMIT (PMBL)*/ 134 135#define PMBL_MEM_BASE_OFFS 0 136#define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS) 137 138#define PMBL_MEM_LIMIT_OFFS 16 139#define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS) 140 141 142#define PMBL_LOW_ADDR_OFFS 0 143#define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS) 144 145#define PMBL_HIGH_ADDR_OFFS 20 146#define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS) 147 148 149/* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */ 150 151#define PRMBL_PREF_MEM_BASE_OFFS 0 152#define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS) 153 154#define PRMBL_PREF_MEM_LIMIT_OFFS 16 155#define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<<PRMBL_PREF_MEM_LIMIT_OFFS) 156 157#define PRMBL_LOW_ADDR_OFFS 0 158#define PRMBL_LOW_ADDR_MASK (0xFFFFF << PRMBL_LOW_ADDR_OFFS) 159 160#define PRMBL_HIGH_ADDR_OFFS 20 161#define PRMBL_HIGH_ADDR_MASK (0xFFF << PRMBL_HIGH_ADDR_OFFS) 162 163#define PRMBL_ADD_CAP_OFFS 0 164#define PRMBL_ADD_CAP_MASK (0xf << PRMBL_ADD_CAP_OFFS) 165#define PRMBL_ADD_CAP_32BIT (0x0 << PRMBL_ADD_CAP_OFFS) 166#define PRMBL_ADD_CAP_64BIT (0x1 << PRMBL_ADD_CAP_OFFS) 167 168/* P2P_IO_BASE_LIMIT_UPPER_16 (PIBLU) */ 169 170#define PRBU_IO_UPP_BASE_OFFS 0 171#define PRBU_IO_UPP_BASE_MASK (0xffff << PRBU_IO_UPP_BASE_OFFS) 172 173#define PRBU_IO_UPP_LIMIT_OFFS 16 174#define PRBU_IO_UPP_LIMIT_MASK (0xffff << PRBU_IO_UPP_LIMIT_OFFS) 175 176 177/* typedefs */ 178 179typedef enum _mvPciBarMapping 180{ 181 PCI_MEMORY_BAR, 182 PCI_IO_BAR, 183 PCI_NO_MAPPING 184}MV_PCI_BAR_MAPPING; 185 186typedef enum _mvPciBarType 187{ 188 PCI_32BIT_BAR, 189 PCI_64BIT_BAR 190}MV_PCI_BAR_TYPE; 191 192typedef enum _mvPciIntPin 193{ 194 MV_PCI_INTA = 1, 195 MV_PCI_INTB = 2, 196 MV_PCI_INTC = 3, 197 MV_PCI_INTD = 4 198}MV_PCI_INT_PIN; 199 200typedef enum _mvPciHeader 201{ 202 MV_PCI_STANDARD, 203 MV_PCI_PCI2PCI_BRIDGE 204 205}MV_PCI_HEADER; 206 207 208/* BAR structure */ 209typedef struct _pciBar 210{ 211 MV_U32 barOffset; 212 MV_U32 barBaseLow; 213 MV_U32 barBaseHigh; 214 MV_U32 barSizeLow; 215 MV_U32 barSizeHigh; 216 /* The 'barBaseAddr' is a 64-bit variable 217 that will contain the TOTAL base address 218 value achived by combining both the 'barBaseLow' 219 and the 'barBaseHigh' parameters as follows: 220 221 BIT: 63 31 0 222 | | | 223 barBaseHigh barBaseLow */ 224 MV_U64 barBaseAddr; 225 /* The 'barSize' is a 64-bit variable 226 that will contain the TOTAL size achived 227 by combining both the 'barSizeLow' and 228 the 'barSizeHigh' parameters as follows: 229 230 BIT: 63 31 0 231 | | | 232 barSizeHigh barSizeLow 233 234 NOTE: The total size described above 235 is AFTER the size calculation as 236 described in PCI spec rev2.2 */ 237 MV_U64 barSize; 238 MV_BOOL isPrefetchable; 239 MV_PCI_BAR_TYPE barType; 240 MV_PCI_BAR_MAPPING barMapping; 241 242 243} PCI_BAR; 244 245/* Device information structure */ 246typedef struct _mvPciDevice 247{ 248 /* Device specific information */ 249 MV_U32 busNumber; /* Pci agent bus number */ 250 MV_U32 deviceNum; /* Pci agent device number */ 251 MV_U32 function; /* Pci agent function number */ 252 253 MV_U32 venID; /* Pci agent Vendor ID */ 254 MV_U32 deviceID; /* Pci agent Device ID */ 255 256 MV_BOOL isFastB2BCapable; /* Capability of Fast Back to Back 257 transactions */ 258 MV_BOOL isCapListSupport; /* Support of Capability list */ 259 MV_BOOL is66MHZCapable; /* 66MHZ support */ 260 261 MV_U32 baseClassCode; /* Pci agent base Class Code */ 262 MV_U32 subClassCode; /* Pci agent sub Class Code */ 263 MV_U32 progIf; /* Pci agent Programing interface */ 264 MV_U32 revisionID; 265 266 PCI_BAR pciBar[6]; /* Pci agent bar list */ 267 268 MV_U32 p2pPrimBusNum; /* P2P Primary Bus number*/ 269 MV_U32 p2pSecBusNum; /* P2P Secondary Bus Number*/ 270 MV_U32 p2pSubBusNum; /* P2P Subordinate bus Number */ 271 MV_U32 p2pSecLatencyTimer; /* P2P Econdary Latency Timer*/ 272 MV_U32 p2pIObase; /* P2P IO Base */ 273 MV_U32 p2pIOLimit; /* P2P IO Linit */ 274 MV_BOOL bIO32; 275 MV_U32 p2pSecStatus; /* P2P Secondary Status */ 276 MV_U32 p2pMemBase; /* P2P Memory Space */ 277 MV_U32 p2pMemLimit; /* P2P Memory Limit*/ 278 MV_U32 p2pPrefMemBase; /* P2P Prefetchable Mem Base*/ 279 MV_U32 p2pPrefMemLimit; /* P2P Prefetchable Memory Limit*/ 280 MV_BOOL bPrefMem64; 281 MV_U32 p2pPrefBaseUpper32Bits;/* P2P Prefetchable upper 32 bits*/ 282 MV_U32 p2pPrefLimitUpper32Bits;/* P2P prefetchable limit upper 32*/ 283 284 285 MV_U32 pciCacheLine; /* Pci agent cache line */ 286 MV_U32 pciLatencyTimer; /* Pci agent Latency timer */ 287 MV_PCI_HEADER pciHeader; /* Pci agent header type*/ 288 MV_BOOL isMultiFunction; /* Multi function support */ 289 MV_BOOL isBISTCapable; /* Self test capable */ 290 291 MV_U32 subSysID; /* Sub System ID */ 292 MV_U32 subSysVenID; /* Sub System Vendor ID */ 293 294 MV_BOOL isExpRom; /* Expantion Rom support */ 295 MV_U32 expRomAddr; /* Expantion Rom pointer */ 296 297 MV_U32 capListPointer; /* Capability list pointer */ 298 299 MV_U32 irqLine; /* IRQ line */ 300 MV_PCI_INT_PIN intPin; /* Interrupt pin */ 301 MV_U32 minGrant; /* Minimum grant*/ 302 MV_U32 maxLatency; /* Maximum latency*/ 303 304 MV_U32 funtionsNum; /* pci agent total functions number */ 305 306 MV_U32 barsNum; 307 MV_U8 type[60]; /* class name of the pci agent */ 308 309 310} MV_PCI_DEVICE; 311 312/* PCI gloabl functions */ 313MV_STATUS mvPciClassNameGet(MV_U32 classCode, MV_8 *pType); 314 315 316/* Performs a full scan on both PCIs and returns all possible details on the 317 agents found on the bus. */ 318MV_STATUS mvPciScan(MV_U32 pciIf, 319 MV_PCI_DEVICE *pPciAgents, 320 MV_U32 *pPciAgentsNum); 321 322 323#endif /* #ifndef __INCmvPciUtilsh */ 324