1/******************************************************************************* 2Copyright (C) Marvell International Ltd. and its affiliates 3 4This software file (the "File") is owned and distributed by Marvell 5International Ltd. and/or its affiliates ("Marvell") under the following 6alternative licensing terms. Once you have made an election to distribute the 7File under one of the following license alternatives, please (i) delete this 8introductory statement regarding license alternatives, (ii) delete the two 9license alternatives that you have not elected to use and (iii) preserve the 10Marvell copyright notice above. 11 12******************************************************************************** 13Marvell Commercial License Option 14 15If you received this File from Marvell and you have entered into a commercial 16license agreement (a "Commercial License") with Marvell, the File is licensed 17to you under the terms of the applicable Commercial License. 18 19******************************************************************************** 20Marvell GPL License Option 21 22If you received this File from Marvell, you may opt to use, redistribute and/or 23modify this File in accordance with the terms and conditions of the General 24Public License Version 2, June 1991 (the "GPL License"), a copy of which is 25available along with the File in the license.txt file or by writing to the Free 26Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or 27on the worldwide web at http://www.gnu.org/licenses/gpl.txt. 28 29THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED 30WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY 31DISCLAIMED. The GPL License provides additional details about this warranty 32disclaimer. 33******************************************************************************** 34Marvell BSD License Option 35 36If you received this File from Marvell, you may opt to use, redistribute and/or 37modify this File under the following licensing terms. 38Redistribution and use in source and binary forms, with or without modification, 39are permitted provided that the following conditions are met: 40 41 * Redistributions of source code must retain the above copyright notice, 42 this list of conditions and the following disclaimer. 43 44 * Redistributions in binary form must reproduce the above copyright 45 notice, this list of conditions and the following disclaimer in the 46 documentation and/or other materials provided with the distribution. 47 48 * Neither the name of Marvell nor the names of its contributors may be 49 used to endorse or promote products derived from this software without 50 specific prior written permission. 51 52THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 53ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 54WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 55DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 56ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 57(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 58LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 59ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 61SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 63*******************************************************************************/ 64 65 66#include "cpu/mvCpu.h" 67#include "ctrlEnv/mvCtrlEnvLib.h" 68#include "ctrlEnv/mvCtrlEnvRegs.h" 69#include "ctrlEnv/sys/mvCpuIfRegs.h" 70 71/* defines */ 72#ifdef MV_DEBUG 73 #define DB(x) x 74#else 75 #define DB(x) 76#endif 77 78/* locals */ 79 80/******************************************************************************* 81* mvCpuPclkGet - Get the CPU pClk (pipe clock) 82* 83* DESCRIPTION: 84* This routine extract the CPU core clock. 85* 86* INPUT: 87* None. 88* 89* OUTPUT: 90* None. 91* 92* RETURN: 93* 32bit clock cycles in MHertz. 94* 95*******************************************************************************/ 96/* 6180 have different clk reset sampling */ 97 98static MV_U32 mvCpu6180PclkGet(MV_VOID) 99{ 100 MV_U32 tmpPClkRate=0; 101 MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; 102 103 tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); 104 tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180; 105 tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180; 106 107 tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk; 108 109 return tmpPClkRate; 110} 111 112 113MV_U32 mvCpuPclkGet(MV_VOID) 114{ 115#if defined(PCLCK_AUTO_DETECT) 116 MV_U32 tmpPClkRate=0; 117 MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; 118 119 if(mvCtrlModelGet() == MV_6180_DEV_ID) 120 return mvCpu6180PclkGet(); 121 122 tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); 123 tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate); 124 tmpPClkRate = cpuCLK[tmpPClkRate]; 125 126 return tmpPClkRate; 127#else 128 return MV_DEFAULT_PCLK 129#endif 130} 131 132/******************************************************************************* 133* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) 134* 135* DESCRIPTION: 136* This routine extract the CPU L2 clock. 137* 138* RETURN: 139* 32bit clock cycles in Hertz. 140* 141*******************************************************************************/ 142static MV_U32 mvCpu6180L2ClkGet(MV_VOID) 143{ 144 MV_U32 L2ClkRate=0; 145 MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; 146 147 L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); 148 L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180; 149 L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180; 150 151 L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk; 152 153 return L2ClkRate; 154 155} 156 157MV_U32 mvCpuL2ClkGet(MV_VOID) 158{ 159#ifdef L2CLK_AUTO_DETECT 160 MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio; 161 MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL; 162 163 if(mvCtrlModelGet() == MV_6180_DEV_ID) 164 return mvCpu6180L2ClkGet(); 165 166 pClkRate = mvCpuPclkGet(); 167 168 tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); 169 indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp); 170 171 L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]); 172 173 return L2ClkRate; 174#else 175 return MV_BOARD_DEFAULT_L2CLK; 176#endif 177} 178 179 180/******************************************************************************* 181* mvCpuNameGet - Get CPU name 182* 183* DESCRIPTION: 184* This function returns a string describing the CPU model and revision. 185* 186* INPUT: 187* None. 188* 189* OUTPUT: 190* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. 191* 192* RETURN: 193* None. 194*******************************************************************************/ 195MV_VOID mvCpuNameGet(char *pNameBuff) 196{ 197 MV_U32 cpuModel; 198 199 cpuModel = mvOsCpuPartGet(); 200 201 /* The CPU module is indicated in the Processor Version Register (PVR) */ 202 switch(cpuModel) 203 { 204 case CPU_PART_MRVL131: 205 mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet()); 206 break; 207 case CPU_PART_ARM926: 208 mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet()); 209 break; 210 case CPU_PART_ARM946: 211 mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet()); 212 break; 213 default: 214 mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet()); 215 break; 216 } /* switch */ 217 218 return; 219} 220 221 222#define MV_PROC_STR_SIZE 50 223 224static void mvCpuIfGetL2EccMode(MV_8 *buf) 225{ 226 MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG); 227 if (regVal & BIT2) 228 mvOsSPrintf(buf, "L2 ECC Enabled"); 229 else 230 mvOsSPrintf(buf, "L2 ECC Disabled"); 231} 232 233static void mvCpuIfGetL2Mode(MV_8 *buf) 234{ 235 MV_U32 regVal = 0; 236 __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ 237 if (regVal & BIT22) 238 mvOsSPrintf(buf, "L2 Enabled"); 239 else 240 mvOsSPrintf(buf, "L2 Disabled"); 241} 242 243static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) 244{ 245 MV_U32 regVal = 0; 246 __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ 247 if (regVal & BIT24) 248 mvOsSPrintf(buf, "L2 Prefetch Disabled"); 249 else 250 mvOsSPrintf(buf, "L2 Prefetch Enabled"); 251} 252 253static void mvCpuIfGetWriteAllocMode(MV_8 *buf) 254{ 255 MV_U32 regVal = 0; 256 __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ 257 if (regVal & BIT28) 258 mvOsSPrintf(buf, "Write Allocate Enabled"); 259 else 260 mvOsSPrintf(buf, "Write Allocate Disabled"); 261} 262 263static void mvCpuIfGetCpuStreamMode(MV_8 *buf) 264{ 265 MV_U32 regVal = 0; 266 __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ 267 if (regVal & BIT29) 268 mvOsSPrintf(buf, "CPU Streaming Enabled"); 269 else 270 mvOsSPrintf(buf, "CPU Streaming Disabled"); 271} 272 273static void mvCpuIfPrintCpuRegs(void) 274{ 275 MV_U32 regVal = 0; 276 277 __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ 278 mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal); 279 280 __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ 281 mvOsPrintf("Control Reg = 0x%x\n",regVal); 282 283 __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */ 284 mvOsPrintf("ID Code Reg = 0x%x\n",regVal); 285 286 __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ 287 mvOsPrintf("Cache Type Reg = 0x%x\n",regVal); 288 289} 290 291MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) 292{ 293 MV_U32 count = 0; 294 295 MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; 296 MV_8 L2_En_str[MV_PROC_STR_SIZE]; 297 MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; 298 MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; 299 MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; 300 301 mvCpuIfGetL2Mode(L2_En_str); 302 mvCpuIfGetL2EccMode(L2_ECC_str); 303 mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); 304 mvCpuIfGetWriteAllocMode(Write_Alloc_str); 305 mvCpuIfGetCpuStreamMode(Cpu_Stream_str); 306 mvCpuIfPrintCpuRegs(); 307 308 count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); 309 count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); 310 count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); 311 count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); 312 count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); 313 return count; 314} 315 316MV_U32 whoAmI(MV_VOID) 317{ 318 return 0; 319} 320 321