1/*
2 *  MikroTik RouterBOARD 4xx series support
3 *
4 *  Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
5 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 *  This program is free software; you can redistribute it and/or modify it
8 *  under the terms of the GNU General Public License version 2 as published
9 *  by the Free Software Foundation.
10 */
11
12#include <linux/platform_device.h>
13#include <linux/irq.h>
14#include <linux/mdio-gpio.h>
15#include <linux/mmc/host.h>
16#include <linux/spi/spi.h>
17#include <linux/spi/flash.h>
18#include <linux/spi/mmc_spi.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/partitions.h>
21
22#include <asm/mach-ath79/ar71xx_regs.h>
23#include <asm/mach-ath79/ath79.h>
24#include <asm/mach-ath79/rb4xx_cpld.h>
25
26#include "common.h"
27#include "dev-eth.h"
28#include "dev-gpio-buttons.h"
29#include "dev-leds-gpio.h"
30#include "dev-usb.h"
31#include "machtypes.h"
32#include "pci.h"
33
34#define RB4XX_GPIO_USER_LED	4
35#define RB4XX_GPIO_RESET_SWITCH	7
36
37#define RB4XX_GPIO_CPLD_BASE	32
38#define RB4XX_GPIO_CPLD_LED1	(RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1)
39#define RB4XX_GPIO_CPLD_LED2	(RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2)
40#define RB4XX_GPIO_CPLD_LED3	(RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3)
41#define RB4XX_GPIO_CPLD_LED4	(RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4)
42#define RB4XX_GPIO_CPLD_LED5	(RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5)
43
44#define RB4XX_KEYS_POLL_INTERVAL	20	/* msecs */
45#define RB4XX_KEYS_DEBOUNCE_INTERVAL	(3 * RB4XX_KEYS_POLL_INTERVAL)
46
47static struct gpio_led rb4xx_leds_gpio[] __initdata = {
48	{
49		.name		= "rb4xx:yellow:user",
50		.gpio		= RB4XX_GPIO_USER_LED,
51		.active_low	= 0,
52	}, {
53		.name		= "rb4xx:green:led1",
54		.gpio		= RB4XX_GPIO_CPLD_LED1,
55		.active_low	= 1,
56	}, {
57		.name		= "rb4xx:green:led2",
58		.gpio		= RB4XX_GPIO_CPLD_LED2,
59		.active_low	= 1,
60	}, {
61		.name		= "rb4xx:green:led3",
62		.gpio		= RB4XX_GPIO_CPLD_LED3,
63		.active_low	= 1,
64	}, {
65		.name		= "rb4xx:green:led4",
66		.gpio		= RB4XX_GPIO_CPLD_LED4,
67		.active_low	= 1,
68	}, {
69		.name		= "rb4xx:green:led5",
70		.gpio		= RB4XX_GPIO_CPLD_LED5,
71		.active_low	= 0,
72	},
73};
74
75static struct gpio_keys_button rb4xx_gpio_keys[] __initdata = {
76	{
77		.desc		= "reset_switch",
78		.type		= EV_KEY,
79		.code		= KEY_RESTART,
80		.debounce_interval = RB4XX_KEYS_DEBOUNCE_INTERVAL,
81		.gpio		= RB4XX_GPIO_RESET_SWITCH,
82		.active_low	= 1,
83	}
84};
85
86static struct platform_device rb4xx_nand_device = {
87	.name	= "rb4xx-nand",
88	.id	= -1,
89};
90
91static struct ath79_pci_irq rb4xx_pci_irqs[] __initdata = {
92	{
93		.slot	= 17,
94		.pin	= 1,
95		.irq	= ATH79_PCI_IRQ(2),
96	}, {
97		.slot	= 18,
98		.pin	= 1,
99		.irq	= ATH79_PCI_IRQ(0),
100	}, {
101		.slot	= 18,
102		.pin	= 2,
103		.irq	= ATH79_PCI_IRQ(1),
104	}, {
105		.slot	= 19,
106		.pin	= 1,
107		.irq	= ATH79_PCI_IRQ(1),
108	}, {
109		.slot	= 19,
110		.pin	= 2,
111		.irq	= ATH79_PCI_IRQ(2),
112	}, {
113		.slot	= 20,
114		.pin	= 1,
115		.irq	= ATH79_PCI_IRQ(2),
116	}, {
117		.slot	= 20,
118		.pin	= 2,
119		.irq	= ATH79_PCI_IRQ(0),
120	}, {
121		.slot	= 21,
122		.pin	= 1,
123		.irq	= ATH79_PCI_IRQ(0),
124	}, {
125		.slot	= 22,
126		.pin	= 1,
127		.irq	= ATH79_PCI_IRQ(1),
128	}, {
129		.slot	= 22,
130		.pin	= 2,
131		.irq	= ATH79_PCI_IRQ(2),
132	}, {
133		.slot	= 23,
134		.pin	= 1,
135		.irq	= ATH79_PCI_IRQ(2),
136	}, {
137		.slot	= 23,
138		.pin	= 2,
139		.irq	= ATH79_PCI_IRQ(0),
140	}
141};
142
143static struct mtd_partition rb4xx_partitions[] = {
144	{
145		.name		= "routerboot",
146		.offset		= 0,
147		.size		= 0x0b000,
148		.mask_flags	= MTD_WRITEABLE,
149	}, {
150		.name		= "hard_config",
151		.offset		= 0x0b000,
152		.size		= 0x01000,
153		.mask_flags	= MTD_WRITEABLE,
154	}, {
155		.name		= "bios",
156		.offset		= 0x0d000,
157		.size		= 0x02000,
158		.mask_flags	= MTD_WRITEABLE,
159	}, {
160		.name		= "soft_config",
161		.offset		= 0x0f000,
162		.size		= 0x01000,
163	}
164};
165
166static struct flash_platform_data rb4xx_flash_data = {
167	.type		= "pm25lv512",
168	.parts		= rb4xx_partitions,
169	.nr_parts	= ARRAY_SIZE(rb4xx_partitions),
170};
171
172static struct rb4xx_cpld_platform_data rb4xx_cpld_data = {
173	.gpio_base	= RB4XX_GPIO_CPLD_BASE,
174};
175
176static struct mmc_spi_platform_data rb4xx_mmc_data = {
177	.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34,
178};
179
180static struct spi_board_info rb4xx_spi_info[] = {
181	{
182		.bus_num	= 0,
183		.chip_select	= 0,
184		.max_speed_hz	= 25000000,
185		.modalias	= "m25p80",
186		.platform_data	= &rb4xx_flash_data,
187	}, {
188		.bus_num	= 0,
189		.chip_select	= 1,
190		.max_speed_hz	= 25000000,
191		.modalias	= "spi-rb4xx-cpld",
192		.platform_data	= &rb4xx_cpld_data,
193	}
194};
195
196static struct spi_board_info rb4xx_microsd_info[] = {
197	{
198		.bus_num	= 0,
199		.chip_select	= 2,
200		.max_speed_hz	= 25000000,
201		.modalias	= "mmc_spi",
202		.platform_data	= &rb4xx_mmc_data,
203	}
204};
205
206
207static struct resource rb4xx_spi_resources[] = {
208	{
209		.start	= AR71XX_SPI_BASE,
210		.end	= AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
211		.flags	= IORESOURCE_MEM,
212	},
213};
214
215static struct platform_device rb4xx_spi_device = {
216	.name		= "rb4xx-spi",
217	.id		= -1,
218	.resource	= rb4xx_spi_resources,
219	.num_resources	= ARRAY_SIZE(rb4xx_spi_resources),
220};
221
222static void __init rb4xx_generic_setup(void)
223{
224	ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
225				   AR71XX_GPIO_FUNC_SPI_CS2_EN);
226
227	ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
228					rb4xx_leds_gpio);
229
230	ath79_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL,
231					ARRAY_SIZE(rb4xx_gpio_keys),
232					rb4xx_gpio_keys);
233
234	spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
235	platform_device_register(&rb4xx_spi_device);
236	platform_device_register(&rb4xx_nand_device);
237}
238
239static void __init rb411_setup(void)
240{
241	rb4xx_generic_setup();
242	spi_register_board_info(rb4xx_microsd_info,
243				ARRAY_SIZE(rb4xx_microsd_info));
244
245	ath79_register_mdio(0, 0xfffffffc);
246
247	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
248	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
249	ath79_eth0_data.phy_mask = 0x00000003;
250
251	ath79_register_eth(0);
252
253	ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
254	ath79_register_pci();
255}
256
257MIPS_MACHINE(ATH79_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH",
258	     rb411_setup);
259
260static void __init rb411u_setup(void)
261{
262	rb411_setup();
263	ath79_register_usb();
264}
265
266MIPS_MACHINE(ATH79_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U",
267	     rb411u_setup);
268
269#define RB433_LAN_PHYMASK	BIT(0)
270#define RB433_WAN_PHYMASK	BIT(4)
271#define RB433_MDIO_PHYMASK	(RB433_LAN_PHYMASK | RB433_WAN_PHYMASK)
272
273static void __init rb433_setup(void)
274{
275	rb4xx_generic_setup();
276	spi_register_board_info(rb4xx_microsd_info,
277				ARRAY_SIZE(rb4xx_microsd_info));
278
279	ath79_register_mdio(0, ~RB433_MDIO_PHYMASK);
280
281	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
282	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
283	ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK;
284
285	ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
286	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
287	ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK;
288
289	ath79_register_eth(1);
290	ath79_register_eth(0);
291
292	ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
293	ath79_register_pci();
294}
295
296MIPS_MACHINE(ATH79_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH",
297	     rb433_setup);
298
299static void __init rb433u_setup(void)
300{
301	rb433_setup();
302	ath79_register_usb();
303}
304
305MIPS_MACHINE(ATH79_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH",
306	     rb433u_setup);
307
308static void __init rb435g_setup(void)
309{
310	rb4xx_generic_setup();
311
312	spi_register_board_info(rb4xx_microsd_info,
313				ARRAY_SIZE(rb4xx_microsd_info));
314
315	ath79_register_mdio(0, ~RB433_MDIO_PHYMASK);
316
317	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
318	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
319	ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK;
320
321	ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
322	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
323	ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK;
324
325	ath79_register_eth(1);
326	ath79_register_eth(0);
327
328	ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
329	ath79_register_pci();
330
331	ath79_register_usb();
332}
333
334MIPS_MACHINE(ATH79_MACH_RB_435G, "435G", "MikroTik RouterBOARD 435G",
335	     rb435g_setup);
336
337#define RB450_LAN_PHYMASK	BIT(0)
338#define RB450_WAN_PHYMASK	BIT(4)
339#define RB450_MDIO_PHYMASK	(RB450_LAN_PHYMASK | RB450_WAN_PHYMASK)
340
341static void __init rb450_generic_setup(int gige)
342{
343	rb4xx_generic_setup();
344	ath79_register_mdio(0, ~RB450_MDIO_PHYMASK);
345
346	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
347	ath79_eth0_data.phy_if_mode = (gige) ?
348		PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII;
349	ath79_eth0_data.phy_mask = RB450_LAN_PHYMASK;
350
351	ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
352	ath79_eth1_data.phy_if_mode = (gige) ?
353		PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII;
354	ath79_eth1_data.phy_mask = RB450_WAN_PHYMASK;
355
356	ath79_register_eth(1);
357	ath79_register_eth(0);
358}
359
360static void __init rb450_setup(void)
361{
362	rb450_generic_setup(0);
363}
364
365MIPS_MACHINE(ATH79_MACH_RB_450, "450", "MikroTik RouterBOARD 450",
366	     rb450_setup);
367
368static void __init rb450g_setup(void)
369{
370	rb450_generic_setup(1);
371	spi_register_board_info(rb4xx_microsd_info,
372				ARRAY_SIZE(rb4xx_microsd_info));
373}
374
375MIPS_MACHINE(ATH79_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G",
376	     rb450g_setup);
377
378static void __init rb493_setup(void)
379{
380	rb4xx_generic_setup();
381
382	ath79_register_mdio(0, 0x3fffff00);
383
384	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
385	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
386	ath79_eth0_data.speed = SPEED_100;
387	ath79_eth0_data.duplex = DUPLEX_FULL;
388
389	ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
390	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
391	ath79_eth1_data.phy_mask = 0x00000001;
392
393	ath79_register_eth(0);
394	ath79_register_eth(1);
395
396	ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
397	ath79_register_pci();
398}
399
400MIPS_MACHINE(ATH79_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH",
401	     rb493_setup);
402
403#define RB493G_GPIO_MDIO_MDC		7
404#define RB493G_GPIO_MDIO_DATA		8
405
406#define RB493G_MDIO_PHYMASK		BIT(0)
407
408static struct mdio_gpio_platform_data rb493g_mdio_data = {
409	.mdc		= RB493G_GPIO_MDIO_MDC,
410	.mdio		= RB493G_GPIO_MDIO_DATA,
411
412	.phy_mask	= ~RB493G_MDIO_PHYMASK,
413};
414
415static struct platform_device rb493g_mdio_device = {
416	.name 		= "mdio-gpio",
417	.id 		= -1,
418	.dev 		= {
419		.platform_data	= &rb493g_mdio_data,
420	},
421};
422
423static void __init rb493g_setup(void)
424{
425	ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
426				    AR71XX_GPIO_FUNC_SPI_CS2_EN);
427
428	ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
429				    rb4xx_leds_gpio);
430
431	spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
432	spi_register_board_info(rb4xx_microsd_info,
433				ARRAY_SIZE(rb4xx_microsd_info));
434
435	platform_device_register(&rb4xx_spi_device);
436	platform_device_register(&rb4xx_nand_device);
437
438	ath79_register_mdio(0, ~RB493G_MDIO_PHYMASK);
439
440	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
441	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
442	ath79_eth0_data.phy_mask = RB493G_MDIO_PHYMASK;
443	ath79_eth0_data.speed = SPEED_1000;
444	ath79_eth0_data.duplex = DUPLEX_FULL;
445
446	ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
447	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
448	ath79_eth1_data.mii_bus_dev = &rb493g_mdio_device.dev;
449	ath79_eth1_data.phy_mask = RB493G_MDIO_PHYMASK;
450	ath79_eth1_data.speed = SPEED_1000;
451	ath79_eth1_data.duplex = DUPLEX_FULL;
452
453	platform_device_register(&rb493g_mdio_device);
454
455	ath79_register_eth(1);
456	ath79_register_eth(0);
457
458	ath79_register_usb();
459
460	ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
461	ath79_register_pci();
462}
463
464MIPS_MACHINE(ATH79_MACH_RB_493G, "493G", "MikroTik RouterBOARD 493G",
465	     rb493g_setup);
466