1/* 2 * ADM5120 HCD (Host Controller Driver) for USB 3 * 4 * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org> 5 * 6 * This file was derived from: drivers/usb/host/ohci-hcd.c 7 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 8 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> 9 * 10 * [ Initialisation is based on Linus' ] 11 * [ uhci code and gregs ahcd fragments ] 12 * [ (C) Copyright 1999 Linus Torvalds ] 13 * [ (C) Copyright 1999 Gregory P. Smith] 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License version 2 as published 17 * by the Free Software Foundation. 18 * 19 */ 20 21#include <linux/module.h> 22#include <linux/moduleparam.h> 23#include <linux/pci.h> 24#include <linux/kernel.h> 25#include <linux/delay.h> 26#include <linux/ioport.h> 27#include <linux/sched.h> 28#include <linux/slab.h> 29#include <linux/errno.h> 30#include <linux/init.h> 31#include <linux/timer.h> 32#include <linux/list.h> 33#include <linux/usb.h> 34#include <linux/usb/otg.h> 35#include <linux/usb/hcd.h> 36#include <linux/dma-mapping.h> 37#include <linux/dmapool.h> 38#include <linux/debugfs.h> 39#include <linux/io.h> 40 41#include <asm/irq.h> 42#include <asm/system.h> 43#include <asm/unaligned.h> 44#include <asm/byteorder.h> 45 46#define DRIVER_VERSION "0.27.0" 47#define DRIVER_AUTHOR "Gabor Juhos <juhosg@openwrt.org>" 48#define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver" 49 50/*-------------------------------------------------------------------------*/ 51 52#undef ADMHC_VERBOSE_DEBUG /* not always helpful */ 53 54/* For initializing controller (mask in an HCFS mode too) */ 55#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR 56 57#define ADMHC_INTR_INIT \ 58 (ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \ 59 | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI) 60 61/*-------------------------------------------------------------------------*/ 62 63static const char hcd_name[] = "admhc-hcd"; 64 65#define STATECHANGE_DELAY msecs_to_jiffies(300) 66 67#include "adm5120.h" 68 69static void admhc_dump(struct admhcd *ahcd, int verbose); 70static int admhc_init(struct admhcd *ahcd); 71static void admhc_stop(struct usb_hcd *hcd); 72 73#include "adm5120-dbg.c" 74#include "adm5120-mem.c" 75#include "adm5120-pm.c" 76#include "adm5120-hub.c" 77#include "adm5120-q.c" 78 79/*-------------------------------------------------------------------------*/ 80 81/* 82 * queue up an urb for anything except the root hub 83 */ 84static int admhc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 85 gfp_t mem_flags) 86{ 87 struct admhcd *ahcd = hcd_to_admhcd(hcd); 88 struct ed *ed; 89 struct urb_priv *urb_priv; 90 unsigned int pipe = urb->pipe; 91 int td_cnt = 0; 92 unsigned long flags; 93 int ret = 0; 94 95#ifdef ADMHC_VERBOSE_DEBUG 96 spin_lock_irqsave(&ahcd->lock, flags); 97 urb_print(ahcd, urb, "ENQEUE", usb_pipein(pipe), -EINPROGRESS); 98 spin_unlock_irqrestore(&ahcd->lock, flags); 99#endif 100 101 /* every endpoint has an ed, locate and maybe (re)initialize it */ 102 ed = ed_get(ahcd, urb->ep, urb->dev, pipe, urb->interval); 103 if (!ed) 104 return -ENOMEM; 105 106 /* for the private part of the URB we need the number of TDs */ 107 switch (ed->type) { 108 case PIPE_CONTROL: 109 if (urb->transfer_buffer_length > TD_DATALEN_MAX) 110 /* td_submit_urb() doesn't yet handle these */ 111 return -EMSGSIZE; 112 113 /* 1 TD for setup, 1 for ACK, plus ... */ 114 td_cnt = 2; 115 /* FALLTHROUGH */ 116 case PIPE_BULK: 117 /* one TD for every 4096 Bytes (can be up to 8K) */ 118 td_cnt += urb->transfer_buffer_length / TD_DATALEN_MAX; 119 /* ... and for any remaining bytes ... */ 120 if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0) 121 td_cnt++; 122 /* ... and maybe a zero length packet to wrap it up */ 123 if (td_cnt == 0) 124 td_cnt++; 125 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 126 && (urb->transfer_buffer_length 127 % usb_maxpacket(urb->dev, pipe, 128 usb_pipeout(pipe))) == 0) 129 td_cnt++; 130 break; 131 case PIPE_INTERRUPT: 132 /* 133 * for Interrupt IN/OUT transactions, each ED contains 134 * only 1 TD. 135 * TODO: check transfer_buffer_length? 136 */ 137 td_cnt = 1; 138 break; 139 case PIPE_ISOCHRONOUS: 140 /* number of packets from URB */ 141 td_cnt = urb->number_of_packets; 142 break; 143 } 144 145 urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags); 146 if (!urb_priv) 147 return -ENOMEM; 148 149 urb_priv->ed = ed; 150 151 spin_lock_irqsave(&ahcd->lock, flags); 152 /* don't submit to a dead HC */ 153 if (!HCD_HW_ACCESSIBLE(hcd)) { 154 ret = -ENODEV; 155 goto fail; 156 } 157 if (!HC_IS_RUNNING(hcd->state)) { 158 ret = -ENODEV; 159 goto fail; 160 } 161 162 ret = usb_hcd_link_urb_to_ep(hcd, urb); 163 if (ret) 164 goto fail; 165 166 /* schedule the ed if needed */ 167 if (ed->state == ED_IDLE) { 168 ret = ed_schedule(ahcd, ed); 169 if (ret < 0) { 170 usb_hcd_unlink_urb_from_ep(hcd, urb); 171 goto fail; 172 } 173 if (ed->type == PIPE_ISOCHRONOUS) { 174 u16 frame = admhc_frame_no(ahcd); 175 176 /* delay a few frames before the first TD */ 177 frame += max_t (u16, 8, ed->interval); 178 frame &= ~(ed->interval - 1); 179 frame |= ed->branch; 180 urb->start_frame = frame; 181 182 /* yes, only URB_ISO_ASAP is supported, and 183 * urb->start_frame is never used as input. 184 */ 185 } 186 } else if (ed->type == PIPE_ISOCHRONOUS) 187 urb->start_frame = ed->last_iso + ed->interval; 188 189 /* fill the TDs and link them to the ed; and 190 * enable that part of the schedule, if needed 191 * and update count of queued periodic urbs 192 */ 193 urb->hcpriv = urb_priv; 194 td_submit_urb(ahcd, urb); 195 196#ifdef ADMHC_VERBOSE_DEBUG 197 admhc_dump_ed(ahcd, "admhc_urb_enqueue", urb_priv->ed, 1); 198#endif 199 200fail: 201 if (ret) 202 urb_priv_free(ahcd, urb_priv); 203 204 spin_unlock_irqrestore(&ahcd->lock, flags); 205 return ret; 206} 207 208/* 209 * decouple the URB from the HC queues (TDs, urb_priv); 210 * reporting is always done 211 * asynchronously, and we might be dealing with an urb that's 212 * partially transferred, or an ED with other urbs being unlinked. 213 */ 214static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 215 int status) 216{ 217 struct admhcd *ahcd = hcd_to_admhcd(hcd); 218 unsigned long flags; 219 int ret; 220 221 spin_lock_irqsave(&ahcd->lock, flags); 222 223#ifdef ADMHC_VERBOSE_DEBUG 224 urb_print(ahcd, urb, "DEQUEUE", 1, status); 225#endif 226 ret = usb_hcd_check_unlink_urb(hcd, urb, status); 227 if (ret) { 228 /* Do nothing */ 229 ; 230 } else if (HC_IS_RUNNING(hcd->state)) { 231 struct urb_priv *urb_priv; 232 233 /* Unless an IRQ completed the unlink while it was being 234 * handed to us, flag it for unlink and giveback, and force 235 * some upcoming INTR_SF to call finish_unlinks() 236 */ 237 urb_priv = urb->hcpriv; 238 if (urb_priv) { 239 if (urb_priv->ed->state == ED_OPER) 240 start_ed_unlink(ahcd, urb_priv->ed); 241 } 242 } else { 243 /* 244 * with HC dead, we won't respect hc queue pointers 245 * any more ... just clean up every urb's memory. 246 */ 247 if (urb->hcpriv) 248 finish_urb(ahcd, urb, status); 249 } 250 spin_unlock_irqrestore(&ahcd->lock, flags); 251 252 return ret; 253} 254 255/*-------------------------------------------------------------------------*/ 256 257/* frees config/altsetting state for endpoints, 258 * including ED memory, dummy TD, and bulk/intr data toggle 259 */ 260 261static void admhc_endpoint_disable(struct usb_hcd *hcd, 262 struct usb_host_endpoint *ep) 263{ 264 struct admhcd *ahcd = hcd_to_admhcd(hcd); 265 unsigned long flags; 266 struct ed *ed = ep->hcpriv; 267 unsigned limit = 1000; 268 269 /* ASSERT: any requests/urbs are being unlinked */ 270 /* ASSERT: nobody can be submitting urbs for this any more */ 271 272 if (!ed) 273 return; 274 275#ifdef ADMHC_VERBOSE_DEBUG 276 spin_lock_irqsave(&ahcd->lock, flags); 277 admhc_dump_ed(ahcd, "EP-DISABLE", ed, 1); 278 spin_unlock_irqrestore(&ahcd->lock, flags); 279#endif 280 281rescan: 282 spin_lock_irqsave(&ahcd->lock, flags); 283 284 if (!HC_IS_RUNNING(hcd->state)) { 285sanitize: 286 ed->state = ED_IDLE; 287 finish_unlinks(ahcd, 0); 288 } 289 290 switch (ed->state) { 291 case ED_UNLINK: /* wait for hw to finish? */ 292 /* major IRQ delivery trouble loses INTR_SOFI too... */ 293 if (limit-- == 0) { 294 admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n"); 295 goto sanitize; 296 } 297 spin_unlock_irqrestore(&ahcd->lock, flags); 298 schedule_timeout_uninterruptible(1); 299 goto rescan; 300 case ED_IDLE: /* fully unlinked */ 301 if (list_empty(&ed->td_list)) { 302 td_free(ahcd, ed->dummy); 303 ed_free(ahcd, ed); 304 break; 305 } 306 /* else FALL THROUGH */ 307 default: 308 /* caller was supposed to have unlinked any requests; 309 * that's not our job. can't recover; must leak ed. 310 */ 311 admhc_err(ahcd, "leak ed %p (#%02x) state %d%s\n", 312 ed, ep->desc.bEndpointAddress, ed->state, 313 list_empty(&ed->td_list) ? "" : " (has tds)"); 314 td_free(ahcd, ed->dummy); 315 break; 316 } 317 318 ep->hcpriv = NULL; 319 320 spin_unlock_irqrestore(&ahcd->lock, flags); 321} 322 323static int admhc_get_frame_number(struct usb_hcd *hcd) 324{ 325 struct admhcd *ahcd = hcd_to_admhcd(hcd); 326 327 return admhc_frame_no(ahcd); 328} 329 330static void admhc_usb_reset(struct admhcd *ahcd) 331{ 332#if 0 333 ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control); 334 ahcd->hc_control &= OHCI_CTRL_RWC; 335 admhc_writel(ahcd, ahcd->hc_control, &ahcd->regs->control); 336#else 337 /* FIXME */ 338 ahcd->host_control = ADMHC_BUSS_RESET; 339 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control); 340#endif 341} 342 343/* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and 344 * other cases where the next software may expect clean state from the 345 * "firmware". this is bus-neutral, unlike shutdown() methods. 346 */ 347static void 348admhc_shutdown(struct usb_hcd *hcd) 349{ 350 struct admhcd *ahcd; 351 352 ahcd = hcd_to_admhcd(hcd); 353 admhc_intr_disable(ahcd, ADMHC_INTR_MIE); 354 admhc_dma_disable(ahcd); 355 admhc_usb_reset(ahcd); 356 /* flush the writes */ 357 admhc_writel_flush(ahcd); 358} 359 360/*-------------------------------------------------------------------------* 361 * HC functions 362 *-------------------------------------------------------------------------*/ 363 364static void admhc_eds_cleanup(struct admhcd *ahcd) 365{ 366 if (ahcd->ed_tails[PIPE_INTERRUPT]) { 367 ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]); 368 ahcd->ed_tails[PIPE_INTERRUPT] = NULL; 369 } 370 371 if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) { 372 ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]); 373 ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL; 374 } 375 376 if (ahcd->ed_tails[PIPE_CONTROL]) { 377 ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]); 378 ahcd->ed_tails[PIPE_CONTROL] = NULL; 379 } 380 381 if (ahcd->ed_tails[PIPE_BULK]) { 382 ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]); 383 ahcd->ed_tails[PIPE_BULK] = NULL; 384 } 385 386 ahcd->ed_head = NULL; 387} 388 389#define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP) 390 391static int admhc_eds_init(struct admhcd *ahcd) 392{ 393 struct ed *ed; 394 395 ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO); 396 if (!ed) 397 goto err; 398 399 ahcd->ed_tails[PIPE_INTERRUPT] = ed; 400 401 ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO); 402 if (!ed) 403 goto err; 404 405 ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed; 406 ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT]; 407 ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed; 408 ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma); 409 410 ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO); 411 if (!ed) 412 goto err; 413 414 ahcd->ed_tails[PIPE_CONTROL] = ed; 415 ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS]; 416 ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed; 417 ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma); 418 419 ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO); 420 if (!ed) 421 goto err; 422 423 ahcd->ed_tails[PIPE_BULK] = ed; 424 ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL]; 425 ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed; 426 ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma); 427 428 ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT]; 429 430#ifdef ADMHC_VERBOSE_DEBUG 431 admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1); 432 admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1); 433 admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1); 434 admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1); 435#endif 436 437 return 0; 438 439err: 440 admhc_eds_cleanup(ahcd); 441 return -ENOMEM; 442} 443 444/* init memory, and kick BIOS/SMM off */ 445 446static int admhc_init(struct admhcd *ahcd) 447{ 448 struct usb_hcd *hcd = admhcd_to_hcd(ahcd); 449 int ret; 450 451 admhc_disable(ahcd); 452 ahcd->regs = hcd->regs; 453 454 /* Disable HC interrupts */ 455 admhc_intr_disable(ahcd, ADMHC_INTR_MIE); 456 457 /* Read the number of ports unless overridden */ 458 if (ahcd->num_ports == 0) 459 ahcd->num_ports = admhc_read_rhdesc(ahcd) & ADMHC_RH_NUMP; 460 461 ret = admhc_mem_init(ahcd); 462 if (ret) 463 goto err; 464 465 /* init dummy endpoints */ 466 ret = admhc_eds_init(ahcd); 467 if (ret) 468 goto err; 469 470 create_debug_files(ahcd); 471 472 return 0; 473 474err: 475 admhc_stop(hcd); 476 return ret; 477} 478 479/*-------------------------------------------------------------------------*/ 480 481/* Start an OHCI controller, set the BUS operational 482 * resets USB and controller 483 * enable interrupts 484 */ 485static int admhc_run(struct admhcd *ahcd) 486{ 487 u32 val; 488 int first = ahcd->fminterval == 0; 489 struct usb_hcd *hcd = admhcd_to_hcd(ahcd); 490 491 admhc_disable(ahcd); 492 493 /* boot firmware should have set this up (5.1.1.3.1) */ 494 if (first) { 495 val = admhc_readl(ahcd, &ahcd->regs->fminterval); 496 ahcd->fminterval = val & ADMHC_SFI_FI_MASK; 497 if (ahcd->fminterval != FI) 498 admhc_dbg(ahcd, "fminterval delta %d\n", 499 ahcd->fminterval - FI); 500 ahcd->fminterval |= 501 (FSLDP(ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT); 502 /* also: power/overcurrent flags in rhdesc */ 503 } 504 505#if 0 /* TODO: not applicable */ 506 /* Reset USB nearly "by the book". RemoteWakeupConnected has 507 * to be checked in case boot firmware (BIOS/SMM/...) has set up 508 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM). 509 * If the bus glue detected wakeup capability then it should 510 * already be enabled; if so we'll just enable it again. 511 */ 512 if ((ahcd->hc_control & OHCI_CTRL_RWC) != 0) 513 device_set_wakeup_capable(hcd->self.controller, 1); 514#endif 515 516 switch (ahcd->host_control & ADMHC_HC_BUSS) { 517 case ADMHC_BUSS_OPER: 518 val = 0; 519 break; 520 case ADMHC_BUSS_SUSPEND: 521 /* FALLTHROUGH ? */ 522 case ADMHC_BUSS_RESUME: 523 ahcd->host_control = ADMHC_BUSS_RESUME; 524 val = 10 /* msec wait */; 525 break; 526 /* case ADMHC_BUSS_RESET: */ 527 default: 528 ahcd->host_control = ADMHC_BUSS_RESET; 529 val = 50 /* msec wait */; 530 break; 531 } 532 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control); 533 534 /* flush the writes */ 535 admhc_writel_flush(ahcd); 536 537 msleep(val); 538 val = admhc_read_rhdesc(ahcd); 539 if (!(val & ADMHC_RH_NPS)) { 540 /* power down each port */ 541 for (val = 0; val < ahcd->num_ports; val++) 542 admhc_write_portstatus(ahcd, val, ADMHC_PS_CPP); 543 } 544 /* flush those writes */ 545 admhc_writel_flush(ahcd); 546 547 /* 2msec timelimit here means no irqs/preempt */ 548 spin_lock_irq(&ahcd->lock); 549 550 admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol); 551 val = 30; /* ... allow extra time */ 552 while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) { 553 if (--val == 0) { 554 spin_unlock_irq(&ahcd->lock); 555 admhc_err(ahcd, "USB HC reset timed out!\n"); 556 return -1; 557 } 558 udelay(1); 559 } 560 561 /* enable HOST mode, before access any host specific register */ 562 admhc_writel(ahcd, ADMHC_CTRL_UHFE, &ahcd->regs->gencontrol); 563 564 /* Tell the controller where the descriptor list is */ 565 admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead); 566 567 periodic_reinit(ahcd); 568 569 /* use rhsc irqs after khubd is fully initialized */ 570 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 571 hcd->uses_new_polling = 1; 572 573#if 0 574 /* wake on ConnectStatusChange, matching external hubs */ 575 admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status); 576#else 577 /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */ 578#endif 579 580 /* Choose the interrupts we care about now, others later on demand */ 581 admhc_intr_ack(ahcd, ~0); 582 admhc_intr_enable(ahcd, ADMHC_INTR_INIT); 583 584 admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc); 585 586 /* flush those writes */ 587 admhc_writel_flush(ahcd); 588 589 /* start controller operations */ 590 ahcd->host_control = ADMHC_BUSS_OPER; 591 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control); 592 593 val = 20; 594 while ((admhc_readl(ahcd, &ahcd->regs->host_control) 595 & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) { 596 if (--val == 0) { 597 spin_unlock_irq(&ahcd->lock); 598 admhc_err(ahcd, "unable to setup operational mode!\n"); 599 return -1; 600 } 601 mdelay(1); 602 } 603 604 hcd->state = HC_STATE_RUNNING; 605 606 ahcd->next_statechange = jiffies + STATECHANGE_DELAY; 607 608#if 0 609 /* FIXME: enabling DMA is always failed here for an unknown reason */ 610 admhc_dma_enable(ahcd); 611 612 val = 200; 613 while ((admhc_readl(ahcd, &ahcd->regs->host_control) 614 & ADMHC_HC_DMAE) != ADMHC_HC_DMAE) { 615 if (--val == 0) { 616 spin_unlock_irq(&ahcd->lock); 617 admhc_err(ahcd, "unable to enable DMA!\n"); 618 admhc_dump(ahcd, 1); 619 return -1; 620 } 621 mdelay(1); 622 } 623 624#endif 625 626 spin_unlock_irq(&ahcd->lock); 627 628 mdelay(ADMHC_POTPGT); 629 630 return 0; 631} 632 633/*-------------------------------------------------------------------------*/ 634 635/* an interrupt happens */ 636 637static irqreturn_t admhc_irq(struct usb_hcd *hcd) 638{ 639 struct admhcd *ahcd = hcd_to_admhcd(hcd); 640 struct admhcd_regs __iomem *regs = ahcd->regs; 641 u32 ints; 642 643 ints = admhc_readl(ahcd, ®s->int_status); 644 if ((ints & ADMHC_INTR_INTA) == 0) { 645 /* no unmasked interrupt status is set */ 646 return IRQ_NONE; 647 } 648 649 ints &= admhc_readl(ahcd, ®s->int_enable); 650 651 if (ints & ADMHC_INTR_FATI) { 652 /* e.g. due to PCI Master/Target Abort */ 653 admhc_disable(ahcd); 654 admhc_err(ahcd, "Fatal Error, controller disabled\n"); 655 admhc_dump(ahcd, 1); 656 admhc_usb_reset(ahcd); 657 } 658 659 if (ints & ADMHC_INTR_BABI) { 660 admhc_intr_disable(ahcd, ADMHC_INTR_BABI); 661 admhc_intr_ack(ahcd, ADMHC_INTR_BABI); 662 admhc_err(ahcd, "Babble Detected\n"); 663 } 664 665 if (ints & ADMHC_INTR_INSM) { 666 admhc_vdbg(ahcd, "Root Hub Status Change\n"); 667 ahcd->next_statechange = jiffies + STATECHANGE_DELAY; 668 admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM); 669 670 /* NOTE: Vendors didn't always make the same implementation 671 * choices for RHSC. Many followed the spec; RHSC triggers 672 * on an edge, like setting and maybe clearing a port status 673 * change bit. With others it's level-triggered, active 674 * until khubd clears all the port status change bits. We'll 675 * always disable it here and rely on polling until khubd 676 * re-enables it. 677 */ 678 admhc_intr_disable(ahcd, ADMHC_INTR_INSM); 679 usb_hcd_poll_rh_status(hcd); 680 } else if (ints & ADMHC_INTR_RESI) { 681 /* For connect and disconnect events, we expect the controller 682 * to turn on RHSC along with RD. But for remote wakeup events 683 * this might not happen. 684 */ 685 admhc_vdbg(ahcd, "Resume Detect\n"); 686 admhc_intr_ack(ahcd, ADMHC_INTR_RESI); 687 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 688 if (ahcd->autostop) { 689 spin_lock(&ahcd->lock); 690 admhc_rh_resume(ahcd); 691 spin_unlock(&ahcd->lock); 692 } else 693 usb_hcd_resume_root_hub(hcd); 694 } 695 696 if (ints & ADMHC_INTR_TDC) { 697 admhc_vdbg(ahcd, "Transfer Descriptor Complete\n"); 698 admhc_intr_ack(ahcd, ADMHC_INTR_TDC); 699 if (HC_IS_RUNNING(hcd->state)) 700 admhc_intr_disable(ahcd, ADMHC_INTR_TDC); 701 spin_lock(&ahcd->lock); 702 admhc_td_complete(ahcd); 703 spin_unlock(&ahcd->lock); 704 if (HC_IS_RUNNING(hcd->state)) 705 admhc_intr_enable(ahcd, ADMHC_INTR_TDC); 706 } 707 708 if (ints & ADMHC_INTR_SO) { 709 /* could track INTR_SO to reduce available PCI/... bandwidth */ 710 admhc_vdbg(ahcd, "Schedule Overrun\n"); 711 } 712 713#if 1 714 spin_lock(&ahcd->lock); 715 if (ahcd->ed_rm_list) 716 finish_unlinks(ahcd, admhc_frame_no(ahcd)); 717 718 if ((ints & ADMHC_INTR_SOFI) != 0 && !ahcd->ed_rm_list 719 && HC_IS_RUNNING(hcd->state)) 720 admhc_intr_disable(ahcd, ADMHC_INTR_SOFI); 721 spin_unlock(&ahcd->lock); 722#else 723 if (ints & ADMHC_INTR_SOFI) { 724 admhc_vdbg(ahcd, "Start Of Frame\n"); 725 spin_lock(&ahcd->lock); 726 727 /* handle any pending ED removes */ 728 finish_unlinks(ahcd, admhc_frameno(ahcd)); 729 730 /* leaving INTR_SOFI enabled when there's still unlinking 731 * to be done in the (next frame). 732 */ 733 if ((ahcd->ed_rm_list == NULL) || 734 HC_IS_RUNNING(hcd->state) == 0) 735 /* 736 * disable INTR_SOFI if there are no unlinking to be 737 * done (in the next frame) 738 */ 739 admhc_intr_disable(ahcd, ADMHC_INTR_SOFI); 740 741 spin_unlock(&ahcd->lock); 742 } 743#endif 744 745 if (HC_IS_RUNNING(hcd->state)) { 746 admhc_intr_ack(ahcd, ints); 747 admhc_intr_enable(ahcd, ADMHC_INTR_MIE); 748 admhc_writel_flush(ahcd); 749 } 750 751 return IRQ_HANDLED; 752} 753 754/*-------------------------------------------------------------------------*/ 755 756static void admhc_stop(struct usb_hcd *hcd) 757{ 758 struct admhcd *ahcd = hcd_to_admhcd(hcd); 759 760 admhc_dump(ahcd, 1); 761 762 flush_scheduled_work(); 763 764 admhc_usb_reset(ahcd); 765 admhc_intr_disable(ahcd, ADMHC_INTR_MIE); 766 767 free_irq(hcd->irq, hcd); 768 hcd->irq = -1; 769 770 remove_debug_files(ahcd); 771 admhc_eds_cleanup(ahcd); 772 admhc_mem_cleanup(ahcd); 773} 774 775/*-------------------------------------------------------------------------*/ 776 777#ifdef CONFIG_ADM5120 778#include "adm5120-drv.c" 779#define PLATFORM_DRIVER usb_hcd_adm5120_driver 780#endif 781 782#if !defined(PLATFORM_DRIVER) 783#error "missing bus glue for admhc-hcd" 784#endif 785 786#define DRIVER_INFO DRIVER_DESC " version " DRIVER_VERSION 787 788static int __init admhc_hcd_mod_init(void) 789{ 790 int ret = 0; 791 792 if (usb_disabled()) 793 return -ENODEV; 794 795 pr_info("%s: " DRIVER_INFO "\n", hcd_name); 796 pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name, 797 sizeof(struct ed), sizeof(struct td)); 798 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 799 800#ifdef DEBUG 801 admhc_debug_root = debugfs_create_dir("admhc", usb_debug_root); 802 if (!admhc_debug_root) { 803 ret = -ENOENT; 804 goto error_debug; 805 } 806#endif 807 808#ifdef PLATFORM_DRIVER 809 ret = platform_driver_register(&PLATFORM_DRIVER); 810 if (ret < 0) 811 goto error_platform; 812#endif 813 814 return ret; 815 816#ifdef PLATFORM_DRIVER 817 platform_driver_unregister(&PLATFORM_DRIVER); 818error_platform: 819#endif 820 821#ifdef DEBUG 822 debugfs_remove(admhc_debug_root); 823 admhc_debug_root = NULL; 824error_debug: 825#endif 826 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 827 return ret; 828} 829module_init(admhc_hcd_mod_init); 830 831static void __exit admhc_hcd_mod_exit(void) 832{ 833 platform_driver_unregister(&PLATFORM_DRIVER); 834#ifdef DEBUG 835 debugfs_remove(admhc_debug_root); 836#endif 837 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 838} 839module_exit(admhc_hcd_mod_exit); 840 841MODULE_AUTHOR(DRIVER_AUTHOR); 842MODULE_DESCRIPTION(DRIVER_INFO); 843MODULE_VERSION(DRIVER_VERSION); 844MODULE_LICENSE("GPL v2"); 845