1/* 2 * ADM5120 ethernet switch definitions 3 * 4 * This header file defines the hardware registers of the ADM5120 SoC 5 * built-in Ethernet switch. 6 * 7 * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published 11 * by the Free Software Foundation. 12 * 13 */ 14 15#ifndef _MACH_ADM5120_SWITCH_H 16#define _MACH_ADM5120_SWITCH_H 17 18#ifndef BIT 19# define BIT(at) (1 << (at)) 20#endif 21#define BITMASK(len) (BIT(len)-1) 22 23#define SW_READ_REG(r) __raw_readl( \ 24 (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r) 25#define SW_WRITE_REG(r, v) __raw_writel((v), \ 26 (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r) 27 28/* Switch register offsets */ 29#define SWITCH_REG_CODE 0x0000 30#define SWITCH_REG_SOFT_RESET 0x0004 /* Soft Reset */ 31#define SWITCH_REG_BOOT_DONE 0x0008 /* Boot Done */ 32#define SWITCH_REG_SW_RESET 0x000C /* Switch Reset */ 33#define SWITCH_REG_PHY_STATUS 0x0014 /* PHY Status */ 34#define SWITCH_REG_MEMCTRL 0x001C /* Memory Control */ 35#define SWITCH_REG_CPUP_CONF 0x0024 /* CPU Port Configuration */ 36#define SWITCH_REG_PORT_CONF0 0x0028 /* Port Configuration 0 */ 37#define SWITCH_REG_PORT_CONF1 0x002C /* Port Configuration 1 */ 38#define SWITCH_REG_PORT_CONF2 0x0030 /* Port Configuration 2 */ 39#define SWITCH_REG_VLAN_G1 0x0040 /* VLAN group 1 */ 40#define SWITCH_REG_VLAN_G2 0x0044 /* VLAN group 2 */ 41#define SWITCH_REG_SEND_TRIG 0x0048 /* Send Trigger */ 42#define SWITCH_REG_MAC_WT0 0x0058 /* MAC Write Address 0 */ 43#define SWITCH_REG_MAC_WT1 0x005C /* MAC Write Address 1 */ 44#define SWITCH_REG_BW_CNTL0 0x0060 /* Bandwidth Control 0 */ 45#define SWITCH_REG_BW_CNTL1 0x0064 /* Bandwidth Control 1 */ 46#define SWITCH_REG_PHY_CNTL0 0x0068 /* PHY Control 0 */ 47#define SWITCH_REG_PHY_CNTL1 0x006C /* PHY Control 1 */ 48#define SWITCH_REG_PORT_TH 0x0078 /* Port Threshold */ 49#define SWITCH_REG_PHY_CNTL2 0x007C /* PHY Control 2 */ 50#define SWITCH_REG_PHY_CNTL3 0x0080 /* PHY Control 3 */ 51#define SWITCH_REG_PRI_CNTL 0x0084 /* Priority Control */ 52#define SWITCH_REG_PHY_CNTL4 0x00A0 /* PHY Control 4 */ 53#define SWITCH_REG_EMPTY_CNT 0x00A4 /* Empty Count */ 54#define SWITCH_REG_PORT_CNTLS 0x00A8 /* Port Control Select */ 55#define SWITCH_REG_PORT_CNTL 0x00AC /* Port Control */ 56#define SWITCH_REG_INT_STATUS 0x00B0 /* Interrupt Status */ 57#define SWITCH_REG_INT_MASK 0x00B4 /* Interrupt Mask */ 58#define SWITCH_REG_GPIO_CONF0 0x00B8 /* GPIO Configuration 0 */ 59#define SWITCH_REG_GPIO_CONF2 0x00BC /* GPIO Configuration 1 */ 60#define SWITCH_REG_WDOG0 0x00C0 /* Watchdog 0 */ 61#define SWITCH_REG_WDOG1 0x00C4 /* Watchdog 1 */ 62 63#define SWITCH_REG_SHDA 0x00D0 /* Send High Descriptors Address */ 64#define SWITCH_REG_SLDA 0x00D4 /* Send Low Descriptors Address */ 65#define SWITCH_REG_RHDA 0x00D8 /* Receive High Descriptor Address */ 66#define SWITCH_REG_RLDA 0x00DC /* Receive Low Descriptor Address */ 67#define SWITCH_REG_SHWA 0x00E0 /* Send High Working Address */ 68#define SWITCH_REG_SLWA 0x00E4 /* Send Low Working Address */ 69#define SWITCH_REG_RHWA 0x00E8 /* Receive High Working Address */ 70#define SWITCH_REG_RLWA 0x00EC /* Receive Low Working Address */ 71 72#define SWITCH_REG_TIMER_INT 0x00F0 /* Timer */ 73#define SWITCH_REG_TIMER 0x00F4 /* Timer Interrupt */ 74 75#define SWITCH_REG_PORT0_LED 0x0100 76#define SWITCH_REG_PORT1_LED 0x0104 77#define SWITCH_REG_PORT2_LED 0x0108 78#define SWITCH_REG_PORT3_LED 0x010C 79#define SWITCH_REG_PORT4_LED 0x0110 80 81/* CODE register bits */ 82#define CODE_PC_MASK BITMASK(16) /* Product Code */ 83#define CODE_REV_SHIFT 16 84#define CODE_REV_MASK BITMASK(4) /* Product Revision */ 85#define CODE_CLKS_SHIFT 20 86#define CODE_CLKS_MASK BITMASK(2) /* Clock Speed */ 87#define CODE_CLKS_175 0 /* 175 MHz */ 88#define CODE_CLKS_200 1 /* 200 MHz */ 89#define CODE_CLKS_225 2 /* 225 MHz */ 90#define CODE_CLKS_250 3 /* 250 MHz */ 91#define CODE_NAB BIT(24) /* NAND boot */ 92#define CODE_PK_MASK BITMASK(1) /* Package type */ 93#define CODE_PK_SHIFT 29 94#define CODE_PK_BGA 0 /* BGA package */ 95#define CODE_PK_PQFP 1 /* PQFP package */ 96 97/* MEMCTRL register bits */ 98#define MEMCTRL_SDRS_MASK BITMASK(3) /* SDRAM bank size */ 99#define MEMCTRL_SDRS_4M 0x01 100#define MEMCTRL_SDRS_8M 0x02 101#define MEMCTRL_SDRS_16M 0x03 102#define MEMCTRL_SDRS_64M 0x04 103#define MEMCTRL_SDRS_128M 0x05 104#define MEMCTRL_SDR1_ENABLE BIT(5) /* enable SDRAM bank 1 */ 105 106#define MEMCTRL_SRS0_SHIFT 8 /* shift for SRAM0 size */ 107#define MEMCTRL_SRS1_SHIFT 16 /* shift for SRAM1 size */ 108#define MEMCTRL_SRS_MASK BITMASK(3) /* SRAM size mask */ 109#define MEMCTRL_SRS_DISABLED 0x00 /* Disabled */ 110#define MEMCTRL_SRS_512K 0x01 /* 512KB*/ 111#define MEMCTRL_SRS_1M 0x02 /* 1MB */ 112#define MEMCTRL_SRS_2M 0x03 /* 2MB */ 113#define MEMCTRL_SRS_4M 0x04 /* 4MB */ 114 115/* Port bits used in various registers */ 116#define SWITCH_PORT_PHY0 BIT(0) 117#define SWITCH_PORT_PHY1 BIT(1) 118#define SWITCH_PORT_PHY2 BIT(2) 119#define SWITCH_PORT_PHY3 BIT(3) 120#define SWITCH_PORT_PHY4 BIT(4) 121#define SWITCH_PORT_MII BIT(5) 122#define SWITCH_PORT_CPU BIT(6) 123 124/* Port bit shorthands */ 125#define SWITCH_PORTS_PHY 0x1F /* phy ports */ 126#define SWITCH_PORTS_NOCPU 0x3F /* physical ports */ 127#define SWITCH_PORTS_ALL 0x7F /* all ports */ 128 129/* CPUP_CONF register bits */ 130#define CPUP_CONF_DCPUP BIT(0) /* Disable CPU port */ 131#define CPUP_CONF_CRCP BIT(1) /* CRC padding from CPU */ 132#define CPUP_CONF_BTM BIT(2) /* Bridge Testing Mode */ 133#define CPUP_CONF_DUNP_SHIFT 9 /* Disable Unknown Packets for portX */ 134#define CPUP_CONF_DMCP_SHIFT 16 /* Disable Mcast Packets form portX */ 135#define CPUP_CONF_DBCP_SHIFT 24 /* Disable Bcast Packets form portX */ 136 137/* PORT_CONF0 register bits */ 138#define PORT_CONF0_DP_SHIFT 0 /* Disable Port */ 139#define PORT_CONF0_EMCP_SHIFT 8 /* Enable All MC Packets */ 140#define PORT_CONF0_BP_SHIFT 16 /* Enable Back Pressure */ 141 142/* PORT_CONF1 register bits */ 143#define PORT_CONF1_DISL_SHIFT 0 /* Disable Learning */ 144#define PORT_CONF1_BS_SHIFT 6 /* Blocking State */ 145#define PORT_CONF1_BM_SHIFT 12 /* Blocking Mode */ 146 147/* SEND_TRIG register bits */ 148#define SEND_TRIG_STL BIT(0) /* Send Trigger Low */ 149#define SEND_TRIG_STH BIT(1) /* Send Trigger High */ 150 151/* MAC_WT0 register bits */ 152#define MAC_WT0_MAWC BIT(0) /* MAC address write command */ 153#define MAC_WT0_MWD_SHIFT 1 154#define MAC_WT0_MWD BIT(1) /* MAC write done */ 155#define MAC_WT0_WFB BIT(2) /* Write Filter Bit */ 156#define MAC_WT0_WVN_SHIFT 3 /* Write Vlan Number shift */ 157#define MAC_WT0_WVE BIT(6) /* Write VLAN enable */ 158#define MAC_WT0_WPMN_SHIFT 7 159#define MAC_WT0_WAF_SHIFT 13 /* Write Age Field shift */ 160#define MAC_WT0_WAF_EMPTY 0 161#define MAC_WT0_WAF_STATIC 7 /* age: static */ 162#define MAC_WT0_MAC0_SHIFT 16 163#define MAC_WT0_MAC1_SHIFT 24 164 165/* MAC_WT1 register bits */ 166#define MAC_WT1_MAC2_SHIFT 0 167#define MAC_WT1_MAC3_SHIFT 8 168#define MAC_WT1_MAC4_SHIFT 16 169#define MAC_WT1_MAC5_SHIFT 24 170 171/* BW_CNTL0/BW_CNTL1 register bits */ 172#define BW_CNTL_DISABLE 0x00 173#define BW_CNTL_64K 0x01 174#define BW_CNTL_128K 0x02 175#define BW_CNTL_256K 0x03 176#define BW_CNTL_512K 0x04 177#define BW_CNTL_1M 0x05 178#define BW_CNTL_4M 0x06 179#define BW_CNTL_10M 0x07 180 181#define P4TBC_SHIFT 0 182#define P4RBC_SHIFT 4 183#define P5TBC_SHIFT 8 184#define P5RBC_SHIFT 12 185 186#define BW_CNTL1_NAND_ENABLE 0x100 187 188/* PHY_CNTL0 register bits */ 189#define PHY_CNTL0_PHYA_MASK BITMASK(5) 190#define PHY_CNTL0_PHYR_MASK BITMASK(5) 191#define PHY_CNTL0_PHYR_SHIFT 8 192#define PHY_CNTL0_WC BIT(13) /* Write Command */ 193#define PHY_CNTL0_RC BIT(14) /* Read Command */ 194#define PHY_CNTL0_WTD_MASK BIT(16) /* Read Command */ 195#define PHY_CNTL0_WTD_SHIFT 16 196 197/* PHY_CNTL1 register bits */ 198#define PHY_CNTL1_WOD BIT(0) /* Write Operation Done */ 199#define PHY_CNTL1_ROD BIT(1) /* Read Operation Done */ 200#define PHY_CNTL1_RD_MASK BITMASK(16) 201#define PHY_CNTL1_RD_SHIFT 16 202 203/* PHY_CNTL2 register bits */ 204#define PHY_CNTL2_ANE_SHIFT 0 /* Auto Negotiation Enable */ 205#define PHY_CNTL2_SC_SHIFT 5 /* Speed Control */ 206#define PHY_CNTL2_DC_SHIFT 10 /* Duplex Control */ 207#define PHY_CNTL2_FNCV_SHIFT 15 /* Recommended FC Value */ 208#define PHY_CNTL2_PHYR_SHIFT 20 /* PHY reset */ 209#define PHY_CNTL2_AMDIX_SHIFT 25 /* Auto MDIX enable */ 210/* PHY_CNTL2_RMAE is bad in datasheet */ 211#define PHY_CNTL2_RMAE BIT(31) /* Recommended MCC Average enable */ 212 213/* PHY_CNTL3 register bits */ 214#define PHY_CNTL3_RNT BIT(10) /* Recommend Normal Threshold */ 215 216/* PORT_TH register bits */ 217#define PORT_TH_PPT_MASK BITMASK(8) /* Per Port Threshold */ 218#define PORT_TH_CPUT_SHIFT 8 /* CPU Port Buffer Threshold */ 219#define PORT_TH_CPUT_MASK BITMASK(8) 220#define PORT_TH_CPUHT_SHIFT 16 /* CPU Hold Threshold */ 221#define PORT_TH_CPUHT_MASK BITMASK(8) 222#define PORT_TH_CPURT_SHIFT 24 /* CPU Release Threshold */ 223#define PORT_TH_CPURT_MASK BITMASK(8) 224 225/* EMPTY_CNT register bits */ 226#define EMPTY_CNT_EBGB_MASK BITMASK(9) /* Empty Blocks in the Global Buffer */ 227 228/* GPIO_CONF0 register bits */ 229#define GPIO_CONF0_MASK BITMASK(8) 230#define GPIO_CONF0_IM_SHIFT 0 231#define GPIO_CONF0_IV_SHIFT 8 232#define GPIO_CONF0_OE_SHIFT 16 233#define GPIO_CONF0_OV_SHIFT 24 234#define GPIO_CONF0_IM_MASK (0xFF << GPIO_CONF0_IM_SHIFT) 235#define GPIO_CONF0_IV_MASK (0xFF << GPIO_CONF0_IV_SHIFT) 236#define GPIO_CONF0_OE_MASK (0xFF << GPIO_CONF0_OE_SHIFT) 237#define GPIO_CONF0_OV_MASK (0xFF << GPIO_CONF0_OV_SHIFT) 238 239/* GPIO_CONF2 register bits */ 240#define GPIO_CONF2_CSX0 BIT(4) /* enable CSX0:INTX0 on GPIO 1:2 */ 241#define GPIO_CONF2_CSX1 BIT(5) /* enable CSX1:INTX1 on GPIO 3:4 */ 242#define GPIO_CONF2_EW BIT(6) /* enable wait state pin for CSX0/1 */ 243 244/* INT_STATUS/INT_MASK register bits */ 245#define SWITCH_INT_SHD BIT(0) /* Send High Done */ 246#define SWITCH_INT_SLD BIT(1) /* Send Low Done */ 247#define SWITCH_INT_RHD BIT(2) /* Receive High Done */ 248#define SWITCH_INT_RLD BIT(3) /* Receive Low Done */ 249#define SWITCH_INT_HDF BIT(4) /* High Descriptor Full */ 250#define SWITCH_INT_LDF BIT(5) /* Low Descriptor Full */ 251#define SWITCH_INT_P0QF BIT(6) /* Port0 Queue Full */ 252#define SWITCH_INT_P1QF BIT(7) /* Port1 Queue Full */ 253#define SWITCH_INT_P2QF BIT(8) /* Port2 Queue Full */ 254#define SWITCH_INT_P3QF BIT(9) /* Port3 Queue Full */ 255#define SWITCH_INT_P4QF BIT(10) /* Port4 Queue Full */ 256#define SWITCH_INT_P5QF BIT(11) /* Port5 Queue Full */ 257#define SWITCH_INT_CPQF BIT(13) /* CPU Queue Full */ 258#define SWITCH_INT_GQF BIT(14) /* Global Queue Full */ 259#define SWITCH_INT_MD BIT(15) /* Must Drop */ 260#define SWITCH_INT_BCS BIT(16) /* BC Storm */ 261#define SWITCH_INT_PSC BIT(18) /* Port Status Change */ 262#define SWITCH_INT_ID BIT(19) /* Intruder Detected */ 263#define SWITCH_INT_W0TE BIT(20) /* Watchdog 0 Timer Expired */ 264#define SWITCH_INT_W1TE BIT(21) /* Watchdog 1 Timer Expired */ 265#define SWITCH_INT_RDE BIT(22) /* Receive Descriptor Error */ 266#define SWITCH_INT_SDE BIT(23) /* Send Descriptor Error */ 267#define SWITCH_INT_CPUH BIT(24) /* CPU Hold */ 268 269/* TIMER_INT register bits */ 270#define TIMER_INT_TOS BIT(0) /* time-out status */ 271#define TIMER_INT_TOM BIT(16) /* mask time-out interrupt */ 272 273/* TIMER register bits */ 274#define TIMER_PERIOD_MASK BITMASK(16) /* mask for timer period */ 275#define TIMER_PERIOD_DEFAULT 0xFFFF /* default timer period */ 276#define TIMER_TE BIT(16) /* timer enable bit */ 277 278/* PORTx_LED register bits */ 279#define LED_MODE_MASK BITMASK(4) 280#define LED_MODE_INPUT 0 281#define LED_MODE_FLASH 1 282#define LED_MODE_OUT_HIGH 2 283#define LED_MODE_OUT_LOW 3 284#define LED_MODE_LINK 4 285#define LED_MODE_SPEED 5 286#define LED_MODE_DUPLEX 6 287#define LED_MODE_ACT 7 288#define LED_MODE_COLL 8 289#define LED_MODE_LINK_ACT 9 290#define LED_MODE_DUPLEX_COLL 10 291#define LED_MODE_10M_ACT 11 292#define LED_MODE_100M_ACT 12 293#define LED0_MODE_SHIFT 0 /* LED0 mode shift */ 294#define LED1_MODE_SHIFT 4 /* LED1 mode shift */ 295#define LED2_MODE_SHIFT 8 /* LED2 mode shift */ 296#define LED0_IV_SHIFT 12 /* LED0 input value shift */ 297#define LED1_IV_SHIFT 13 /* LED1 input value shift */ 298#define LED2_IV_SHIFT 14 /* LED2 input value shift */ 299 300#endif /* _MACH_ADM5120_SWITCH_H */ 301