1/* 2 * ADM5120 MPMC (Multiport Memory Controller) register definitions 3 * 4 * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation. 9 * 10 */ 11 12#ifndef _MACH_ADM5120_MPMC_H 13#define _MACH_ADM5120_MPMC_H 14 15#define MPMC_READ_REG(r) __raw_readl( \ 16 (void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r) 17#define MPMC_WRITE_REG(r, v) __raw_writel((v), \ 18 (void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r) 19 20#define MPMC_REG_CTRL 0x0000 21#define MPMC_REG_STATUS 0x0004 22#define MPMC_REG_CONF 0x0008 23#define MPMC_REG_DC 0x0020 24#define MPMC_REG_DR 0x0024 25#define MPMC_REG_DRP 0x0030 26 27#define MPMC_REG_DC0 0x0100 28#define MPMC_REG_DRC0 0x0104 29#define MPMC_REG_DC1 0x0120 30#define MPMC_REG_DRC1 0x0124 31#define MPMC_REG_DC2 0x0140 32#define MPMC_REG_DRC2 0x0144 33#define MPMC_REG_DC3 0x0160 34#define MPMC_REG_DRC3 0x0164 35#define MPMC_REG_SC0 0x0200 /* for F_CS1_N */ 36#define MPMC_REG_SC1 0x0220 /* for F_CS0_N */ 37#define MPMC_REG_SC2 0x0240 38#define MPMC_REG_WEN2 0x0244 39#define MPMC_REG_OEN2 0x0248 40#define MPMC_REG_RD2 0x024C 41#define MPMC_REG_PG2 0x0250 42#define MPMC_REG_WR2 0x0254 43#define MPMC_REG_TN2 0x0258 44#define MPMC_REG_SC3 0x0260 45 46/* Control register bits */ 47#define MPMC_CTRL_AM (1 << 1) /* Address Mirror */ 48#define MPMC_CTRL_LPM (1 << 2) /* Low Power Mode */ 49#define MPMC_CTRL_DWB (1 << 3) /* Drain Write Buffers */ 50 51/* Status register bits */ 52#define MPMC_STATUS_BUSY (1 << 0) /* Busy */ 53#define MPMC_STATUS_WBS (1 << 1) /* Write Buffer Status */ 54#define MPMC_STATUS_SRA (1 << 2) /* Self-Refresh Acknowledge*/ 55 56/* Dynamic Control register bits */ 57#define MPMC_DC_CE (1 << 0) 58#define MPMC_DC_DMC (1 << 1) 59#define MPMC_DC_SRR (1 << 2) 60#define MPMC_DC_SI_SHIFT 7 61#define MPMC_DC_SI_MASK (3 << 7) 62#define MPMC_DC_SI_NORMAL (0 << 7) 63#define MPMC_DC_SI_MODE (1 << 7) 64#define MPMC_DC_SI_PALL (2 << 7) 65#define MPMC_DC_SI_NOP (3 << 7) 66 67#define SRAM_REG_CONF 0x00 68#define SRAM_REG_WWE 0x04 69#define SRAM_REG_WOE 0x08 70#define SRAM_REG_WRD 0x0C 71#define SRAM_REG_WPG 0x10 72#define SRAM_REG_WWR 0x14 73#define SRAM_REG_WTR 0x18 74 75/* Dynamic Configuration register bits */ 76#define DC_BE (1 << 19) /* buffer enable */ 77#define DC_RW_SHIFT 28 /* shift for number of rows */ 78#define DC_RW_MASK 0x03 79#define DC_NB_SHIFT 26 /* shift for number of banks */ 80#define DC_NB_MASK 0x01 81#define DC_CW_SHIFT 22 /* shift for number of columns */ 82#define DC_CW_MASK 0x07 83#define DC_DW_SHIFT 7 /* shift for device width */ 84#define DC_DW_MASK 0x03 85 86/* Static Configuration register bits */ 87#define SC_MW_MASK 0x03 /* memory width mask */ 88#define SC_MW_8 0x00 /* 8 bit memory width */ 89#define SC_MW_16 0x01 /* 16 bit memory width */ 90#define SC_MW_32 0x02 /* 32 bit memory width */ 91 92#endif /* _MACH_ADM5120_MPMC_H */ 93