1/* 2 * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved. 3 * Permission to use, copy, modify, and/or distribute this software for 4 * any purpose with or without fee is hereby granted, provided that the 5 * above copyright notice and this permission notice appear in all copies. 6 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 7 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 8 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 9 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 10 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 11 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 12 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 13 */ 14 15 16/** 17 * @defgroup isisc_port_ctrl ISISC_PORT_CONTROL 18 * @{ 19 */ 20#include "sw.h" 21#include "hsl.h" 22#include "hsl_dev.h" 23#include "hsl_port_prop.h" 24#include "isisc_port_ctrl.h" 25#include "isisc_reg.h" 26#include "hsl_phy.h" 27static a_bool_t 28_isisc_port_phy_connected(a_uint32_t dev_id, fal_port_t port_id) 29{ 30 if ((0 == port_id) || (6 == port_id)) 31 { 32 return A_FALSE; 33 } 34 else 35 { 36 return A_TRUE; 37 } 38} 39 40static sw_error_t 41_isisc_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, 42 fal_port_duplex_t duplex) 43{ 44 sw_error_t rv; 45 a_uint32_t phy_id, reg_save, reg_val, force, tmp; 46 hsl_phy_ops_t *phy_drv; 47 48 HSL_DEV_ID_CHECK(dev_id); 49 50 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 51 { 52 return SW_BAD_PARAM; 53 } 54 55 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 56 if (NULL == phy_drv->phy_duplex_set) 57 return SW_NOT_SUPPORTED; 58 59 if (FAL_DUPLEX_BUTT <= duplex) 60 { 61 return SW_BAD_PARAM; 62 } 63 64 HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, 65 (a_uint8_t *) (®_val), sizeof (a_uint32_t)); 66 SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, tmp, reg_val); 67 68 /* for those ports without PHY device we set MAC register */ 69 if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) 70 { 71 SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); 72 if (FAL_HALF_DUPLEX == duplex) 73 { 74 if (tmp == 0) 75 return SW_OK; 76 SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_val); 77 } 78 else 79 { 80 if (tmp == 1) 81 return SW_OK; 82 SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val); 83 } 84 reg_save = reg_val; 85 } 86 else 87 { 88 /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */ 89 rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); 90 SW_RTN_ON_ERROR(rv); 91 rv = phy_drv->phy_duplex_get (dev_id, phy_id, &tmp); 92 SW_RTN_ON_ERROR(rv); 93 if (tmp == duplex) 94 return SW_OK; 95 reg_save = reg_val; 96 SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); 97 SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val); 98 SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val); 99 100 HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, 101 (a_uint8_t *) (®_val), sizeof (a_uint32_t)); 102 103 rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex); 104 SW_RTN_ON_ERROR(rv); 105 106 /* If MAC not in sync with PHY mode, the behavior is undefine. 107 You must be careful... */ 108 SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save); 109 if (!force) 110 { 111 if (FAL_HALF_DUPLEX == duplex) 112 { 113 SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_save); 114 } 115 else 116 { 117 SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_save); 118 } 119 } 120 } 121 122 HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, 123 (a_uint8_t *) (®_save), sizeof (a_uint32_t)); 124 return rv; 125} 126 127static sw_error_t 128_isisc_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, 129 fal_port_duplex_t * pduplex) 130{ 131 sw_error_t rv; 132 a_uint32_t reg, field; 133 134 HSL_DEV_ID_CHECK(dev_id); 135 136 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 137 { 138 return SW_BAD_PARAM; 139 } 140 141 HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, 142 (a_uint8_t *) (®), sizeof (a_uint32_t)); 143 SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, field, reg); 144 if (field) 145 { 146 *pduplex = FAL_FULL_DUPLEX; 147 } 148 else 149 { 150 *pduplex = FAL_HALF_DUPLEX; 151 } 152 153 return SW_OK; 154} 155 156static sw_error_t 157_isisc_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, 158 fal_port_speed_t speed) 159{ 160 sw_error_t rv; 161 a_uint32_t phy_id, reg_save, reg_val, force, tmp; 162 hsl_phy_ops_t *phy_drv; 163 164 HSL_DEV_ID_CHECK(dev_id); 165 166 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 167 { 168 return SW_BAD_PARAM; 169 } 170 171 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 172 if (NULL == phy_drv->phy_speed_set) 173 return SW_NOT_SUPPORTED; 174 175 if (FAL_SPEED_1000 < speed) 176 { 177 return SW_BAD_PARAM; 178 } 179 180 HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, 181 (a_uint8_t *) (®_val), sizeof (a_uint32_t)); 182 SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, tmp, reg_val); 183 184 /* for those ports without PHY device we set MAC register */ 185 if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) 186 { 187 SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); 188 if (FAL_SPEED_10 == speed) 189 { 190 if (tmp == 0) 191 return SW_OK; 192 SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val); 193 } 194 else if (FAL_SPEED_100 == speed) 195 { 196 if (tmp == 1) 197 return SW_OK; 198 SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val); 199 } 200 else 201 { 202 if (tmp == 2) 203 return SW_OK; 204 SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val); 205 } 206 reg_save = reg_val; 207 208 } 209 else 210 { 211 /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */ 212 rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); 213 SW_RTN_ON_ERROR(rv); 214 rv = phy_drv->phy_speed_get (dev_id, phy_id, &tmp); 215 SW_RTN_ON_ERROR(rv); 216 if (tmp == speed) 217 return SW_OK; 218 reg_save = reg_val; 219 SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); 220 SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val); 221 SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val); 222 223 HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, 224 (a_uint8_t *) (®_val), sizeof (a_uint32_t)); 225 226 227 rv = phy_drv->phy_speed_set (dev_id, phy_id, speed); 228 SW_RTN_ON_ERROR(rv); 229 230 /* If MAC not in sync with PHY mode, the behavior is undefine. 231 You must be careful... */ 232 SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save); 233 if (!force) 234 { 235 if (FAL_SPEED_10 == speed) 236 { 237 SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_save); 238 } 239 else if (FAL_SPEED_100 == speed) 240 { 241 SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_save); 242 } 243 else 244 { 245 SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_save); 246 } 247 } 248 } 249 250 HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, 251 (a_uint8_t *) (®_save), sizeof (a_uint32_t)); 252 return rv; 253} 254 255static sw_error_t 256_isisc_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, 257 fal_port_speed_t * pspeed) 258{ 259 sw_error_t rv = SW_OK; 260 a_uint32_t reg, field; 261 262 HSL_DEV_ID_CHECK(dev_id); 263 264 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 265 { 266 return SW_BAD_PARAM; 267 } 268 269 HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, 270 (a_uint8_t *) (®), sizeof (a_uint32_t)); 271 SW_RTN_ON_ERROR(rv); 272 273 SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, field, reg); 274 if (0 == field) 275 { 276 *pspeed = FAL_SPEED_10; 277 } 278 else if (1 == field) 279 { 280 *pspeed = FAL_SPEED_100; 281 } 282 else if (2 == field) 283 { 284 *pspeed = FAL_SPEED_1000; 285 } 286 else 287 { 288 *pspeed = FAL_SPEED_BUTT; 289 rv = SW_READ_ERROR; 290 } 291 292 return rv; 293} 294 295static sw_error_t 296_isisc_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, 297 a_bool_t * status) 298{ 299 a_uint32_t phy_id; 300 sw_error_t rv; 301 hsl_phy_ops_t *phy_drv; 302 303 HSL_DEV_ID_CHECK(dev_id); 304 305 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) 306 { 307 return SW_BAD_PARAM; 308 } 309 310 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 311 if (NULL == phy_drv->phy_autoneg_status_get) 312 return SW_NOT_SUPPORTED; 313 314 rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); 315 SW_RTN_ON_ERROR(rv); 316 317 *status = phy_drv->phy_autoneg_status_get (dev_id, phy_id); 318 319 return SW_OK; 320} 321 322static sw_error_t 323_isisc_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id) 324{ 325 sw_error_t rv; 326 a_uint32_t phy_id; 327 hsl_phy_ops_t *phy_drv; 328 329 HSL_DEV_ID_CHECK(dev_id); 330 331 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) 332 { 333 return SW_BAD_PARAM; 334 } 335 336 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 337 if (NULL == phy_drv->phy_autoneg_enable_set) 338 return SW_NOT_SUPPORTED; 339 340 rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); 341 SW_RTN_ON_ERROR(rv); 342 343 rv = phy_drv->phy_autoneg_enable_set (dev_id, phy_id); 344 return rv; 345} 346 347static sw_error_t 348_isisc_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) 349{ 350 sw_error_t rv; 351 a_uint32_t phy_id; 352 hsl_phy_ops_t *phy_drv; 353 354 HSL_DEV_ID_CHECK(dev_id); 355 356 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) 357 { 358 return SW_BAD_PARAM; 359 } 360 361 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 362 if (NULL == phy_drv->phy_restart_autoneg) 363 return SW_NOT_SUPPORTED; 364 365 rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); 366 SW_RTN_ON_ERROR(rv); 367 368 rv = phy_drv->phy_restart_autoneg (dev_id, phy_id); 369 return rv; 370} 371 372static sw_error_t 373_isisc_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, 374 a_uint32_t autoadv) 375{ 376 sw_error_t rv; 377 a_uint32_t phy_id; 378 hsl_phy_ops_t *phy_drv; 379 380 HSL_DEV_ID_CHECK(dev_id); 381 382 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) 383 { 384 return SW_BAD_PARAM; 385 } 386 387 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 388 if (NULL == phy_drv->phy_autoneg_adv_set) 389 return SW_NOT_SUPPORTED; 390 391 rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); 392 SW_RTN_ON_ERROR(rv); 393 394 rv = phy_drv->phy_autoneg_adv_set (dev_id, phy_id, autoadv); 395 SW_RTN_ON_ERROR(rv); 396 397 return SW_OK; 398} 399 400static sw_error_t 401_isisc_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, 402 a_uint32_t * autoadv) 403{ 404 sw_error_t rv; 405 a_uint32_t phy_id; 406 hsl_phy_ops_t *phy_drv; 407 408 HSL_DEV_ID_CHECK(dev_id); 409 410 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) 411 { 412 return SW_BAD_PARAM; 413 } 414 415 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 416 if (NULL == phy_drv->phy_autoneg_adv_get) 417 return SW_NOT_SUPPORTED; 418 419 rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); 420 SW_RTN_ON_ERROR(rv); 421 422 *autoadv = 0; 423 rv = phy_drv->phy_autoneg_adv_get (dev_id, phy_id, autoadv); 424 SW_RTN_ON_ERROR(rv); 425 426 return SW_OK; 427} 428 429static sw_error_t 430_isisc_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 431{ 432 sw_error_t rv; 433 a_uint32_t val, force, reg, tmp; 434 435 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 436 { 437 return SW_BAD_PARAM; 438 } 439 440 if (A_TRUE == enable) 441 { 442 val = 1; 443 } 444 else if (A_FALSE == enable) 445 { 446 val = 0; 447 } 448 else 449 { 450 return SW_BAD_PARAM; 451 } 452 453 HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, 454 (a_uint8_t *) (®), sizeof (a_uint32_t)); 455 SW_RTN_ON_ERROR(rv); 456 457 SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); 458 if (force) 459 { 460 /* flow control isn't in force mode so can't set */ 461 return SW_DISABLE; 462 } 463 tmp = reg; 464 465 SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg); 466 SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg); 467 SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg); 468 if (tmp == reg) 469 return SW_OK; 470 471 HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, 472 (a_uint8_t *) (®), sizeof (a_uint32_t)); 473 return rv; 474} 475 476static sw_error_t 477_isisc_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, 478 a_bool_t * enable) 479{ 480 sw_error_t rv; 481 a_uint32_t rx, reg; 482 483 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 484 { 485 return SW_BAD_PARAM; 486 } 487 488 HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, 489 (a_uint8_t *) (®), sizeof (a_uint32_t)); 490 SW_RTN_ON_ERROR(rv); 491 492 SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg); 493 494 if (1 == rx) 495 { 496 *enable = A_TRUE; 497 } 498 else 499 { 500 *enable = A_FALSE; 501 } 502 503 return SW_OK; 504} 505 506static sw_error_t 507_isisc_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, 508 a_bool_t enable) 509{ 510 sw_error_t rv; 511 a_uint32_t reg, tmp; 512 513 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 514 { 515 return SW_BAD_PARAM; 516 } 517 518 HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, 519 (a_uint8_t *) (®), sizeof (a_uint32_t)); 520 SW_RTN_ON_ERROR(rv); 521 SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, tmp, reg); 522 523 if (A_TRUE == enable) 524 { 525 if (tmp == 0) 526 return SW_OK; 527 SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); 528 } 529 else if (A_FALSE == enable) 530 { 531 /* for those ports without PHY, it can't sync flow control status */ 532 if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) 533 { 534 return SW_DISABLE; 535 } 536 if (tmp == 1) 537 return SW_OK; 538 SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg); 539 } 540 else 541 { 542 return SW_BAD_PARAM; 543 } 544 545 HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, 546 (a_uint8_t *) (®), sizeof (a_uint32_t)); 547 return rv; 548} 549 550static sw_error_t 551_isisc_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, 552 a_bool_t * enable) 553{ 554 sw_error_t rv; 555 a_uint32_t force, reg; 556 557 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 558 { 559 return SW_BAD_PARAM; 560 } 561 562 HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, 563 (a_uint8_t *) (®), sizeof (a_uint32_t)); 564 SW_RTN_ON_ERROR(rv); 565 566 SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); 567 if (0 == force) 568 { 569 *enable = A_TRUE; 570 } 571 else 572 { 573 *enable = A_FALSE; 574 } 575 576 return SW_OK; 577} 578 579static sw_error_t 580_isisc_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 581{ 582 sw_error_t rv; 583 a_uint32_t phy_id = 0; 584 hsl_phy_ops_t *phy_drv; 585 586 HSL_DEV_ID_CHECK(dev_id); 587 588 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) 589 { 590 return SW_BAD_PARAM; 591 } 592 593 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 594 if (NULL == phy_drv->phy_powersave_set) 595 return SW_NOT_SUPPORTED; 596 597 rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); 598 SW_RTN_ON_ERROR(rv); 599 600 rv = phy_drv->phy_powersave_set (dev_id, phy_id, enable); 601 602 return rv; 603} 604 605static sw_error_t 606_isisc_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, 607 a_bool_t * enable) 608{ 609 sw_error_t rv; 610 a_uint32_t phy_id = 0; 611 hsl_phy_ops_t *phy_drv; 612 613 HSL_DEV_ID_CHECK(dev_id); 614 615 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) 616 { 617 return SW_BAD_PARAM; 618 } 619 620 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 621 if (NULL == phy_drv->phy_powersave_get) 622 return SW_NOT_SUPPORTED; 623 624 rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); 625 SW_RTN_ON_ERROR(rv); 626 627 rv = phy_drv->phy_powersave_get (dev_id, phy_id, enable); 628 629 return rv; 630} 631 632static sw_error_t 633_isisc_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 634{ 635 sw_error_t rv; 636 a_uint32_t phy_id = 0; 637 hsl_phy_ops_t *phy_drv; 638 639 HSL_DEV_ID_CHECK(dev_id); 640 641 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) 642 { 643 return SW_BAD_PARAM; 644 } 645 646 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 647 if (NULL == phy_drv->phy_hibernation_set) 648 return SW_NOT_SUPPORTED; 649 650 rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); 651 SW_RTN_ON_ERROR(rv); 652 653 rv = phy_drv->phy_hibernation_set (dev_id, phy_id, enable); 654 655 return rv; 656} 657 658static sw_error_t 659_isisc_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, 660 a_bool_t * enable) 661{ 662 sw_error_t rv; 663 a_uint32_t phy_id = 0; 664 hsl_phy_ops_t *phy_drv; 665 666 HSL_DEV_ID_CHECK(dev_id); 667 668 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) 669 { 670 return SW_BAD_PARAM; 671 } 672 673 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 674 if (NULL == phy_drv->phy_hibernation_get) 675 return SW_NOT_SUPPORTED; 676 677 rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); 678 SW_RTN_ON_ERROR(rv); 679 680 rv = phy_drv->phy_hibernation_get (dev_id, phy_id, enable); 681 682 return rv; 683} 684 685static sw_error_t 686_isisc_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, 687 fal_cable_status_t * cable_status, a_uint32_t * cable_len) 688{ 689 sw_error_t rv; 690 a_uint32_t phy_id = 0; 691 hsl_phy_ops_t *phy_drv; 692 693 HSL_DEV_ID_CHECK(dev_id); 694 695 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) 696 { 697 return SW_BAD_PARAM; 698 } 699 700 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 701 if (NULL == phy_drv->phy_cdt) 702 return SW_NOT_SUPPORTED; 703 704 rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); 705 SW_RTN_ON_ERROR(rv); 706 707 rv = phy_drv->phy_cdt (dev_id, phy_id, mdi_pair, cable_status, cable_len); 708 709 return rv; 710} 711 712static sw_error_t 713_isisc_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, 714 fal_port_header_mode_t mode) 715{ 716 sw_error_t rv; 717 a_uint32_t val; 718 719 HSL_DEV_ID_CHECK(dev_id); 720 721 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 722 { 723 return SW_BAD_PARAM; 724 } 725 726 if (FAL_NO_HEADER_EN == mode) 727 { 728 val = 0; 729 } 730 else if (FAL_ONLY_MANAGE_FRAME_EN == mode) 731 { 732 val = 1; 733 } 734 else if (FAL_ALL_TYPE_FRAME_EN == mode) 735 { 736 val = 2; 737 } 738 else 739 { 740 return SW_BAD_PARAM; 741 } 742 743 HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE, 744 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 745 return rv; 746} 747 748static sw_error_t 749_isisc_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, 750 fal_port_header_mode_t * mode) 751{ 752 sw_error_t rv; 753 a_uint32_t val; 754 755 HSL_DEV_ID_CHECK(dev_id); 756 757 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 758 { 759 return SW_BAD_PARAM; 760 } 761 762 HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE, 763 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 764 SW_RTN_ON_ERROR(rv); 765 766 if (1 == val) 767 { 768 *mode = FAL_ONLY_MANAGE_FRAME_EN; 769 } 770 else if (2 == val) 771 { 772 *mode = FAL_ALL_TYPE_FRAME_EN; 773 } 774 else 775 { 776 *mode = FAL_NO_HEADER_EN; 777 } 778 779 return SW_OK; 780} 781 782static sw_error_t 783_isisc_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, 784 fal_port_header_mode_t mode) 785{ 786 sw_error_t rv; 787 a_uint32_t val; 788 789 HSL_DEV_ID_CHECK(dev_id); 790 791 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 792 { 793 return SW_BAD_PARAM; 794 } 795 796 if (FAL_NO_HEADER_EN == mode) 797 { 798 val = 0; 799 } 800 else if (FAL_ONLY_MANAGE_FRAME_EN == mode) 801 { 802 val = 1; 803 } 804 else if (FAL_ALL_TYPE_FRAME_EN == mode) 805 { 806 val = 2; 807 } 808 else 809 { 810 return SW_BAD_PARAM; 811 } 812 813 HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE, 814 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 815 return rv; 816} 817 818static sw_error_t 819_isisc_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, 820 fal_port_header_mode_t * mode) 821{ 822 sw_error_t rv; 823 a_uint32_t val; 824 825 HSL_DEV_ID_CHECK(dev_id); 826 827 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 828 { 829 return SW_BAD_PARAM; 830 } 831 832 HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE, 833 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 834 SW_RTN_ON_ERROR(rv); 835 836 if (1 == val) 837 { 838 *mode = FAL_ONLY_MANAGE_FRAME_EN; 839 } 840 else if (2 == val) 841 { 842 *mode = FAL_ALL_TYPE_FRAME_EN; 843 } 844 else 845 { 846 *mode = FAL_NO_HEADER_EN; 847 } 848 849 return SW_OK; 850} 851 852static sw_error_t 853_isisc_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type) 854{ 855 a_uint32_t reg; 856 sw_error_t rv; 857 858 HSL_DEV_ID_CHECK(dev_id); 859 860 HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0, 861 (a_uint8_t *) (®), sizeof (a_uint32_t)); 862 SW_RTN_ON_ERROR(rv); 863 864 if (A_TRUE == enable) 865 { 866 if (0xffff < type) 867 { 868 return SW_BAD_PARAM; 869 } 870 SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 1, reg); 871 SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, type, reg); 872 } 873 else if (A_FALSE == enable) 874 { 875 SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 0, reg); 876 SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, 0, reg); 877 } 878 else 879 { 880 return SW_BAD_PARAM; 881 } 882 883 HSL_REG_ENTRY_SET(rv, dev_id, HEADER_CTL, 0, 884 (a_uint8_t *) (®), sizeof (a_uint32_t)); 885 return rv; 886} 887 888static sw_error_t 889_isisc_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type) 890{ 891 a_uint32_t data, reg; 892 sw_error_t rv; 893 894 HSL_DEV_ID_CHECK(dev_id); 895 896 HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0, 897 (a_uint8_t *) (®), sizeof (a_uint32_t)); 898 SW_RTN_ON_ERROR(rv); 899 900 SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_LEN, data, reg); 901 if (data) 902 { 903 SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_VAL, data, reg); 904 *enable = A_TRUE; 905 *type = data; 906 } 907 else 908 { 909 *enable = A_FALSE; 910 *type = 0; 911 } 912 913 return SW_OK; 914} 915 916static sw_error_t 917_isisc_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 918{ 919 sw_error_t rv; 920 a_uint32_t reg, force, val, tmp; 921 922 HSL_DEV_ID_CHECK(dev_id); 923 924 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 925 { 926 return SW_BAD_PARAM; 927 } 928 929 HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, 930 (a_uint8_t *) (®), sizeof (a_uint32_t)); 931 SW_RTN_ON_ERROR(rv); 932 933 if (A_TRUE == enable) 934 { 935 val = 1; 936 } 937 else if (A_FALSE == enable) 938 { 939 val = 0; 940 } 941 else 942 { 943 return SW_BAD_PARAM; 944 } 945 tmp = reg; 946 947 /* for those ports without PHY device we set MAC register */ 948 if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) 949 { 950 SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); 951 SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg); 952 } 953 else 954 { 955 SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg); 956 if (force) 957 { 958 /* link isn't in force mode so can't set */ 959 return SW_DISABLE; 960 } 961 else 962 { 963 SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg); 964 } 965 } 966 if (tmp == reg) 967 return SW_OK; 968 HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, 969 (a_uint8_t *) (®), sizeof (a_uint32_t)); 970 return rv; 971} 972 973static sw_error_t 974_isisc_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) 975{ 976 sw_error_t rv; 977 a_uint32_t val; 978 979 HSL_DEV_ID_CHECK(dev_id); 980 981 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 982 { 983 return SW_BAD_PARAM; 984 } 985 986 HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TXMAC_EN, 987 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 988 SW_RTN_ON_ERROR(rv); 989 990 if (val) 991 { 992 *enable = A_TRUE; 993 } 994 else 995 { 996 *enable = A_FALSE; 997 } 998 999 return SW_OK; 1000} 1001 1002static sw_error_t 1003_isisc_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 1004{ 1005 sw_error_t rv; 1006 a_uint32_t reg, force, val, tmp; 1007 1008 HSL_DEV_ID_CHECK(dev_id); 1009 1010 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 1011 { 1012 return SW_BAD_PARAM; 1013 } 1014 1015 HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, 1016 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1017 SW_RTN_ON_ERROR(rv); 1018 1019 if (A_TRUE == enable) 1020 { 1021 val = 1; 1022 } 1023 else if (A_FALSE == enable) 1024 { 1025 val = 0; 1026 } 1027 else 1028 { 1029 return SW_BAD_PARAM; 1030 } 1031 tmp = reg; 1032 1033 /* for those ports without PHY device we set MAC register */ 1034 if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) 1035 { 1036 SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); 1037 SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg); 1038 } 1039 else 1040 { 1041 SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg); 1042 if (force) 1043 { 1044 /* link isn't in force mode so can't set */ 1045 return SW_DISABLE; 1046 } 1047 else 1048 { 1049 SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg); 1050 } 1051 } 1052 if (tmp == reg) 1053 return SW_OK; 1054 HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, 1055 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1056 return rv; 1057} 1058 1059static sw_error_t 1060_isisc_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) 1061{ 1062 sw_error_t rv; 1063 a_uint32_t val; 1064 1065 HSL_DEV_ID_CHECK(dev_id); 1066 1067 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 1068 { 1069 return SW_BAD_PARAM; 1070 } 1071 1072 HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RXMAC_EN, 1073 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1074 SW_RTN_ON_ERROR(rv); 1075 1076 if (val) 1077 { 1078 *enable = A_TRUE; 1079 } 1080 else 1081 { 1082 *enable = A_FALSE; 1083 } 1084 1085 return SW_OK; 1086} 1087 1088static sw_error_t 1089_isisc_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 1090{ 1091 sw_error_t rv; 1092 a_uint32_t val, reg, force, tmp; 1093 1094 HSL_DEV_ID_CHECK(dev_id); 1095 1096 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 1097 { 1098 return SW_BAD_PARAM; 1099 } 1100 1101 if (A_TRUE == enable) 1102 { 1103 val = 1; 1104 } 1105 else if (A_FALSE == enable) 1106 { 1107 val = 0; 1108 } 1109 else 1110 { 1111 return SW_BAD_PARAM; 1112 } 1113 1114 HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, 1115 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1116 SW_RTN_ON_ERROR(rv); 1117 tmp = reg; 1118 1119 /* for those ports without PHY device we set MAC register */ 1120 if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) 1121 { 1122 SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); 1123 SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg); 1124 } 1125 else 1126 { 1127 SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); 1128 if (force) 1129 { 1130 /* flow control isn't in force mode so can't set */ 1131 return SW_DISABLE; 1132 } 1133 else 1134 { 1135 SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg); 1136 } 1137 } 1138 if (tmp == reg) 1139 return SW_OK; 1140 HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, 1141 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1142 return rv; 1143} 1144 1145static sw_error_t 1146_isisc_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) 1147{ 1148 sw_error_t rv; 1149 a_uint32_t val; 1150 1151 HSL_DEV_ID_CHECK(dev_id); 1152 1153 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 1154 { 1155 return SW_BAD_PARAM; 1156 } 1157 1158 HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_FLOW_EN, 1159 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1160 SW_RTN_ON_ERROR(rv); 1161 1162 if (val) 1163 { 1164 *enable = A_TRUE; 1165 } 1166 else 1167 { 1168 *enable = A_FALSE; 1169 } 1170 1171 return SW_OK; 1172} 1173 1174static sw_error_t 1175_isisc_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 1176{ 1177 sw_error_t rv; 1178 a_uint32_t val, reg, force, tmp; 1179 1180 HSL_DEV_ID_CHECK(dev_id); 1181 1182 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 1183 { 1184 return SW_BAD_PARAM; 1185 } 1186 1187 if (A_TRUE == enable) 1188 { 1189 val = 1; 1190 } 1191 else if (A_FALSE == enable) 1192 { 1193 val = 0; 1194 } 1195 else 1196 { 1197 return SW_BAD_PARAM; 1198 } 1199 1200 HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, 1201 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1202 SW_RTN_ON_ERROR(rv); 1203 tmp = reg; 1204 1205 /* for those ports without PHY device we set MAC register */ 1206 if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) 1207 { 1208 SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); 1209 SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg); 1210 } 1211 else 1212 { 1213 SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); 1214 if (force) 1215 { 1216 /* flow control isn't in force mode so can't set */ 1217 return SW_DISABLE; 1218 } 1219 else 1220 { 1221 SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg); 1222 } 1223 } 1224 if ( tmp == reg) 1225 return SW_OK; 1226 HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, 1227 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1228 return rv; 1229} 1230 1231static sw_error_t 1232_isisc_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) 1233{ 1234 sw_error_t rv; 1235 a_uint32_t val; 1236 1237 HSL_DEV_ID_CHECK(dev_id); 1238 1239 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 1240 { 1241 return SW_BAD_PARAM; 1242 } 1243 1244 HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RX_FLOW_EN, 1245 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1246 SW_RTN_ON_ERROR(rv); 1247 1248 if (val) 1249 { 1250 *enable = A_TRUE; 1251 } 1252 else 1253 { 1254 *enable = A_FALSE; 1255 } 1256 1257 return SW_OK; 1258} 1259 1260static sw_error_t 1261_isisc_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 1262{ 1263 sw_error_t rv; 1264 a_uint32_t val, tmp; 1265 1266 HSL_DEV_ID_CHECK(dev_id); 1267 1268 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 1269 { 1270 return SW_BAD_PARAM; 1271 } 1272 1273 if (A_TRUE == enable) 1274 { 1275 val = 1; 1276 } 1277 else if (A_FALSE == enable) 1278 { 1279 val = 0; 1280 } 1281 else 1282 { 1283 return SW_BAD_PARAM; 1284 } 1285 HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN, 1286 (a_uint8_t *) (&tmp), sizeof (a_uint32_t)); 1287 if (tmp == val) 1288 return SW_OK; 1289 1290 HSL_REG_FIELD_SET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN, 1291 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1292 return rv; 1293} 1294 1295static sw_error_t 1296_isisc_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) 1297{ 1298 sw_error_t rv; 1299 a_uint32_t val; 1300 1301 HSL_DEV_ID_CHECK(dev_id); 1302 1303 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 1304 { 1305 return SW_BAD_PARAM; 1306 } 1307 1308 HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN, 1309 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1310 SW_RTN_ON_ERROR(rv); 1311 1312 if (val) 1313 { 1314 *enable = A_TRUE; 1315 } 1316 else 1317 { 1318 *enable = A_FALSE; 1319 } 1320 1321 return SW_OK; 1322} 1323 1324static sw_error_t 1325_isisc_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 1326{ 1327 sw_error_t rv; 1328 a_uint32_t reg, tmp; 1329 1330 HSL_DEV_ID_CHECK(dev_id); 1331 1332 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 1333 { 1334 return SW_BAD_PARAM; 1335 } 1336 1337 HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, 1338 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1339 SW_RTN_ON_ERROR(rv); 1340 1341 SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, tmp, reg); 1342 1343 if (A_TRUE == enable) 1344 { 1345 if(tmp == 0) 1346 return SW_OK; 1347 1348 SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); 1349 } 1350 else if (A_FALSE == enable) 1351 { 1352 if(tmp == 1) 1353 return SW_OK; 1354 1355 /* for those ports without PHY, it can't sync link status */ 1356 if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) 1357 { 1358 return SW_DISABLE; 1359 } 1360 SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg); 1361 } 1362 else 1363 { 1364 return SW_BAD_PARAM; 1365 } 1366 1367 HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, 1368 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1369 return rv; 1370} 1371 1372static sw_error_t 1373_isisc_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) 1374{ 1375 sw_error_t rv; 1376 a_uint32_t val; 1377 1378 HSL_DEV_ID_CHECK(dev_id); 1379 1380 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 1381 { 1382 return SW_BAD_PARAM; 1383 } 1384 1385 HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, LINK_EN, 1386 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1387 SW_RTN_ON_ERROR(rv); 1388 1389 if (0 == val) 1390 { 1391 *enable = A_TRUE; 1392 } 1393 else 1394 { 1395 *enable = A_FALSE; 1396 } 1397 1398 return SW_OK; 1399} 1400 1401static sw_error_t 1402_isisc_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status) 1403{ 1404 sw_error_t rv; 1405 a_uint32_t phy_id; 1406 hsl_phy_ops_t *phy_drv; 1407 1408 HSL_DEV_ID_CHECK(dev_id); 1409 1410 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 1411 { 1412 return SW_BAD_PARAM; 1413 } 1414 1415 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 1416 if (NULL == phy_drv->phy_link_status_get) 1417 return SW_NOT_SUPPORTED; 1418 1419 /* for those ports without PHY device supposed always link up */ 1420 if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) 1421 { 1422 *status = A_TRUE; 1423 } 1424 else 1425 { 1426 rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); 1427 SW_RTN_ON_ERROR(rv); 1428 1429 if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id)) 1430 { 1431 *status = A_TRUE; 1432 } 1433 else 1434 { 1435 *status = A_FALSE; 1436 } 1437 } 1438 1439 return SW_OK; 1440} 1441 1442static sw_error_t 1443_isisc_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status) 1444{ 1445 sw_error_t rv; 1446 a_uint32_t port_id; 1447 a_uint32_t phy_id; 1448 hsl_dev_t *pdev = NULL; 1449 hsl_phy_ops_t *phy_drv; 1450 HSL_DEV_ID_CHECK(dev_id); 1451 1452 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 1453 if (NULL == phy_drv->phy_link_status_get) 1454 return SW_NOT_SUPPORTED; 1455 1456 pdev = hsl_dev_ptr_get(dev_id); 1457 if (pdev == NULL) 1458 return SW_NOT_INITIALIZED; 1459 1460 *status = 0x0; 1461 for (port_id = 0; port_id < pdev->nr_ports; port_id++) 1462 { 1463 /* for those ports without PHY device supposed always link up */ 1464 if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) 1465 { 1466 *status |= (0x1 << port_id); 1467 } 1468 else 1469 { 1470 rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); 1471 SW_RTN_ON_ERROR(rv); 1472 1473 if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id)) 1474 { 1475 *status |= (0x1 << port_id); 1476 } 1477 else 1478 { 1479 *status &= ~(0x1 << port_id); 1480 } 1481 } 1482 } 1483 return SW_OK; 1484} 1485 1486static sw_error_t 1487_isisc_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 1488{ 1489 sw_error_t rv; 1490 a_uint32_t val; 1491 1492 HSL_DEV_ID_CHECK(dev_id); 1493 1494 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 1495 { 1496 return SW_BAD_PARAM; 1497 } 1498 1499 if (A_TRUE == enable) 1500 { 1501 val = 1; 1502 } 1503 else if (A_FALSE == enable) 1504 { 1505 val = 0; 1506 } 1507 else 1508 { 1509 return SW_BAD_PARAM; 1510 } 1511 1512 HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN, 1513 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1514 return SW_OK; 1515} 1516 1517static sw_error_t 1518_isisc_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) 1519{ 1520 sw_error_t rv; 1521 a_uint32_t val; 1522 1523 HSL_DEV_ID_CHECK(dev_id); 1524 1525 if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) 1526 { 1527 return SW_BAD_PARAM; 1528 } 1529 1530 HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN, 1531 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1532 SW_RTN_ON_ERROR(rv); 1533 1534 if (0 == val) 1535 { 1536 *enable = A_FALSE; 1537 } 1538 else 1539 { 1540 *enable = A_TRUE; 1541 } 1542 1543 return SW_OK; 1544} 1545 1546/** 1547 * @brief Set duplex mode on a particular port. 1548 * @param[in] dev_id device id 1549 * @param[in] port_id port id 1550 * @param[in] duplex duplex mode 1551 * @return SW_OK or error code 1552 */ 1553HSL_LOCAL sw_error_t 1554isisc_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, 1555 fal_port_duplex_t duplex) 1556{ 1557 sw_error_t rv; 1558 1559 HSL_API_LOCK; 1560 rv = _isisc_port_duplex_set(dev_id, port_id, duplex); 1561 HSL_API_UNLOCK; 1562 return rv; 1563} 1564 1565/** 1566 * @brief Get duplex mode on a particular port. 1567 * @param[in] dev_id device id 1568 * @param[in] port_id port id 1569 * @param[out] duplex duplex mode 1570 * @return SW_OK or error code 1571 */ 1572HSL_LOCAL sw_error_t 1573isisc_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, 1574 fal_port_duplex_t * pduplex) 1575{ 1576 sw_error_t rv; 1577 1578 HSL_API_LOCK; 1579 rv = _isisc_port_duplex_get(dev_id, port_id, pduplex); 1580 HSL_API_UNLOCK; 1581 return rv; 1582} 1583 1584/** 1585 * @brief Set speed on a particular port. 1586 * @param[in] dev_id device id 1587 * @param[in] port_id port id 1588 * @param[in] speed port speed 1589 * @return SW_OK or error code 1590 */ 1591HSL_LOCAL sw_error_t 1592isisc_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, 1593 fal_port_speed_t speed) 1594{ 1595 sw_error_t rv; 1596 1597 HSL_API_LOCK; 1598 rv = _isisc_port_speed_set(dev_id, port_id, speed); 1599 HSL_API_UNLOCK; 1600 return rv; 1601} 1602 1603/** 1604 * @brief Get speed on a particular port. 1605 * @param[in] dev_id device id 1606 * @param[in] port_id port id 1607 * @param[out] speed port speed 1608 * @return SW_OK or error code 1609 */ 1610HSL_LOCAL sw_error_t 1611isisc_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, 1612 fal_port_speed_t * pspeed) 1613{ 1614 sw_error_t rv; 1615 1616 HSL_API_LOCK; 1617 rv = _isisc_port_speed_get(dev_id, port_id, pspeed); 1618 HSL_API_UNLOCK; 1619 return rv; 1620} 1621 1622/** 1623 * @brief Get auto negotiation status on a particular port. 1624 * @param[in] dev_id device id 1625 * @param[in] port_id port id 1626 * @param[out] status A_TRUE or A_FALSE 1627 * @return SW_OK or error code 1628 */ 1629HSL_LOCAL sw_error_t 1630isisc_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, 1631 a_bool_t * status) 1632{ 1633 sw_error_t rv; 1634 1635 HSL_API_LOCK; 1636 rv = _isisc_port_autoneg_status_get(dev_id, port_id, status); 1637 HSL_API_UNLOCK; 1638 return rv; 1639} 1640 1641/** 1642 * @brief Enable auto negotiation status on a particular port. 1643 * @param[in] dev_id device id 1644 * @param[in] port_id port id 1645 * @return SW_OK or error code 1646 */ 1647HSL_LOCAL sw_error_t 1648isisc_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id) 1649{ 1650 sw_error_t rv; 1651 1652 HSL_API_LOCK; 1653 rv = _isisc_port_autoneg_enable(dev_id, port_id); 1654 HSL_API_UNLOCK; 1655 return rv; 1656} 1657 1658/** 1659 * @brief Restart auto negotiation procedule on a particular port. 1660 * @param[in] dev_id device id 1661 * @param[in] port_id port id 1662 * @return SW_OK or error code 1663 */ 1664HSL_LOCAL sw_error_t 1665isisc_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) 1666{ 1667 sw_error_t rv; 1668 1669 HSL_API_LOCK; 1670 rv = _isisc_port_autoneg_restart(dev_id, port_id); 1671 HSL_API_UNLOCK; 1672 return rv; 1673} 1674 1675/** 1676 * @brief Set auto negotiation advtisement ability on a particular port. 1677 * @details Comments: 1678 * auto negotiation advtisement ability is defined by macro such as 1679 * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE... 1680 * @param[in] dev_id device id 1681 * @param[in] port_id port id 1682 * @param[in] autoadv auto negotiation advtisement ability bit map 1683 * @return SW_OK or error code 1684 */ 1685HSL_LOCAL sw_error_t 1686isisc_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, 1687 a_uint32_t autoadv) 1688{ 1689 sw_error_t rv; 1690 1691 HSL_API_LOCK; 1692 rv = _isisc_port_autoneg_adv_set(dev_id, port_id, autoadv); 1693 HSL_API_UNLOCK; 1694 return rv; 1695} 1696 1697/** 1698 * @brief Get auto negotiation advtisement ability on a particular port. 1699 * @param[in] dev_id device id 1700 * @param[in] port_id port id 1701 * @param[out] autoadv auto negotiation advtisement ability bit map 1702 * @return SW_OK or error code 1703 */ 1704HSL_LOCAL sw_error_t 1705isisc_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, 1706 a_uint32_t * autoadv) 1707{ 1708 sw_error_t rv; 1709 1710 HSL_API_LOCK; 1711 rv = _isisc_port_autoneg_adv_get(dev_id, port_id, autoadv); 1712 HSL_API_UNLOCK; 1713 return rv; 1714} 1715 1716/** 1717 * @brief Set flow control(rx/tx/bp) status on a particular port. 1718 * @param[in] dev_id device id 1719 * @param[in] port_id port id 1720 * @param[in] enable A_TRUE or A_FALSE 1721 * @return SW_OK or error code 1722 */ 1723HSL_LOCAL sw_error_t 1724isisc_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 1725{ 1726 sw_error_t rv; 1727 1728 HSL_API_LOCK; 1729 rv = _isisc_port_flowctrl_set(dev_id, port_id, enable); 1730 HSL_API_UNLOCK; 1731 return rv; 1732} 1733 1734/** 1735 * @brief Get flow control status on a particular port. 1736 * @param[in] dev_id device id 1737 * @param[in] port_id port id 1738 * @param[out] enable A_TRUE or A_FALSE 1739 * @return SW_OK or error code 1740 */ 1741HSL_LOCAL sw_error_t 1742isisc_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) 1743{ 1744 sw_error_t rv; 1745 1746 HSL_API_LOCK; 1747 rv = _isisc_port_flowctrl_get(dev_id, port_id, enable); 1748 HSL_API_UNLOCK; 1749 return rv; 1750} 1751 1752/** 1753 * @brief Set flow control force mode on a particular port. 1754 * @param[in] dev_id device id 1755 * @param[in] port_id port id 1756 * @param[out] enable A_TRUE or A_FALSE 1757 * @return SW_OK or error code 1758 */ 1759HSL_LOCAL sw_error_t 1760isisc_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, 1761 a_bool_t enable) 1762{ 1763 sw_error_t rv; 1764 1765 HSL_API_LOCK; 1766 rv = _isisc_port_flowctrl_forcemode_set(dev_id, port_id, enable); 1767 HSL_API_UNLOCK; 1768 return rv; 1769} 1770 1771/** 1772 * @brief Get flow control force mode on a particular port. 1773 * @param[in] dev_id device id 1774 * @param[in] port_id port id 1775 * @param[out] enable A_TRUE or A_FALSE 1776 * @return SW_OK or error code 1777 */ 1778HSL_LOCAL sw_error_t 1779isisc_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, 1780 a_bool_t * enable) 1781{ 1782 sw_error_t rv; 1783 1784 HSL_API_LOCK; 1785 rv = _isisc_port_flowctrl_forcemode_get(dev_id, port_id, enable); 1786 HSL_API_UNLOCK; 1787 return rv; 1788} 1789 1790/** 1791 * @brief Set powersaving status on a particular port. 1792 * @param[in] dev_id device id 1793 * @param[in] port_id port id 1794 * @param[out] enable A_TRUE or A_FALSE 1795 * @return SW_OK or error code 1796 */ 1797HSL_LOCAL sw_error_t 1798isisc_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 1799{ 1800 sw_error_t rv; 1801 1802 HSL_API_LOCK; 1803 rv = _isisc_port_powersave_set(dev_id, port_id, enable); 1804 HSL_API_UNLOCK; 1805 return rv; 1806} 1807 1808/** 1809 * @brief Get powersaving status on a particular port. 1810 * @param[in] dev_id device id 1811 * @param[in] port_id port id 1812 * @param[out] enable A_TRUE or A_FALSE 1813 * @return SW_OK or error code 1814 */ 1815HSL_LOCAL sw_error_t 1816isisc_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, 1817 a_bool_t * enable) 1818{ 1819 sw_error_t rv; 1820 1821 HSL_API_LOCK; 1822 rv = _isisc_port_powersave_get(dev_id, port_id, enable); 1823 HSL_API_UNLOCK; 1824 return rv; 1825} 1826 1827/** 1828 * @brief Set hibernate status on a particular port. 1829 * @param[in] dev_id device id 1830 * @param[in] port_id port id 1831 * @param[out] enable A_TRUE or A_FALSE 1832 * @return SW_OK or error code 1833 */ 1834HSL_LOCAL sw_error_t 1835isisc_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 1836{ 1837 sw_error_t rv; 1838 1839 HSL_API_LOCK; 1840 rv = _isisc_port_hibernate_set(dev_id, port_id, enable); 1841 HSL_API_UNLOCK; 1842 return rv; 1843} 1844 1845/** 1846 * @brief Get hibernate status on a particular port. 1847 * @param[in] dev_id device id 1848 * @param[in] port_id port id 1849 * @param[out] enable A_TRUE or A_FALSE 1850 * @return SW_OK or error code 1851 */ 1852HSL_LOCAL sw_error_t 1853isisc_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, 1854 a_bool_t * enable) 1855{ 1856 sw_error_t rv; 1857 1858 HSL_API_LOCK; 1859 rv = _isisc_port_hibernate_get(dev_id, port_id, enable); 1860 HSL_API_UNLOCK; 1861 return rv; 1862} 1863 1864/** 1865 * @brief Run cable diagnostic test on a particular port. 1866 * @param[in] dev_id device id 1867 * @param[in] port_id port id 1868 * @param[in] mdi_pair mdi pair id 1869 * @param[out] cable_status cable status 1870 * @param[out] cable_len cable len 1871 * @return SW_OK or error code 1872 */ 1873HSL_LOCAL sw_error_t 1874isisc_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, 1875 fal_cable_status_t * cable_status, a_uint32_t * cable_len) 1876{ 1877 sw_error_t rv; 1878 1879 HSL_API_LOCK; 1880 rv = _isisc_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len); 1881 HSL_API_UNLOCK; 1882 return rv; 1883} 1884 1885/** 1886 * @brief Set status of Atheros header packets parsed on a particular port. 1887 * @param[in] dev_id device id 1888 * @param[in] port_id port id 1889 * @param[in] enable A_TRUE or A_FALSE 1890 * @return SW_OK or error code 1891 */ 1892HSL_LOCAL sw_error_t 1893isisc_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, 1894 fal_port_header_mode_t mode) 1895{ 1896 sw_error_t rv; 1897 1898 HSL_API_LOCK; 1899 rv = _isisc_port_rxhdr_mode_set(dev_id, port_id, mode); 1900 HSL_API_UNLOCK; 1901 return rv; 1902} 1903 1904/** 1905 * @brief Get status of Atheros header packets parsed on a particular port. 1906 * @param[in] dev_id device id 1907 * @param[in] port_id port id 1908 * @param[out] enable A_TRUE or A_FALSE 1909 * @return SW_OK or error code 1910 */ 1911HSL_LOCAL sw_error_t 1912isisc_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, 1913 fal_port_header_mode_t * mode) 1914{ 1915 sw_error_t rv; 1916 1917 HSL_API_LOCK; 1918 rv = _isisc_port_rxhdr_mode_get(dev_id, port_id, mode); 1919 HSL_API_UNLOCK; 1920 return rv; 1921} 1922 1923/** 1924 * @brief Set status of Atheros header packets parsed on a particular port. 1925 * @param[in] dev_id device id 1926 * @param[in] port_id port id 1927 * @param[in] enable A_TRUE or A_FALSE 1928 * @return SW_OK or error code 1929 */ 1930HSL_LOCAL sw_error_t 1931isisc_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, 1932 fal_port_header_mode_t mode) 1933{ 1934 sw_error_t rv; 1935 1936 HSL_API_LOCK; 1937 rv = _isisc_port_txhdr_mode_set(dev_id, port_id, mode); 1938 HSL_API_UNLOCK; 1939 return rv; 1940} 1941 1942/** 1943 * @brief Get status of Atheros header packets parsed on a particular port. 1944 * @param[in] dev_id device id 1945 * @param[in] port_id port id 1946 * @param[out] enable A_TRUE or A_FALSE 1947 * @return SW_OK or error code 1948 */ 1949HSL_LOCAL sw_error_t 1950isisc_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, 1951 fal_port_header_mode_t * mode) 1952{ 1953 sw_error_t rv; 1954 1955 HSL_API_LOCK; 1956 rv = _isisc_port_txhdr_mode_get(dev_id, port_id, mode); 1957 HSL_API_UNLOCK; 1958 return rv; 1959} 1960 1961/** 1962 * @brief Set status of Atheros header type value on a particular device. 1963 * @param[in] dev_id device id 1964 * @param[in] enable A_TRUE or A_FALSE 1965 * @param[in] type header type value 1966 * @return SW_OK or error code 1967 */ 1968HSL_LOCAL sw_error_t 1969isisc_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type) 1970{ 1971 sw_error_t rv; 1972 HSL_API_LOCK; 1973 rv = _isisc_header_type_set(dev_id, enable, type); 1974 HSL_API_UNLOCK; 1975 return rv; 1976} 1977 1978/** 1979 * @brief Get status of Atheros header type value on a particular device. 1980 * @param[in] dev_id device id 1981 * @param[out] enable A_TRUE or A_FALSE 1982 * @param[out] type header type value 1983 * @return SW_OK or error code 1984 */ 1985HSL_LOCAL sw_error_t 1986isisc_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type) 1987{ 1988 sw_error_t rv; 1989 1990 HSL_API_LOCK; 1991 rv = _isisc_header_type_get(dev_id, enable, type); 1992 HSL_API_UNLOCK; 1993 return rv; 1994} 1995 1996/** 1997 * @brief Set status of txmac on a particular port. 1998 * @param[in] dev_id device id 1999 * @param[in] port_id port id 2000 * @param[in] enable A_TRUE or A_FALSE 2001 * @return SW_OK or error code 2002 */ 2003HSL_LOCAL sw_error_t 2004isisc_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 2005{ 2006 sw_error_t rv; 2007 HSL_API_LOCK; 2008 rv = _isisc_port_txmac_status_set(dev_id, port_id, enable); 2009 HSL_API_UNLOCK; 2010 return rv; 2011} 2012 2013/** 2014 * @brief Get status of txmac on a particular port. 2015 * @param[in] dev_id device id 2016 * @param[in] port_id port id 2017 * @param[out] enable A_TRUE or A_FALSE 2018 * @return SW_OK or error code 2019 */ 2020HSL_LOCAL sw_error_t 2021isisc_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) 2022{ 2023 sw_error_t rv; 2024 2025 HSL_API_LOCK; 2026 rv = _isisc_port_txmac_status_get(dev_id, port_id, enable); 2027 HSL_API_UNLOCK; 2028 return rv; 2029} 2030 2031/** 2032 * @brief Set status of rxmac on a particular port. 2033 * @param[in] dev_id device id 2034 * @param[in] port_id port id 2035 * @param[in] enable A_TRUE or A_FALSE 2036 * @return SW_OK or error code 2037 */ 2038HSL_LOCAL sw_error_t 2039isisc_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 2040{ 2041 sw_error_t rv; 2042 HSL_API_LOCK; 2043 rv = _isisc_port_rxmac_status_set(dev_id, port_id, enable); 2044 HSL_API_UNLOCK; 2045 return rv; 2046} 2047 2048/** 2049 * @brief Get status of rxmac on a particular port. 2050 * @param[in] dev_id device id 2051 * @param[in] port_id port id 2052 * @param[out] enable A_TRUE or A_FALSE 2053 * @return SW_OK or error code 2054 */ 2055HSL_LOCAL sw_error_t 2056isisc_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) 2057{ 2058 sw_error_t rv; 2059 2060 HSL_API_LOCK; 2061 rv = _isisc_port_rxmac_status_get(dev_id, port_id, enable); 2062 HSL_API_UNLOCK; 2063 return rv; 2064} 2065 2066/** 2067 * @brief Set status of tx flow control on a particular port. 2068 * @param[in] dev_id device id 2069 * @param[in] port_id port id 2070 * @param[in] enable A_TRUE or A_FALSE 2071 * @return SW_OK or error code 2072 */ 2073HSL_LOCAL sw_error_t 2074isisc_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 2075{ 2076 sw_error_t rv; 2077 HSL_API_LOCK; 2078 rv = _isisc_port_txfc_status_set(dev_id, port_id, enable); 2079 HSL_API_UNLOCK; 2080 return rv; 2081} 2082 2083/** 2084 * @brief Get status of tx flow control on a particular port. 2085 * @param[in] dev_id device id 2086 * @param[in] port_id port id 2087 * @param[out] enable A_TRUE or A_FALSE 2088 * @return SW_OK or error code 2089 */ 2090HSL_LOCAL sw_error_t 2091isisc_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) 2092{ 2093 sw_error_t rv; 2094 2095 HSL_API_LOCK; 2096 rv = _isisc_port_txfc_status_get(dev_id, port_id, enable); 2097 HSL_API_UNLOCK; 2098 return rv; 2099} 2100 2101/** 2102 * @brief Set status of rx flow control on a particular port. 2103 * @param[in] dev_id device id 2104 * @param[in] port_id port id 2105 * @param[in] enable A_TRUE or A_FALSE 2106 * @return SW_OK or error code 2107 */ 2108HSL_LOCAL sw_error_t 2109isisc_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 2110{ 2111 sw_error_t rv; 2112 HSL_API_LOCK; 2113 rv = _isisc_port_rxfc_status_set(dev_id, port_id, enable); 2114 HSL_API_UNLOCK; 2115 return rv; 2116} 2117 2118/** 2119 * @brief Set status of rx flow control on a particular port. 2120 * @param[in] dev_id device id 2121 * @param[in] port_id port id 2122 * @param[out] enable A_TRUE or A_FALSE 2123 * @return SW_OK or error code 2124 */ 2125HSL_LOCAL sw_error_t 2126isisc_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) 2127{ 2128 sw_error_t rv; 2129 2130 HSL_API_LOCK; 2131 rv = _isisc_port_rxfc_status_get(dev_id, port_id, enable); 2132 HSL_API_UNLOCK; 2133 return rv; 2134} 2135 2136/** 2137 * @brief Set status of back pressure on a particular port. 2138 * @param[in] dev_id device id 2139 * @param[in] port_id port id 2140 * @param[in] enable A_TRUE or A_FALSE 2141 * @return SW_OK or error code 2142 */ 2143HSL_LOCAL sw_error_t 2144isisc_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 2145{ 2146 sw_error_t rv; 2147 HSL_API_LOCK; 2148 rv = _isisc_port_bp_status_set(dev_id, port_id, enable); 2149 HSL_API_UNLOCK; 2150 return rv; 2151} 2152 2153/** 2154 * @brief Set status of back pressure on a particular port. 2155 * @param[in] dev_id device id 2156 * @param[in] port_id port id 2157 * @param[out] enable A_TRUE or A_FALSE 2158 * @return SW_OK or error code 2159 */ 2160HSL_LOCAL sw_error_t 2161isisc_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) 2162{ 2163 sw_error_t rv; 2164 2165 HSL_API_LOCK; 2166 rv = _isisc_port_bp_status_get(dev_id, port_id, enable); 2167 HSL_API_UNLOCK; 2168 return rv; 2169} 2170 2171/** 2172 * @brief Set link force mode on a particular port. 2173 * @param[in] dev_id device id 2174 * @param[in] port_id port id 2175 * @param[in] enable A_TRUE or A_FALSE 2176 * @return SW_OK or error code 2177 */ 2178HSL_LOCAL sw_error_t 2179isisc_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 2180{ 2181 sw_error_t rv; 2182 HSL_API_LOCK; 2183 rv = _isisc_port_link_forcemode_set(dev_id, port_id, enable); 2184 HSL_API_UNLOCK; 2185 return rv; 2186} 2187 2188/** 2189 * @brief Get link force mode on a particular port. 2190 * @param[in] dev_id device id 2191 * @param[in] port_id port id 2192 * @param[out] enable A_TRUE or A_FALSE 2193 * @return SW_OK or error code 2194 */ 2195HSL_LOCAL sw_error_t 2196isisc_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) 2197{ 2198 sw_error_t rv; 2199 2200 HSL_API_LOCK; 2201 rv = _isisc_port_link_forcemode_get(dev_id, port_id, enable); 2202 HSL_API_UNLOCK; 2203 return rv; 2204} 2205 2206/** 2207 * @brief Get link status on particular port. 2208 * @param[in] dev_id device id 2209 * @param[in] port_id port id 2210 * @param[out] status link status up (A_TRUE) or down (A_FALSE) 2211 * @return SW_OK or error code 2212 */ 2213HSL_LOCAL sw_error_t 2214isisc_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status) 2215{ 2216 sw_error_t rv; 2217 2218 HSL_API_LOCK; 2219 rv = _isisc_port_link_status_get(dev_id, port_id, status); 2220 HSL_API_UNLOCK; 2221 return rv; 2222} 2223 2224/** 2225 * @brief Get link status on all ports. 2226 * @param[in] dev_id device id 2227 * @param[out] status link status bitmap and bit 0 for port 0, bi 1 for port 1, ..., etc. 2228 * @return SW_OK or error code 2229 */ 2230HSL_LOCAL sw_error_t 2231isisc_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status) 2232{ 2233 sw_error_t rv; 2234 2235 HSL_API_LOCK; 2236 rv = _isisc_ports_link_status_get(dev_id, status); 2237 HSL_API_UNLOCK; 2238 return rv; 2239} 2240 2241/** 2242 * @brief Set mac loop back on a particular port. 2243 * @param[in] dev_id device id 2244 * @param[in] port_id port id 2245 * @param[in] enable A_TRUE or A_FALSE 2246 * @return SW_OK or error code 2247 */ 2248HSL_LOCAL sw_error_t 2249isisc_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 2250{ 2251 sw_error_t rv; 2252 HSL_API_LOCK; 2253 rv = _isisc_port_mac_loopback_set(dev_id, port_id, enable); 2254 HSL_API_UNLOCK; 2255 return rv; 2256} 2257 2258/** 2259 * @brief Get mac loop back on a particular port. 2260 * @param[in] dev_id device id 2261 * @param[in] port_id port id 2262 * @param[out] enable A_TRUE or A_FALSE 2263 * @return SW_OK or error code 2264 */ 2265HSL_LOCAL sw_error_t 2266isisc_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) 2267{ 2268 sw_error_t rv; 2269 2270 HSL_API_LOCK; 2271 rv = _isisc_port_mac_loopback_get(dev_id, port_id, enable); 2272 HSL_API_UNLOCK; 2273 return rv; 2274} 2275 2276sw_error_t 2277isisc_port_ctrl_init(a_uint32_t dev_id) 2278{ 2279 HSL_DEV_ID_CHECK(dev_id); 2280 2281#ifndef HSL_STANDALONG 2282 { 2283 hsl_api_t *p_api; 2284 2285 SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); 2286 2287 p_api->port_duplex_get = isisc_port_duplex_get; 2288 p_api->port_duplex_set = isisc_port_duplex_set; 2289 p_api->port_speed_get = isisc_port_speed_get; 2290 p_api->port_speed_set = isisc_port_speed_set; 2291 p_api->port_autoneg_status_get = isisc_port_autoneg_status_get; 2292 p_api->port_autoneg_enable = isisc_port_autoneg_enable; 2293 p_api->port_autoneg_restart = isisc_port_autoneg_restart; 2294 p_api->port_autoneg_adv_get = isisc_port_autoneg_adv_get; 2295 p_api->port_autoneg_adv_set = isisc_port_autoneg_adv_set; 2296 p_api->port_flowctrl_set = isisc_port_flowctrl_set; 2297 p_api->port_flowctrl_get = isisc_port_flowctrl_get; 2298 p_api->port_flowctrl_forcemode_set = isisc_port_flowctrl_forcemode_set; 2299 p_api->port_flowctrl_forcemode_get = isisc_port_flowctrl_forcemode_get; 2300 p_api->port_powersave_set = isisc_port_powersave_set; 2301 p_api->port_powersave_get = isisc_port_powersave_get; 2302 p_api->port_hibernate_set = isisc_port_hibernate_set; 2303 p_api->port_hibernate_get = isisc_port_hibernate_get; 2304 p_api->port_cdt = isisc_port_cdt; 2305 p_api->port_rxhdr_mode_set = isisc_port_rxhdr_mode_set; 2306 p_api->port_rxhdr_mode_get = isisc_port_rxhdr_mode_get; 2307 p_api->port_txhdr_mode_set = isisc_port_txhdr_mode_set; 2308 p_api->port_txhdr_mode_get = isisc_port_txhdr_mode_get; 2309 p_api->header_type_set = isisc_header_type_set; 2310 p_api->header_type_get = isisc_header_type_get; 2311 p_api->port_txmac_status_set = isisc_port_txmac_status_set; 2312 p_api->port_txmac_status_get = isisc_port_txmac_status_get; 2313 p_api->port_rxmac_status_set = isisc_port_rxmac_status_set; 2314 p_api->port_rxmac_status_get = isisc_port_rxmac_status_get; 2315 p_api->port_txfc_status_set = isisc_port_txfc_status_set; 2316 p_api->port_txfc_status_get = isisc_port_txfc_status_get; 2317 p_api->port_rxfc_status_set = isisc_port_rxfc_status_set; 2318 p_api->port_rxfc_status_get = isisc_port_rxfc_status_get; 2319 p_api->port_bp_status_set = isisc_port_bp_status_set; 2320 p_api->port_bp_status_get = isisc_port_bp_status_get; 2321 p_api->port_link_forcemode_set = isisc_port_link_forcemode_set; 2322 p_api->port_link_forcemode_get = isisc_port_link_forcemode_get; 2323 p_api->port_link_status_get = isisc_port_link_status_get; 2324 p_api->ports_link_status_get = isisc_ports_link_status_get; 2325 p_api->port_mac_loopback_set=isisc_port_mac_loopback_set; 2326 p_api->port_mac_loopback_get=isisc_port_mac_loopback_get; 2327 } 2328#endif 2329 2330 return SW_OK; 2331} 2332 2333/** 2334 * @} 2335 */ 2336 2337