1/* 2 * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved. 3 * Permission to use, copy, modify, and/or distribute this software for 4 * any purpose with or without fee is hereby granted, provided that the 5 * above copyright notice and this permission notice appear in all copies. 6 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 7 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 8 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 9 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 10 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 11 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 12 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 13 */ 14 15 16 17#ifndef _F1_PHY_H_ 18#define _F1_PHY_H_ 19 20#ifdef __cplusplus 21extern "C" { 22#endif /* __cplusplus */ 23 24 /* PHY Registers */ 25#define F1_PHY_CONTROL 0 26#define F1_PHY_STATUS 1 27#define F1_PHY_ID1 2 28#define F1_PHY_ID2 3 29#define F1_AUTONEG_ADVERT 4 30#define F1_LINK_PARTNER_ABILITY 5 31#define F1_AUTONEG_EXPANSION 6 32#define F1_NEXT_PAGE_TRANSMIT 7 33#define F1_LINK_PARTNER_NEXT_PAGE 8 34#define F1_1000BASET_CONTROL 9 35#define F1_1000BASET_STATUS 10 36#define F1_MMD_CTRL_REG 13 37#define F1_MMD_DATA_REG 14 38#define F1_EXTENDED_STATUS 15 39#define F1_PHY_SPEC_CONTROL 16 40#define F1_PHY_SPEC_STATUS 17 41#define F1_PHY_INTR_MASK 18 42#define F1_PHY_INTR_STATUS 19 43#define F1_PHY_CDT_CONTROL 22 44#define F1_PHY_CDT_STATUS 28 45#define F1_DEBUG_PORT_ADDRESS 29 46#define F1_DEBUG_PORT_DATA 30 47 48 49 /*debug port*/ 50#define F1_DEBUG_PORT_RGMII_MODE 18 51#define F1_DEBUG_PORT_RGMII_MODE_EN 0x0008 52 53#define F1_DEBUG_PORT_RX_DELAY 0 54#define F1_DEBUG_PORT_RX_DELAY_EN 0x8000 55 56#define F1_DEBUG_PORT_TX_DELAY 5 57#define F1_DEBUG_PORT_TX_DELAY_EN 0x0100 58 59 /* PHY Registers Field*/ 60 61 /* Control Register fields offset:0*/ 62 /* bits 6,13: 10=1000, 01=100, 00=10 */ 63#define F1_CTRL_SPEED_MSB 0x0040 64 65 /* Collision test enable */ 66#define F1_CTRL_COLL_TEST_ENABLE 0x0080 67 68 /* FDX =1, half duplex =0 */ 69#define F1_CTRL_FULL_DUPLEX 0x0100 70 71 /* Restart auto negotiation */ 72#define F1_CTRL_RESTART_AUTONEGOTIATION 0x0200 73 74 /* Isolate PHY from MII */ 75#define F1_CTRL_ISOLATE 0x0400 76 77 /* Power down */ 78#define F1_CTRL_POWER_DOWN 0x0800 79 80 /* Auto Neg Enable */ 81#define F1_CTRL_AUTONEGOTIATION_ENABLE 0x1000 82 83 /* bits 6,13: 10=1000, 01=100, 00=10 */ 84#define F1_CTRL_SPEED_LSB 0x2000 85 86 /* 0 = normal, 1 = loopback */ 87#define F1_CTRL_LOOPBACK 0x4000 88#define F1_CTRL_SOFTWARE_RESET 0x8000 89 90#define F1_CTRL_SPEED_MASK 0x2040 91#define F1_CTRL_SPEED_1000 0x0040 92#define F1_CTRL_SPEED_100 0x2000 93#define F1_CTRL_SPEED_10 0x0000 94 95#define F1_RESET_DONE(phy_control) \ 96 (((phy_control) & (F1_CTRL_SOFTWARE_RESET)) == 0) 97 98 /* Status Register fields offset:1*/ 99 /* Extended register capabilities */ 100#define F1_STATUS_EXTENDED_CAPS 0x0001 101 102 /* Jabber Detected */ 103#define F1_STATUS_JABBER_DETECT 0x0002 104 105 /* Link Status 1 = link */ 106#define F1_STATUS_LINK_STATUS_UP 0x0004 107 108 /* Auto Neg Capable */ 109#define F1_STATUS_AUTONEG_CAPS 0x0008 110 111 /* Remote Fault Detect */ 112#define F1_STATUS_REMOTE_FAULT 0x0010 113 114 /* Auto Neg Complete */ 115#define F1_STATUS_AUTO_NEG_DONE 0x0020 116 117 /* Preamble may be suppressed */ 118#define F1_STATUS_PREAMBLE_SUPPRESS 0x0040 119 120 /* Ext. status info in Reg 0x0F */ 121#define F1_STATUS_EXTENDED_STATUS 0x0100 122 123 /* 100T2 Half Duplex Capable */ 124#define F1_STATUS_100T2_HD_CAPS 0x0200 125 126 /* 100T2 Full Duplex Capable */ 127#define F1_STATUS_100T2_FD_CAPS 0x0400 128 129 /* 10T Half Duplex Capable */ 130#define F1_STATUS_10T_HD_CAPS 0x0800 131 132 /* 10T Full Duplex Capable */ 133#define F1_STATUS_10T_FD_CAPS 0x1000 134 135 /* 100X Half Duplex Capable */ 136#define F1_STATUS_100X_HD_CAPS 0x2000 137 138 /* 100X Full Duplex Capable */ 139#define F1_STATUS_100X_FD_CAPS 0x4000 140 141 /* 100T4 Capable */ 142#define F1_STATUS_100T4_CAPS 0x8000 143 144 /* extended status register capabilities */ 145 146#define F1_STATUS_1000T_HD_CAPS 0x1000 147 148#define F1_STATUS_1000T_FD_CAPS 0x2000 149 150#define F1_STATUS_1000X_HD_CAPS 0x4000 151 152#define F1_STATUS_1000X_FD_CAPS 0x8000 153 154#define F1_AUTONEG_DONE(ip_phy_status) \ 155 (((ip_phy_status) & (F1_STATUS_AUTO_NEG_DONE)) == \ 156 (F1_STATUS_AUTO_NEG_DONE)) 157 158 /* PHY identifier1 offset:2*/ 159//Organizationally Unique Identifier bits 3:18 160 161 /* PHY identifier2 offset:3*/ 162//Organizationally Unique Identifier bits 19:24 163 164 /* Auto-Negotiation Advertisement register. offset:4*/ 165 /* indicates IEEE 802.3 CSMA/CD */ 166#define F1_ADVERTISE_SELECTOR_FIELD 0x0001 167 168 /* 10T Half Duplex Capable */ 169#define F1_ADVERTISE_10HALF 0x0020 170 171 /* 10T Full Duplex Capable */ 172#define F1_ADVERTISE_10FULL 0x0040 173 174 /* 100TX Half Duplex Capable */ 175#define F1_ADVERTISE_100HALF 0x0080 176 177 /* 100TX Full Duplex Capable */ 178#define F1_ADVERTISE_100FULL 0x0100 179 180 /* 100T4 Capable */ 181#define F1_ADVERTISE_100T4 0x0200 182 183 /* Pause operation desired */ 184#define F1_ADVERTISE_PAUSE 0x0400 185 186 /* Asymmetric Pause Direction bit */ 187#define F1_ADVERTISE_ASYM_PAUSE 0x0800 188 189 /* Remote Fault detected */ 190#define F1_ADVERTISE_REMOTE_FAULT 0x2000 191 192 /* Next Page ability supported */ 193#define F1_ADVERTISE_NEXT_PAGE 0x8000 194 195 /* 100TX Half Duplex Capable */ 196#define F1_ADVERTISE_1000HALF 0x0100 197 198 /* 100TX Full Duplex Capable */ 199#define F1_ADVERTISE_1000FULL 0x0200 200 201#define F1_ADVERTISE_ALL \ 202 (F1_ADVERTISE_10HALF | F1_ADVERTISE_10FULL | \ 203 F1_ADVERTISE_100HALF | F1_ADVERTISE_100FULL | \ 204 F1_ADVERTISE_1000FULL) 205 206#define F1_ADVERTISE_MEGA_ALL \ 207 (F1_ADVERTISE_10HALF | F1_ADVERTISE_10FULL | \ 208 F1_ADVERTISE_100HALF | F1_ADVERTISE_100FULL) 209 210 /* Link Partner ability offset:5*/ 211 /* Same as advertise selector */ 212#define F1_LINK_SLCT 0x001f 213 214 /* Can do 10mbps half-duplex */ 215#define F1_LINK_10BASETX_HALF_DUPLEX 0x0020 216 217 /* Can do 10mbps full-duplex */ 218#define F1_LINK_10BASETX_FULL_DUPLEX 0x0040 219 220 /* Can do 100mbps half-duplex */ 221#define F1_LINK_100BASETX_HALF_DUPLEX 0x0080 222 223 /* Can do 100mbps full-duplex */ 224#define F1_LINK_100BASETX_FULL_DUPLEX 0x0100 225 226 /* Can do 1000mbps full-duplex */ 227#define F1_LINK_1000BASETX_FULL_DUPLEX 0x0800 228 229 /* Can do 1000mbps half-duplex */ 230#define F1_LINK_1000BASETX_HALF_DUPLEX 0x0400 231 232 /* 100BASE-T4 */ 233#define F1_LINK_100BASE4 0x0200 234 235 /* PAUSE */ 236#define F1_LINK_PAUSE 0x0400 237 238 /* Asymmetrical PAUSE */ 239#define F1_LINK_ASYPAUSE 0x0800 240 241 /* Link partner faulted */ 242#define F1_LINK_RFAULT 0x2000 243 244 /* Link partner acked us */ 245#define F1_LINK_LPACK 0x4000 246 247 /* Next page bit */ 248#define F1_LINK_NPAGE 0x8000 249 250 /* Auto-Negotiation Expansion Register offset:6 */ 251 252 /* Next Page Transmit Register offset:7 */ 253 254 /* Link partner Next Page Register offset:8*/ 255 256 /* 1000BASE-T Control Register offset:9*/ 257 /* Advertise 1000T HD capability */ 258#define F1_CTL_1000T_HD_CAPS 0x0100 259 260 /* Advertise 1000T FD capability */ 261#define F1_CTL_1000T_FD_CAPS 0x0200 262 263 /* 1=Repeater/switch device port 0=DTE device*/ 264#define F1_CTL_1000T_REPEATER_DTE 0x0400 265 266 /* 1=Configure PHY as Master 0=Configure PHY as Slave */ 267#define F1_CTL_1000T_MS_VALUE 0x0800 268 269 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ 270#define F1_CTL_1000T_MS_ENABLE 0x1000 271 272 /* Normal Operation */ 273#define F1_CTL_1000T_TEST_MODE_NORMAL 0x0000 274 275 /* Transmit Waveform test */ 276#define F1_CTL_1000T_TEST_MODE_1 0x2000 277 278 /* Master Transmit Jitter test */ 279#define F1_CTL_1000T_TEST_MODE_2 0x4000 280 281 /* Slave Transmit Jitter test */ 282#define F1_CTL_1000T_TEST_MODE_3 0x6000 283 284 /* Transmitter Distortion test */ 285#define F1_CTL_1000T_TEST_MODE_4 0x8000 286#define F1_CTL_1000T_SPEED_MASK 0x0300 287#define F1_CTL_1000T_DEFAULT_CAP_MASK 0x0300 288 289 /* 1000BASE-T Status Register offset:10 */ 290 /* LP is 1000T HD capable */ 291#define F1_STATUS_1000T_LP_HD_CAPS 0x0400 292 293 /* LP is 1000T FD capable */ 294#define F1_STATUS_1000T_LP_FD_CAPS 0x0800 295 296 /* Remote receiver OK */ 297#define F1_STATUS_1000T_REMOTE_RX_STATUS 0x1000 298 299 /* Local receiver OK */ 300#define F1_STATUS_1000T_LOCAL_RX_STATUS 0x2000 301 302 /* 1=Local TX is Master, 0=Slave */ 303#define F1_STATUS_1000T_MS_CONFIG_RES 0x4000 304 305#define F1_STATUS_1000T_MS_CONFIG_FAULT 0x8000 306 307 /* Master/Slave config fault */ 308#define F1_STATUS_1000T_REMOTE_RX_STATUS_SHIFT 12 309#define F1_STATUS_1000T_LOCAL_RX_STATUS_SHIFT 13 310 311 /* Phy Specific Control Register offset:16*/ 312 /* 1=Jabber Function disabled */ 313#define F1_CTL_JABBER_DISABLE 0x0001 314 315 /* 1=Polarity Reversal enabled */ 316#define F1_CTL_POLARITY_REVERSAL 0x0002 317 318 /* 1=SQE Test enabled */ 319#define F1_CTL_SQE_TEST 0x0004 320#define F1_CTL_MAC_POWERDOWN 0x0008 321 322 /* 1=CLK125 low, 0=CLK125 toggling 323 #define F1_CTL_CLK125_DISABLE 0x0010 324 */ 325 /* MDI Crossover Mode bits 6:5 */ 326 /* Manual MDI configuration */ 327#define F1_CTL_MDI_MANUAL_MODE 0x0000 328 329 /* Manual MDIX configuration */ 330#define F1_CTL_MDIX_MANUAL_MODE 0x0020 331 332 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 333#define F1_CTL_AUTO_X_1000T 0x0040 334 335 /* Auto crossover enabled all speeds */ 336#define F1_CTL_AUTO_X_MODE 0x0060 337 338 /* 1=Enable Extended 10BASE-T distance 339 * (Lower 10BASE-T RX Threshold) 340 * 0=Normal 10BASE-T RX Threshold */ 341#define F1_CTL_10BT_EXT_DIST_ENABLE 0x0080 342 343 /* 1=5-Bit interface in 100BASE-TX 344 * 0=MII interface in 100BASE-TX */ 345#define F1_CTL_MII_5BIT_ENABLE 0x0100 346 347 /* 1=Scrambler disable */ 348#define F1_CTL_SCRAMBLER_DISABLE 0x0200 349 350 /* 1=Force link good */ 351#define F1_CTL_FORCE_LINK_GOOD 0x0400 352 353 /* 1=Assert CRS on Transmit */ 354#define F1_CTL_ASSERT_CRS_ON_TX 0x0800 355 356#define F1_CTL_POLARITY_REVERSAL_SHIFT 1 357#define F1_CTL_AUTO_X_MODE_SHIFT 5 358#define F1_CTL_10BT_EXT_DIST_ENABLE_SHIFT 7 359 360 /* Phy Specific status fields offset:17*/ 361 /* 1=Speed & Duplex resolved */ 362#define F1_STATUS_LINK_PASS 0x0400 363#define F1_STATUS_RESOVLED 0x0800 364 365 /* 1=Duplex 0=Half Duplex */ 366#define F1_STATUS_FULL_DUPLEX 0x2000 367 368 /* Speed, bits 14:15 */ 369#define F1_STATUS_SPEED 0xC000 370#define F1_STATUS_SPEED_MASK 0xC000 371 372 /* 00=10Mbs */ 373#define F1_STATUS_SPEED_10MBS 0x0000 374 375 /* 01=100Mbs */ 376#define F1_STATUS_SPEED_100MBS 0x4000 377 378 /* 10=1000Mbs */ 379#define F1_STATUS_SPEED_1000MBS 0x8000 380#define F1_SPEED_DUPLEX_RESOVLED(phy_status) \ 381 (((phy_status) & \ 382 (F1_STATUS_RESOVLED)) == \ 383 (F1_STATUS_RESOVLED)) 384 385 /*phy debug port1 register offset:29*/ 386 /*phy debug port2 register offset:30*/ 387 388 /*F1 interrupt flag */ 389#define F1_INTR_SPEED_CHANGE 0x4000 390#define F1_INTR_DUPLEX_CHANGE 0x2000 391#define F1_INTR_STATUS_UP_CHANGE 0x0400 392#define F1_INTR_STATUS_DOWN_CHANGE 0x0800 393 394 sw_error_t 395 f1_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable); 396 397 sw_error_t 398 f1_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable); 399 400 sw_error_t 401 f1_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable); 402 403 sw_error_t 404 f1_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable); 405 406 sw_error_t 407 f1_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair, 408 fal_cable_status_t *cable_status, a_uint32_t *cable_len) ; 409 410 sw_error_t 411 f1_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id, 412 fal_port_duplex_t duplex); 413 414 sw_error_t 415 f1_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id, 416 fal_port_duplex_t * duplex); 417 418 sw_error_t 419 f1_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id, 420 fal_port_speed_t speed); 421 422 sw_error_t 423 f1_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id, 424 fal_port_speed_t * speed); 425 426 sw_error_t 427 f1_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id); 428 429 sw_error_t 430 f1_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id); 431 432 a_bool_t 433 f1_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id); 434 435 sw_error_t 436 f1_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, 437 a_uint32_t autoneg); 438 439 sw_error_t 440 f1_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, 441 a_uint32_t * autoneg); 442 443 a_bool_t f1_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id); 444 445 sw_error_t 446 f1_phy_intr_mask_set(a_uint32_t dev_id, a_uint32_t phy_id, 447 a_uint32_t intr_mask_flag); 448 449 sw_error_t 450 f1_phy_intr_mask_get(a_uint32_t dev_id, a_uint32_t phy_id, 451 a_uint32_t * intr_mask_flag); 452 453 sw_error_t 454 f1_phy_intr_status_get(a_uint32_t dev_id, a_uint32_t phy_id, 455 a_uint32_t * intr_status_flag); 456 457 int f1_phy_init(void); 458 459#ifdef __cplusplus 460} 461#endif /* __cplusplus */ 462#endif /* _F1_PHY_H_ */ 463