1/* 2 * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved. 3 * Permission to use, copy, modify, and/or distribute this software for 4 * any purpose with or without fee is hereby granted, provided that the 5 * above copyright notice and this permission notice appear in all copies. 6 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 7 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 8 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 9 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 10 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 11 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 12 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 13 */ 14 15/** 16 * @defgroup fal_port_ctrl FAL_PORT_CONTROL 17 * @{ 18 */ 19#ifndef _FAL_PORTCTRL_H_ 20#define _FAL_PORTCTRL_H_ 21 22#ifdef __cplusplus 23extern "c" { 24#endif 25 26#include "common/sw.h" 27#include "fal/fal_type.h" 28 29 typedef enum { 30 FAL_HALF_DUPLEX = 0, 31 FAL_FULL_DUPLEX, 32 FAL_DUPLEX_BUTT = 0xffff 33 } fal_port_duplex_t; 34 35 typedef enum { 36 FAL_SPEED_10 = 10, 37 FAL_SPEED_100 = 100, 38 FAL_SPEED_1000 = 1000, 39 FAL_SPEED_10000 = 10000, 40 FAL_SPEED_BUTT = 0xffff, 41 } fal_port_speed_t; 42 43 typedef enum { 44 FAL_CABLE_STATUS_NORMAL = 0, 45 FAL_CABLE_STATUS_SHORT = 1, 46 FAL_CABLE_STATUS_OPENED = 2, 47 FAL_CABLE_STATUS_INVALID = 3, 48 FAL_CABLE_STATUS_BUTT = 0xffff, 49 } fal_cable_status_t; 50 51#define FAL_ENABLE 1 52#define FAL_DISABLE 0 53 54//phy autoneg adv 55#define FAL_PHY_ADV_10T_HD 0x01 56#define FAL_PHY_ADV_10T_FD 0x02 57#define FAL_PHY_ADV_100TX_HD 0x04 58#define FAL_PHY_ADV_100TX_FD 0x08 59//#define FAL_PHY_ADV_1000T_HD 0x100 60#define FAL_PHY_ADV_1000T_FD 0x200 61#define FAL_PHY_ADV_1000BX_HD 0x400 62#define FAL_PHY_ADV_1000BX_FD 0x800 63 64#define FAL_PHY_ADV_FE_SPEED_ALL \ 65 (FAL_PHY_ADV_10T_HD | FAL_PHY_ADV_10T_FD | FAL_PHY_ADV_100TX_HD |\ 66 FAL_PHY_ADV_100TX_FD) 67 68#define FAL_PHY_ADV_GE_SPEED_ALL \ 69 (FAL_PHY_ADV_10T_HD | FAL_PHY_ADV_10T_FD | FAL_PHY_ADV_100TX_HD |\ 70 FAL_PHY_ADV_100TX_FD | FAL_PHY_ADV_1000T_FD) 71 72#define FAL_PHY_ADV_BX_SPEED_ALL \ 73 (FAL_PHY_ADV_1000BX_HD | FAL_PHY_ADV_1000BX_FD) 74 75#define FAL_PHY_ADV_PAUSE 0x10 76#define FAL_PHY_ADV_ASY_PAUSE 0x20 77#define FAL_PHY_FE_ADV_ALL \ 78 (FAL_PHY_ADV_FE_SPEED_ALL | FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE) 79#define FAL_PHY_GE_ADV_ALL \ 80 (FAL_PHY_ADV_GE_SPEED_ALL | FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE) 81 82#define FAL_PHY_COMBO_ADV_ALL \ 83 (FAL_PHY_ADV_BX_SPEED_ALL | FAL_PHY_ADV_GE_SPEED_ALL | FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE) 84 85//phy capablity 86#define FAL_PHY_AUTONEG_CAPS 0x01 87#define FAL_PHY_100T2_HD_CAPS 0x02 88#define FAL_PHY_100T2_FD_CAPS 0x04 89#define FAL_PHY_10T_HD_CAPS 0x08 90#define FAL_PHY_10T_FD_CAPS 0x10 91#define FAL_PHY_100X_HD_CAPS 0x20 92#define FAL_PHY_100X_FD_CAPS 0x40 93#define FAL_PHY_100T4_CAPS 0x80 94//#define FAL_PHY_1000T_HD_CAPS 0x100 95#define FAL_PHY_1000T_FD_CAPS 0x200 96//#define FAL_PHY_1000X_HD_CAPS 0x400 97#define FAL_PHY_1000X_FD_CAPS 0x800 98 99//phy partner capablity 100#define FAL_PHY_PART_10T_HD 0x1 101#define FAL_PHY_PART_10T_FD 0x2 102#define FAL_PHY_PART_100TX_HD 0x4 103#define FAL_PHY_PART_100TX_FD 0x8 104//#define FAL_PHY_PART_1000T_HD 0x10 105#define FAL_PHY_PART_1000T_FD 0x20 106 107//phy interrupt flag 108#define FAL_PHY_INTR_SPEED_CHANGE 0x1 109#define FAL_PHY_INTR_DUPLEX_CHANGE 0x2 110#define FAL_PHY_INTR_STATUS_UP_CHANGE 0x4 111#define FAL_PHY_INTR_STATUS_DOWN_CHANGE 0x8 112#define FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE 0x10 113#define FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE 0x20 114#define FAL_PHY_INTR_MEDIA_STATUS_CHANGE 0x40 115#define FAL_PHY_INTR_WOL_STATUS 0x80 116#define FAL_PHY_INTR_POE_STATUS 0x100 117 118 typedef enum { 119 FAL_NO_HEADER_EN = 0, 120 FAL_ONLY_MANAGE_FRAME_EN, 121 FAL_ALL_TYPE_FRAME_EN 122 } fal_port_header_mode_t; 123 124 typedef struct { 125 a_uint16_t pair_a_status; 126 a_uint16_t pair_b_status; 127 a_uint16_t pair_c_status; 128 a_uint16_t pair_d_status; 129 a_uint32_t pair_a_len; 130 a_uint32_t pair_b_len; 131 a_uint32_t pair_c_len; 132 a_uint32_t pair_d_len; 133 } fal_port_cdt_t; 134 135/*below is new add for malibu phy*/ 136 137/** Phy mdix mode */ 138 typedef enum { 139 PHY_MDIX_AUTO = 0, 140 /**< Auto MDI/MDIX */ 141 PHY_MDIX_MDI = 1, 142 /**< Fixed MDI */ 143 PHY_MDIX_MDIX = 2 144 /**< Fixed MDIX */ 145 } fal_port_mdix_mode_t; 146 147/** Phy mdix status */ 148 typedef enum { 149 PHY_MDIX_STATUS_MDI = 0, 150 /**< Fixed MDI */ 151 PHY_MDIX_STATUS_MDIX = 1 152 /**< Fixed MDIX */ 153 } fal_port_mdix_status_t; 154 155/** Phy master mode */ 156 typedef enum { 157 PHY_MASTER_MASTER = 0, 158 /**< Phy manual MASTER configuration */ 159 PHY_MASTER_SLAVE = 1, 160 /**< Phy manual SLAVE configuration */ 161 PHY_MASTER_AUTO = 2 162 /**< Phy automatic MASTER/SLAVE configuration */ 163 } fal_port_master_t; 164 165/** Phy preferred medium type */ 166 typedef enum { 167 PHY_MEDIUM_COPPER = 0, 168 /**< Copper */ 169 PHY_MEDIUM_FIBER = 1, 170 /**< Fiber */ 171 172 } fal_port_medium_t; 173 174/** Phy pages */ 175 typedef enum { 176 PHY_SGBX_PAGES = 0, 177 /**< sgbx pages */ 178 PHY_COPPER_PAGES = 1 179 /**< copper pages */ 180 } fal_port_reg_pages_t; 181 182/** Phy preferred Fiber mode */ 183 typedef enum { 184 PHY_FIBER_100FX = 0, 185 /**< 100FX fiber mode */ 186 PHY_FIBER_1000BX = 1, 187 /**< 1000BX fiber mode */ 188 189 } fal_port_fiber_mode_t; 190 191/** Phy reset status */ 192 typedef enum { 193 PHY_RESET_DONE = 0, 194 /**< Phy reset done */ 195 PHY_RESET_BUSY = 1 196 /**< Phy still in reset process */ 197 } fal_port_reset_status_t; 198 199/** Phy auto-negotiation status */ 200 typedef enum { 201 PHY_AUTO_NEG_STATUS_BUSY = 0, 202 /**< Phy still in auto-negotiation process */ 203 PHY_AUTO_NEG_STATUS_DONE = 1 204 /**< Phy auto-negotiation done */ 205 } fal_port_auto_neg_status_t; 206 207 208/** Phy interface mode */ 209 typedef enum { 210 PHY_PSGMII_BASET = 0, 211 /**< PSGMII mode */ 212 PHY_PSGMII_BX1000 = 1, 213 /**< PSGMII BX1000 mode */ 214 PHY_PSGMII_FX100 = 2, 215 /**< PSGMII FX100 mode */ 216 PHY_PSGMII_AMDET = 3, 217 /**< PSGMII Auto mode */ 218 PHY_SGMII_BASET = 4, 219 /**< SGMII mode */ 220 } fal_port_interface_mode_t; 221 222/** Phy counter information */ 223typedef struct { 224 a_uint32_t RxGoodFrame; 225 a_uint32_t RxBadCRC; 226 a_uint32_t TxGoodFrame; 227 a_uint32_t TxBadCRC; 228} fal_port_counter_info_t; 229 230/*above is new add for malibu phy*/ 231 232 sw_error_t 233 fal_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, 234 fal_port_duplex_t duplex); 235 236 sw_error_t 237 fal_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, 238 fal_port_duplex_t * pduplex); 239 240 sw_error_t 241 fal_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, 242 fal_port_speed_t speed); 243 244 sw_error_t 245 fal_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, 246 fal_port_speed_t * pspeed); 247 248 sw_error_t 249 fal_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, 250 a_bool_t * status); 251 252 sw_error_t 253 fal_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id); 254 255 sw_error_t 256 fal_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id); 257 258 sw_error_t 259 fal_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, 260 a_uint32_t autoadv); 261 262 sw_error_t 263 fal_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, 264 a_uint32_t * autoadv); 265 266 sw_error_t 267 fal_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id, 268 a_bool_t enable); 269 270 sw_error_t 271 fal_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id, 272 a_bool_t * enable); 273 274 sw_error_t 275 fal_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, 276 a_bool_t enable); 277 278 sw_error_t 279 fal_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, 280 a_bool_t * enable); 281 282 sw_error_t 283 fal_port_flowctrl_forcemode_set(a_uint32_t dev_id, 284 fal_port_t port_id, 285 a_bool_t enable); 286 287 sw_error_t 288 fal_port_flowctrl_forcemode_get(a_uint32_t dev_id, 289 fal_port_t port_id, 290 a_bool_t * enable); 291 292 sw_error_t 293 fal_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, 294 a_bool_t enable); 295 296 sw_error_t 297 fal_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, 298 a_bool_t * enable); 299 300 sw_error_t 301 fal_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, 302 a_bool_t enable); 303 304 sw_error_t 305 fal_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, 306 a_bool_t * enable); 307 308 sw_error_t 309 fal_port_cdt(a_uint32_t dev_id, fal_port_t port_id, 310 a_uint32_t mdi_pair, fal_cable_status_t * cable_status, 311 a_uint32_t * cable_len); 312 313 sw_error_t 314 fal_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, 315 fal_port_header_mode_t mode); 316 317 sw_error_t 318 fal_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, 319 fal_port_header_mode_t * mode); 320 321 sw_error_t 322 fal_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, 323 fal_port_header_mode_t mode); 324 325 sw_error_t 326 fal_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, 327 fal_port_header_mode_t * mode); 328 329 sw_error_t 330 fal_header_type_set(a_uint32_t dev_id, a_bool_t enable, 331 a_uint32_t type); 332 333 sw_error_t 334 fal_header_type_get(a_uint32_t dev_id, a_bool_t * enable, 335 a_uint32_t * type); 336 337 sw_error_t 338 fal_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, 339 a_bool_t enable); 340 341 sw_error_t 342 fal_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, 343 a_bool_t * enable); 344 345 sw_error_t 346 fal_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, 347 a_bool_t enable); 348 349 sw_error_t 350 fal_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, 351 a_bool_t * enable); 352 353 sw_error_t 354 fal_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, 355 a_bool_t enable); 356 357 sw_error_t 358 fal_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, 359 a_bool_t * enable); 360 361 sw_error_t 362 fal_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, 363 a_bool_t enable); 364 365 sw_error_t 366 fal_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, 367 a_bool_t * enable); 368 369 sw_error_t 370 fal_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, 371 a_bool_t enable); 372 373 sw_error_t 374 fal_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, 375 a_bool_t * enable); 376 377 sw_error_t 378 fal_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, 379 a_bool_t enable); 380 381 sw_error_t 382 fal_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, 383 a_bool_t * enable); 384 385 sw_error_t 386 fal_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, 387 a_bool_t * status); 388 389 sw_error_t 390 fal_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status); 391 392 sw_error_t 393 fal_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, 394 a_bool_t enable); 395 396 sw_error_t 397 fal_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, 398 a_bool_t * enable); 399 400 sw_error_t 401 fal_port_congestion_drop_set(a_uint32_t dev_id, fal_port_t port_id, 402 a_uint32_t queue_id, a_bool_t enable); 403 404 sw_error_t 405 fal_port_congestion_drop_get(a_uint32_t dev_id, fal_port_t port_id, 406 a_uint32_t queue_id, 407 a_bool_t * enable); 408 409 sw_error_t 410 fal_ring_flow_ctrl_thres_set(a_uint32_t dev_id, a_uint32_t ring_id, 411 a_uint8_t on_thres, 412 a_uint8_t off_thres); 413 414 sw_error_t 415 fal_ring_flow_ctrl_thres_get(a_uint32_t dev_id, a_uint32_t ring_id, 416 a_uint8_t * on_thres, 417 a_uint8_t * off_thres); 418 419 sw_error_t 420 fal_port_8023az_set(a_uint32_t dev_id, fal_port_t port_id, 421 a_bool_t enable); 422 423 sw_error_t 424 fal_port_8023az_get(a_uint32_t dev_id, fal_port_t port_id, 425 a_bool_t * enable); 426 427 sw_error_t 428 fal_port_mdix_set(a_uint32_t dev_id, fal_port_t port_id, 429 fal_port_mdix_mode_t mode); 430 sw_error_t 431 fal_port_mdix_get(a_uint32_t dev_id, fal_port_t port_id, 432 fal_port_mdix_mode_t * mode); 433 sw_error_t 434 fal_port_mdix_status_get(a_uint32_t dev_id, fal_port_t port_id, 435 fal_port_mdix_status_t * mode); 436 sw_error_t 437 fal_port_combo_prefer_medium_set(a_uint32_t dev_id, 438 a_uint32_t port_id, 439 fal_port_medium_t medium); 440 sw_error_t fal_port_combo_prefer_medium_get(a_uint32_t dev_id, 441 a_uint32_t port_id, 442 fal_port_medium_t * 443 medium); 444 sw_error_t fal_port_combo_medium_status_get(a_uint32_t dev_id, 445 a_uint32_t port_id, 446 fal_port_medium_t * 447 medium); 448 sw_error_t fal_port_combo_fiber_mode_set(a_uint32_t dev_id, 449 a_uint32_t port_id, 450 fal_port_fiber_mode_t mode); 451 sw_error_t fal_port_combo_fiber_mode_get(a_uint32_t dev_id, 452 a_uint32_t port_id, 453 fal_port_fiber_mode_t * mode); 454 sw_error_t fal_port_local_loopback_set(a_uint32_t dev_id, 455 fal_port_t port_id, 456 a_bool_t enable); 457 458 sw_error_t 459 fal_port_local_loopback_get(a_uint32_t dev_id, fal_port_t port_id, 460 a_bool_t * enable); 461 462 sw_error_t 463 fal_port_remote_loopback_set(a_uint32_t dev_id, fal_port_t port_id, 464 a_bool_t enable); 465 466 sw_error_t 467 fal_port_remote_loopback_get(a_uint32_t dev_id, fal_port_t port_id, 468 a_bool_t * enable); 469 470 sw_error_t 471 fal_port_reset(a_uint32_t dev_id, fal_port_t port_id); 472 473 sw_error_t 474 fal_port_power_off(a_uint32_t dev_id, fal_port_t port_id); 475 476 sw_error_t 477 fal_port_power_on(a_uint32_t dev_id, fal_port_t port_id); 478 479 sw_error_t 480 fal_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id, 481 fal_mac_addr_t * mac); 482 483 sw_error_t 484 fal_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id, 485 fal_mac_addr_t * mac); 486 487 sw_error_t 488 fal_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id, 489 a_uint16_t * org_id, a_uint16_t * rev_id); 490 491 sw_error_t 492 fal_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id, 493 a_bool_t enable); 494 495 sw_error_t 496 fal_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id, 497 a_bool_t * enable); 498 499 sw_error_t 500 fal_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id, 501 fal_port_interface_mode_t mode); 502 503 sw_error_t 504 fal_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id, 505 fal_port_interface_mode_t * mode); 506 507 sw_error_t 508 fal_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id, 509 fal_port_interface_mode_t * mode); 510 511sw_error_t 512 fal_port_counter_set(a_uint32_t dev_id, fal_port_t port_id, 513 a_bool_t enable); 514 515sw_error_t 516 fal_port_counter_get(a_uint32_t dev_id, fal_port_t port_id, 517 a_bool_t * enable); 518 519sw_error_t 520 fal_port_counter_show (a_uint32_t dev_id, fal_port_t port_id, 521 fal_port_counter_info_t * counter_info); 522 523#ifdef __cplusplus 524} 525#endif /* __cplusplus */ 526#endif /* _FAL_PORTCTRL_H_ */ 527/** 528 * @} 529 */ 530