1/* 2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER 12 * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT 13 * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE 14 * USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#ifndef __NSS_GMAC_CLOCKS_H 18#define __NSS_GMAC_CLOCKS_H 19 20#include <asm/io.h> 21 22#ifndef CONFIG_OF 23#include <mach/msm_iomap.h> 24#endif 25 26/* Peripheral clock registers. */ 27#define NSS_ACC_REG (0x28EC) 28#define NSS_RESET_SPARE (0x3B60) 29#define CLK_HALT_NSSFAB0_NSSFAB1_STATEA (0x3C20) 30#define GMAC_COREn_CLK_SRC_CTL(n) (0x3CA0+(32 * (n))) 31#define GMAC_COREn_CLK_SRC0_MD(n) (0x3CA4+(32 * (n))) 32#define GMAC_COREn_CLK_SRC1_MD(n) (0x3CA8+(32 * (n))) 33#define GMAC_COREn_CLK_SRC0_NS(n) (0x3CAC+(32 * (n))) 34#define GMAC_COREn_CLK_SRC1_NS(n) (0x3CB0+(32 * (n))) 35#define GMAC_COREn_CLK_CTL(n) (0x3CB4+(32 * (n))) 36#define GMAC_COREn_CLK_FS(n) (0x3CB8+(32 * (n))) 37#define GMAC_COREn_RESET(n) (0x3CBC+(32 * (n))) 38#define GMAC_AHB_RESET (0x3E24) 39 40 41#define GMAC_ACC_CUST_MASK 0xFF000000 /* Custom ACC fields for GMAC 42 memories */ 43#define GMAC_FS_S_W_VAL 8 /* Wake and sleep counter value 44 of memory footswitch control. 45 Assuming max core frequency 46 is 266MHz */ 47 48/* NSS_RESET_SPARE register bits */ 49#define CAL_PBRS_RST_N_RESET 0x04000000 50#define LCKDT_RST_N_RESET 0x08000000 51#define SRDS_N_RESET 0x10000000 52 53 54/* GMAC_COREn_CLK_SRC_CTL register bits */ 55#define GMAC_DUAL_MN8_SEL 0x00000001 56#define GMAC_CLK_ROOT_ENA 0x00000002 57#define GMAC_CLK_LOW_PWR_ENA 0x00000004 58 59/* GMAC_COREn_CLK_SRC[0,1]_MD register bits (Assuming 266MHz) */ 60#define GMAC_CORE_CLK_M 0x7f 61#define GMAC_CORE_CLK_D 0 /* NOT(2*D) value */ 62#define GMAC_CORE_CLK_M_SHIFT 16 63#define GMAC_CORE_CLK_D_SHIFT 0 64#define GMAC_CORE_CLK_M_VAL (GMAC_CORE_CLK_M << GMAC_CORE_CLK_M_SHIFT) 65#define GMAC_CORE_CLK_D_VAL (GMAC_CORE_CLK_D << GMAC_CORE_CLK_D_SHIFT) 66 67/* GMAC_COREn_CLK_SRC[0,1]_NS register bits (Assuming 266MHz) */ 68#define GMAC_CORE_CLK_N 0 /* NOT(N-M) value N=301 */ 69#define GMAC_CORE_CLK_N_SHIFT 16 70#define GMAC_CORE_CLK_N_VAL (GMAC_CORE_CLK_N << GMAC_CORE_CLK_N_SHIFT) 71#define GMAC_CORE_CLK_MNCNTR_EN 0x00000100 /* Enable M/N counter */ 72#define GMAC_CORE_CLK_MNCNTR_RST 0x00000080 /* Activate reset for 73 M/N counter */ 74#define GMAC_CORE_CLK_MNCNTR_MODE_MASK 0x00000060 /* M/N counter mode 75 mask */ 76#define GMAC_CORE_CLK_MNCNTR_MODE_SHIFT 5 77#define GMAC_CORE_CLK_MNCNTR_MODE_DUAL (2 << GMAC_CORE_CLK_MNCNTR_MODE_SHIFT) 78 /* M/N counter mode 79 dual-edge */ 80#define GMAC_CORE_CLK_PRE_DIV_SEL_MASK 0x00000018 /* Pre divider select 81 mask */ 82#define GMAC_CORE_CLK_PRE_DIV_SEL_SHIFT 3 83#define GMAC_CORE_CLK_PRE_DIV_SEL_BYP (0 << GMAC_CORE_CLK_PRE_DIV_SEL_SHIFT) 84 /* Pre divider bypass */ 85#define GMAC_CORE_CLK_SRC_SEL_MASK 0x00000007 /* clk source Mux select 86 mask */ 87#define GMAC_CORE_CLK_SRC_SEL_SHIFT 0 88#define GMAC_CORE_CLK_SRC_SEL_PLL0 (2 << GMAC_CORE_CLK_SRC_SEL_SHIFT) 89 /* output of clk source 90 Mux is PLL0 */ 91 92/* CLK_HALT_NSSFAB0_NSSFAB1_STATEA register bits */ 93#define GMACn_CORE_CLK_HALT(x) (0x0010 << (x)) 94 95/* GMAC_COREn_CLK_CTL register bits */ 96#define GMAC_CLK_BRANCH_EN 0x0010 97#define GMAC_CLK_INV 0x0020 98#define GMAC_CLK_FABRIC_GATE_EN 0x0040 99 100#endif /* __NSS_GMAC_CLOCKS_H */ 101