1/* 2 ************************************************************************** 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 15 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 ************************************************************************** 17 */ 18 19#ifndef __MSM_NSS_GMAC_H 20#define __MSM_NSS_GMAC_H 21 22#include <linux/phy.h> 23 24#include <msm_nss_macsec.h> 25 26/* NSS GMAC Base Addresses */ 27#define NSS_GMAC0_BASE 0x37000000 28#define NSS_GMAC1_BASE 0x37200000 29#define NSS_GMAC2_BASE 0x37400000 30#define NSS_GMAC3_BASE 0x37600000 31#define NSS_GMAC_REG_LEN 0x00200000 32 33/* NSS GMAC Specific defines */ 34#define NSS_REG_BASE 0x03000000 35#define NSS_REG_LEN 0x0000FFFF 36 37 38/* Offsets of NSS config and status registers within NSS_REG_BASE */ 39/* We start the GMAC numbering from 0 */ 40#define NSS_CSR_REV 0x0000 41#define NSS_CSR_CFG 0x0004 42#define NSS_ETH_CLK_GATE_CTL 0x0008 43#define NSS_ETH_CLK_DIV0 0x000C 44#define NSS_ETH_CLK_DIV1 0x0010 45#define NSS_ETH_CLK_SRC_CTL 0x0014 46#define NSS_ETH_CLK_INV_CTL 0x0018 47#define NSS_MACSEC_CTL 0x0028 48#define NSS_QSGMII_CLK_CTL 0x002C 49#define NSS_GMAC0_CTL 0x0030 50#define NSS_GMAC1_CTL 0x0034 51#define NSS_GMAC2_CTL 0x0038 52#define NSS_GMAC3_CTL 0x003C 53#define NSS_ETH_CLK_ROOT_STAT 0x0040 54#define NSS_QSGMII_STAT 0x0044 55#define NSS_ETH_SPARE_CTL 0x0088 56#define NSS_ETH_SPARE_STAT 0x008C 57 58 59/* Macros to calculate register offsets */ 60#define NSS_GMACn_CTL(n) (NSS_GMAC0_CTL + (n * 4)) 61#define NSS_ETH_CLK_CTLn(x) (NSS_ETH_CLK_CTL0 + (x * 4)) 62 63 64/* NSS_ETH_CLK_GATE_CTL bits */ 65#define MACSEC3_CORE_CLK (1 << 30) 66#define MACSEC2_CORE_CLK (1 << 29) 67#define MACSEC1_CORE_CLK (1 << 28) 68#define MACSEC_CORE_CLKEN_VAL (0x7 << 28) 69#define MACSEC_GMII_RX_CLKEN_VAL (0x7 << 24) 70#define MACSEC_GMII_TX_CLKEN_VAL (0x7 << 20) 71#define GMAC0_PTP_CLK (1 << 16) 72#define GMAC0_RGMII_RX_CLK (1 << 9) 73#define GMAC0_RGMII_TX_CLK (1 << 8) 74#define GMAC0_GMII_RX_CLK (1 << 4) 75#define GMAC0_GMII_TX_CLK (1 << 0) 76 77#define GMAC0_RGMII_TX_CLK_SHIFT 8 78#define GMAC0_RGMII_RX_CLK_SHIFT 9 79#define GMAC0_GMII_RX_CLK_SHIFT 4 80#define GMAC0_GMII_TX_CLK_SHIFT 0 81#define GMAC0_PTP_CLK_SHIFT 16 82 83/* Macros to calculate bit offsets in NSS_ETH_CLK_GATE_CTL register 84 * MACSEC_CORE_CLK: x = 1,2,3 85 * GMII_xx_CLK: x = 0,1,2,3 86 * RGMII_xx_CLK: x = 0,1 87 * PTP_CLK: x = 0,1,2,3 88*/ 89#define MACSECn_CORE_CLK(x) (1 << (MACSEC1_CORE_CLK + x)) 90#define GMACn_GMII_TX_CLK(x) (1 << (GMAC0_GMII_TX_CLK_SHIFT + x)) 91#define GMACn_GMII_RX_CLK(x) (1 << (GMAC0_GMII_RX_CLK_SHIFT + x)) 92#define GMACn_RGMII_TX_CLK(x) (1 << (GMAC0_RGMII_TX_CLK_SHIFT + (x * 2))) 93#define GMACn_RGMII_RX_CLK(x) (1 << (GMAC0_RGMII_RX_CLK_SHIFT + (x * 2))) 94#define GMACn_PTP_CLK(x) (1 << (GMAC0_PTP_CLK_SHIFT + x)) 95 96/* NSS_ETH_CLK_DIV0 bits ; n = 0,1,2,3 */ 97/* PHY increments divider values by 1. Hence the values here are (x - 1) */ 98#define RGMII_CLK_DIV_1000 1 99#define RGMII_CLK_DIV_100 9 100#define RGMII_CLK_DIV_10 99 101#define SGMII_CLK_DIV_1000 0 102#define SGMII_CLK_DIV_100 4 103#define SGMII_CLK_DIV_10 49 104#define QSGMII_CLK_DIV_1000 1 105#define QSGMII_CLK_DIV_100 9 106#define QSGMII_CLK_DIV_10 99 107#define GMACn_CLK_DIV_SIZE 0x7F 108#define GMACn_CLK_DIV(n, val) (val << (n * 8)) 109 110/* NSS_ETH_CLK_SRC_CTL bits */ 111#define GMAC0_GMII_CLK_RGMII (1 << 0) 112#define GMAC1_GMII_CLK_RGMII (1 << 1) 113 114/* NSS_MACSEC_CTL bits */ 115#define GMAC1_MACSEC_BYPASS 0x1 116#define GMACn_MACSEC_BYPASS(n) (GMAC1_MACSEC_BYPASS << (n - 1)) 117 /* n = 1,2,3 */ 118#define MACSEC_EXT_BYPASS_EN_MASK 0x7 119#define MACSEC_DP_RST_VAL (0x7 << 4) 120 121/* Macros to calculate bit offsets in NSS_ETH_CLK_CTL3 register */ 122#define GMACn_GMII_CLK_RGMII(x) (1 << x) 123 124/* NSS_QSGMII_CLK_CTL bits */ 125#define GMAC0_TX_CLK_HALT (1 << 7) 126#define GMAC0_RX_CLK_HALT (1 << 8) 127#define GMAC1_TX_CLK_HALT (1 << 9) 128#define GMAC1_RX_CLK_HALT (1 << 10) 129#define GMAC2_TX_CLK_HALT (1 << 11) 130#define GMAC2_RX_CLK_HALT (1 << 12) 131#define GMAC3_TX_CLK_HALT (1 << 13) 132#define GMAC3_RX_CLK_HALT (1 << 14) 133 134#define GMAC0_QSGMII_TX_CLK_SHIFT 7 135#define GMAC0_QSGMII_RX_CLK_SHIFT 8 136 137/* Macros to calculate bit offsets in NSS_QSGMII_CLK_CTL register */ 138#define GMACn_QSGMII_TX_CLK(n) (1 << (GMAC0_QSGMII_TX_CLK_SHIFT + (n * 2))) 139#define GMACn_QSGMII_RX_CLK(n) (1 << (GMAC0_QSGMII_RX_CLK_SHIFT + (n * 2))) 140 141/* NSS_GMACn_CTL bits */ 142#define GMAC_IFG_CTL(x) (x) 143#define GMAC_IFG_LIMIT(x) (x << 8) 144#define GMAC_PHY_RGMII (1 << 16) 145#define GMAC_PHY_QSGMII (0 << 16) 146#define GMAC_FLOW_CTL (1 << 18) 147#define GMAC_CSYS_REQ (1 << 19) 148#define GMAC_PTP_TRIG (1 << 20) 149 150/* GMAC min Inter Frame Gap values */ 151#define GMAC_IFG 12 152#define MACSEC_IFG (0x2D) 153#define IFG_MASK (0x3F) 154#define GMAC_IFG_MIN_1000 10 155#define GMAC_IFG_MIN_HALF_DUPLEX 8 156 157/* 158 * GMAC min Inter Frame Gap Limits. 159 * In full duplex mode set to same value as IFG 160*/ 161#define GMAC_IFG_LIMIT_HALF 12 162 163/* QSGMII Specific defines */ 164#define QSGMII_REG_BASE 0x1bb00000 165#define QSGMII_REG_LEN 0x0000FFFF 166 167/* QSGMII Register offsets */ 168#define PCS_QSGMII_CTL 0x020 169#define PCS_QSGMII_SGMII_MODE 0x064 170#define PCS_MODE_CTL 0x068 171#define PCS_QSGMII_MAC_STAT 0x074 172#define PCS_ALL_CH_CTL 0x080 173#define PCS_ALL_CH_STAT 0x084 174#define PCS_CAL_LCKDT_CTL 0x120 175#define PCS_CAL_LCKDT_CTL_STATUS 0x124 176#define QSGMII_PHY_MODE_CTL 0x128 177#define QSGMII_PHY_QSGMII_CTL 0x134 178#define QSGMII_PHY_SGMII_1_CTL 0x13C 179#define QSGMII_PHY_SGMII_2_CTL 0x140 180#define QSGMII_PHY_SERDES_CTL 0x144 181 182/* Bit definitions for PCS_QSGMII_CTL register */ 183#define PCS_CH0_SERDES_SN_DETECT 0x800 184#define PCS_CHn_SERDES_SN_DETECT(n) (PCS_CH0_SERDES_SN_DETECT << n) 185#define PCS_CH0_SERDES_SN_DETECT_2 0x10000 186#define PCS_CHn_SERDES_SN_DETECT_2(n) (PCS_CH0_SERDES_SN_DETECT_2 << n) 187#define PCS_QSGMII_DEPTH_THRESH_MASK 0x300 188#define PCS_QSGMII_DEPTH_THRESH(n) (n << 8) 189 /* Threshold for depth control */ 190#define PCS_QSGMII_SHORT_LATENCY 0x20 191#define PCS_QSGMII_SHORT_THRESH 0x10 192#define PCS_QSGMII_CUTTHROUGH_RX 0x8 193#define PCS_QSGMII_CUTTHROUGH_TX 0x4 194#define PCS_QSGMII_SW_VER_1_7 0x2 195#define PCS_QSGMII_ATHR_CSCO_AUTONEG 0x1 196 197 198/* Bit definitions for PCS_QSGMII_SGMII_MODE */ 199#define PCS_QSGMII_MODE_SGMII (0x0 << 0) 200#define PCS_QSGMII_MODE_QSGMII (0x1 << 0) 201 202/* Bit definitions for QSGMII_PHY_MODE_CTL */ 203#define QSGMII_PHY_MODE_SGMII (0x0 << 0) 204#define QSGMII_PHY_MODE_QSGMII (0x1 << 0) 205 206/* Bit definitions for PCS_MODE_CTL register */ 207#define PCS_MODE_CTL_BASE_X 0x00 208#define PCS_MODE_CTL_SGMII_PHY 0x01 209#define PCS_MODE_CTL_SGMII_MAC 0x02 210#define PCS_MODE_CTL_CH0_PHY_RESET 0x10 211#define PCS_MODE_CTL_CH0_PHY_LOOPBACK 0x20 212#define PCS_MODE_CTL_CH0_AUTONEG_RESTART 0x40 213#define PCS_MODE_CTL_CH0_AUTONEG_EN 0x80 214#define PCS_MODE_CTL_CHn_PHY_RESET(n) (PCS_MODE_CTL_CH0_PHY_RESET << (n * 8)) 215#define PCS_MODE_CTL_CHn_PHY_LOOPBACK(n) (PCS_MODE_CTL_CH0_PHY_LOOPBACK << (n * 8)) 216#define PCS_MODE_CTL_CHn_AUTONEG_EN(n) (PCS_MODE_CTL_CH0_AUTONEG_EN << (n * 8)) 217#define PCS_MODE_CTL_CHn_AUTONEG_RESTART(n) (PCS_MODE_CTL_CH0_AUTONEG_RESTART << (n * 8)) 218 219/* Bit definitions for PCS_QSGMII_MAC_STAT register */ 220#define PCS_MAC_STAT_CH0_LINK 0x0001 221#define PCS_MAC_STAT_CH0_DUPLEX 0x0002 222#define PCS_MAC_STAT_CH0_SPEED_MASK 0x000C 223#define PCS_MAC_STAT_CH0_PAUSE 0x0010 224#define PCS_MAC_STAT_CH0_ASYM_PAUSE 0x0020 225#define PCS_MAC_STAT_CH0_TX_PAUSE 0x0040 226#define PCS_MAC_STAT_CH0_RX_PAUSE 0x0080 227#define PCS_MAC_STAT_CHn_LINK(n) (PCS_MAC_STAT_CH0_LINK << (n * 8)) 228#define PCS_MAC_STAT_CHn_DUPLEX(n) (PCS_MAC_STAT_CH0_DUPLEX << (n * 8)) 229#define PCS_MAC_STAT_CHn_SPEED_MASK(n) (PCS_MAC_STAT_CH0_SPEED_MASK << (n * 8)) 230#define PCS_MAC_STAT_CHn_SPEED(n, reg) ((reg & PCS_MAC_STAT_CHn_SPEED_MASK(n)) >> ((n * 8) + 2)) 231#define PCS_MAC_STAT_CHn_PAUSE (PCS_MAC_STAT_CH0_PAUSE << (n * 8)) 232#define PCS_MAC_STAT_CHn_ASYM_PAUSE (PCS_MAC_STAT_CH0_ASYM_PAUSE << (n * 8)) 233#define PCS_MAC_STAT_CHn_TX_PAUSE (PCS_MAC_STAT_CH0_TX_PAUSE << (n * 8)) 234#define PCS_MAC_STAT_CHn_RX_PAUSE (PCS_MAC_STAT_CH0_RX_PAUSE << (n * 8)) 235 236/* Bit definitions for PCS_ALL_CH_CTL register */ 237#define PCS_CH0_FORCE_SPEED 0x2 238#define PCS_CHn_FORCE_SPEED(n) (PCS_CH0_FORCE_SPEED << (n * 4)) 239#define PCS_CH0_SPEED_MASK 0xC 240#define PCS_CHn_SPEED_MASK(n) (PCS_CH0_SPEED_MASK << (n * 4)) 241#define PCS_CH_SPEED_10 0x0 242#define PCS_CH_SPEED_100 0x4 243#define PCS_CH_SPEED_1000 0x8 244#define PCS_CHn_SPEED(ch, speed) (speed << (ch * 4)) 245 246/* Bit definitions for PCS_ALL_CH_STAT register */ 247#define PCS_CH0_AUTONEG_COMPLETE 0x0040 248#define PCS_CHn_AUTONEG_COMPLETE(n) (PCS_CH0_AUTONEG_COMPLETE << (n * 8)) 249 250 251/* Bit definitions for PCS_CAL_LCKDT_CTL register */ 252#define PCS_LCKDT_RST 0x80000 253 254/* Bit definitions for QSGMII_PHY_QSGMII_CTL register */ 255#define QSGMII_PHY_CDR_EN 0x00000001 256#define QSGMII_PHY_RX_FRONT_EN 0x00000002 257#define QSGMII_PHY_RX_SIGNAL_DETECT_EN 0x00000004 258#define QSGMII_PHY_TX_DRIVER_EN 0x00000008 259#define QSGMII_PHY_NEAR_END_LOOPBACK 0x00000020 260#define QSGMII_PHY_FAR_END_LOOPBACK 0x00000040 261#define QSGMII_PHY_QSGMII_EN 0x00000080 262#define QSGMII_PHY_SLEW_RATE_CTL_MASK 0x00000300 263#define QSGMII_PHY_SLEW_RATE_CTL(x) (x << 8) 264#define QSGMII_PHY_DEEMPHASIS_LVL_MASK 0x00000C00 265#define QSGMII_PHY_DEEMPHASIS_LVL(x) (x << 10) 266#define QSGMII_PHY_PHASE_LOOP_GAIN_MASK 0x00007000 267#define QSGMII_PHY_PHASE_LOOP_GAIN(x) (x << 12) 268#define QSGMII_PHY_RX_DC_BIAS_MASK 0x000C0000 269#define QSGMII_PHY_RX_DC_BIAS(x) (x << 18) 270#define QSGMII_PHY_RX_INPUT_EQU_MASK 0x00300000 271#define QSGMII_PHY_RX_INPUT_EQU(x) (x << 20) 272#define QSGMII_PHY_CDR_PI_SLEW_MASK 0x00C00000 273#define QSGMII_PHY_CDR_PI_SLEW(x) (x << 22) 274#define QSGMII_PHY_SIG_DETECT_THRESH_MASK 0x03000000 275#define QSGMII_PHY_SIG_DETECT_THRESH(x) (x << 24) 276#define QSGMII_PHY_TX_SLEW_MASK 0x0C000000 277#define QSGMII_PHY_TX_SLEW(x) (x << 26) 278#define QSGMII_PHY_TX_DRV_AMP_MASK 0xF0000000 279#define QSGMII_PHY_TX_DRV_AMP(x) (x << 28) 280 281 282/* Bit definitions for QSGMII_PHY_SERDES_CTL register */ 283#define SERDES_100MHZ_OSC_CLK 0x00000001 284#define SERDES_LOCK_DETECT_EN 0x00000002 285#define SERDES_PLL_EN 0x00000004 286#define SERDES_VCO_MANUAL_CAL 0x00000008 287#define SERDES_PLL_LOOP_FILTER_MASK 0x00000070 288#define SERDES_PLL_LOOP_FILTER(x) (x << 4) 289#define SERDES_RSV_MASK 0x00FF0000 290#define SERDES_RSV(x) (x << 16) 291#define SERDES_PLL_AMP_MASK 0x07000000 292#define SERDES_PLL_AMP(x) (x << 24) 293#define SERDES_PLL_ICP_MASK 0x70000000 294#define SERDES_PLL_ICP(x) (x << 28) 295 296/* Interface between GMAC and PHY */ 297#define GMAC_INTF_RGMII 0 298#define GMAC_INTF_SGMII 1 299#define GMAC_INTF_QSGMII 2 300 301/* For MII<->MII Interfaces that do not use an Ethernet PHY */ 302#define NSS_GMAC_NO_MDIO_PHY PHY_MAX_ADDR 303 304/* GMAC phy interface profiles */ 305#define NSS_GMAC_PHY_PROFILE_2R_2S 0 /* 2 RGMII, 2 SGMII */ 306#define NSS_GMAC_PHY_PROFILE_1R_3S 1 /* 1 RGMII, 3 SGMII*/ 307#define NSS_GMAC_PHY_PROFILE_QS 2 /* 4 QSGMII */ 308 309extern int32_t nss_gmac_get_phy_profile(void); 310 311struct msm_nss_gmac_platform_data { 312 uint32_t phy_mdio_addr; /* MDIO address of the connected PHY */ 313 uint32_t poll_required; /* [0/1] Link status poll? */ 314 uint32_t rgmii_delay; 315 uint32_t phy_mii_type; 316 uint32_t emulation; /* Running on emulation platform */ 317 uint8_t mac_addr[6]; 318 int32_t forced_speed; /* Forced speed. Values used from 319 ethtool.h. 0 = Speed not forced */ 320 int32_t forced_duplex; /* Forced duplex. Values used from 321 ethtool.h. 0 = Duplex not forced. */ 322 uint32_t socver; 323}; 324 325#define NSS_MAX_GMACS 4 326#define IPQ806X_MDIO_BUS_NAME "mdio-gpio" 327#define IPQ806X_MDIO_BUS_NUM 0 328#define IPQ806X_MDIO_BUS_MAX 1 329 330#define IPQ806X_CLK_CTL_PHYS 0x00900000 331#define IPQ806X_CLK_CTL_SIZE SZ_16K 332#define IPQ806X_TCSR_BASE 0x1A400000 333#define IPQ806X_TCSR_SIZE 0xFFFF 334 335#endif /*__ASM_NSS_GMAC_H */ 336 337 338 339