1/* * Copyright (c) 2013 The Linux Foundation. All rights reserved.* */
2/*
3 * Copyright (c) 2013 The Linux Foundation.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#ifndef __NSS_CLOCKS_H
21#define __NSS_CLOCKS_H
22
23#if (NSS_DT_SUPPORT != 1)
24#include <asm/io.h>
25#include <mach/msm_iomap.h>
26
27#define REG(off)	(MSM_CLK_CTL_BASE + (off))
28#define REG_GCC(off)	(MSM_APCS_GCC_BASE + (off))
29
30/* Peripheral clock registers. */
31#define PLL18_ACR				REG(0x1234)
32#define PLL18_MODE				REG(0x31A0)
33#define PLL18_L_VAL				REG(0x31A4)
34#define PLL18_M_VAL				REG(0x31A8)
35#define PLL18_N_VAL				REG(0x31AC)
36#define PLL18_TEST_CTL				REG(0x31B0)
37#define PLL18_CONFIG				REG(0x31B4)
38#define PLL18_STATUS				REG(0x31B8)
39#define PLL_LOCK_DET_STATUS			REG(0x3420)
40#define PLL_LOCK_DET_MASK			REG(0x3424)
41#define CE5_CORE_CLK_SRC_CTL 			REG(0x36C0)
42#define CE5_CORE_CLK_SRC0_NS 			REG(0x36C4)
43#define NSS_ACC_REG				REG(0x28EC)
44#define NSS_RESET_SPARE				REG(0x3B60)
45#define NSSFB0_CLK_SRC_CTL			REG(0x3B80)
46#define NSSFB0_CLK_SRC0_NS			REG(0x3B84)
47#define NSSFB0_CLK_SRC1_NS			REG(0x3B88)
48#define NSSFB0_CLK_CTL				REG(0x3BA0)
49#define NSSFAB_GLOBAL_BUS_NS			REG(0x3BC0)
50#define NSSFB1_CLK_SRC_CTL			REG(0x3BE0)
51#define NSSFB1_CLK_SRC0_NS			REG(0x3BE4)
52#define NSSFB1_CLK_SRC1_NS			REG(0x3BE8)
53#define NSSFB1_CLK_CTL				REG(0x3C00)
54#define CLK_HALT_NSSFAB0_NSSFAB1_STATEA		REG(0x3C20)
55#define UBI32_MPT0_CLK_CTL			REG(0x3C40)
56#define UBI32_MPT1_CLK_CTL			REG(0x3C44)
57#define CE5_HCLK_SRC_CTL			REG(0x3C60)
58#define CE5_HCLK_SRC0_NS			REG(0x3C64)
59#define CE5_HCLK_SRC1_NS			REG(0x3C68)
60#define CE5_HCLK_CTL				REG(0x3C6C)
61#define NSSFPB_CLK_CTL				REG(0x3C80)
62#define NSSFPB_CLK_SRC_CTL			REG(0x3C84)
63#define NSSFPB_CLK_SRC0_NS			REG(0x3C88)
64#define NSSFPB_CLK_SRC1_NS			REG(0x3C8C)
65#define GMAC_COREn_CLK_SRC_CTL(n)		REG(0x3CA0+32*(n))
66#define GMAC_CORE1_CLK_SRC_CTL			REG(0x3CA0)
67#define GMAC_COREn_CLK_SRC0_MD(n)		REG(0x3CA4+32*(n))
68#define GMAC_CORE1_CLK_SRC0_MD			REG(0x3CA4)
69#define GMAC_COREn_CLK_SRC1_MD(n)		REG(0x3CA8+32*(n))
70#define GMAC_CORE1_CLK_SRC1_MD			REG(0x3CA8)
71#define GMAC_COREn_CLK_SRC0_NS(n)		REG(0x3CAC+32*(n))
72#define GMAC_CORE1_CLK_SRC0_NS			REG(0x3CAC)
73#define GMAC_COREn_CLK_SRC1_NS(n)		REG(0x3CB0+32*(n))
74#define GMAC_CORE1_CLK_SRC1_NS			REG(0x3CB0)
75#define GMAC_COREn_CLK_CTL(n)			REG(0x3CB4+32*(n))
76#define GMAC_CORE1_CLK_CTL			REG(0x3CB4)
77#define GMAC_COREn_CLK_FS(n)			REG(0x3CB8+32*(n))
78#define GMAC_CORE1_CLK_FS			REG(0x3CB8)
79#define GMAC_COREn_RESET(n)			REG(0x3CBC+32*(n))
80#define GMAC_CORE1_RESET			REG(0x3CBC)
81#define UBI32_COREn_CLK_SRC_CTL(n)		REG(0x3D20+32*(n))
82#define UBI32_CORE1_CLK_SRC_CTL			REG(0x3D20)
83#define UBI32_COREn_CLK_SRC0_MD(n)		REG(0x3D24+32*(n))
84#define UBI32_CORE1_CLK_SRC0_MD			REG(0x3D24)
85#define UBI32_COREn_CLK_SRC1_MD(n)		REG(0x3D28+32*(n))
86#define UBI32_CORE1_CLK_SRC1_MD			REG(0x3D28)
87#define UBI32_COREn_CLK_SRC0_NS(n)		REG(0x3D2C+32*(n))
88#define UBI32_CORE1_CLK_SRC0_NS			REG(0x3D2C)
89#define UBI32_COREn_CLK_SRC1_NS(n)		REG(0x3D30+32*(n))
90#define UBI32_CORE1_CLK_SRC1_NS			REG(0x3D30)
91#define UBI32_COREn_CLK_CTL(n)			REG(0x3D34+32*(n))
92#define UBI32_CORE1_CLK_CTL			REG(0x3D34)
93#define UBI32_COREn_CLK_FS(n)			REG(0x3D38+32*(n))
94#define UBI32_CORE1_CLK_FS			REG(0x3D38)
95#define UBI32_COREn_RESET_CLAMP(n)		REG(0x3D3C+32*(n))
96#define UBI32_CORE1_RESET_CLAMP			REG(0x3D3C)
97#define NSS_250MHZ_CLK_SRC_CTL			REG(0x3D60)
98#define NSS_250MHZ_CLK_SRC0_NS			REG(0x3D64)
99#define NSS_250MHZ_CLK_SRC1_NS			REG(0x3D68)
100#define NSS_250MHZ_CLK_SRC0_MD			REG(0x3D6C)
101#define NSS_250MHZ_CLK_SRC1_MD			REG(0x3D70)
102#define NSS_250MHZ_CLK_CTL			REG(0x3D74)
103#define CE5_ACLK_SRC_CTL			REG(0x3D80)
104#define CE5_ACLK_SRC0_NS			REG(0x3D84)
105#define CE5_ACLK_SRC1_NS			REG(0x3D88)
106#define CE5_ACLK_CTL				REG(0x3D8C)
107#define PLL_ENA_NSS				REG(0x3DA0)
108#define NSSTCM_CLK_SRC_CTL			REG(0x3DC0)
109#define NSSTCM_CLK_SRC0_NS			REG(0x3DC4)
110#define NSSTCM_CLK_SRC1_NS			REG(0x3DC8)
111#define NSSTCM_CLK_FS				REG(0x3DCC)
112#define NSSTCM_CLK_CTL				REG(0x3DD0)
113#define CE5_CORE_0_RESET			REG(0x3E00)
114#define CE5_CORE_1_RESET			REG(0x3E04)
115#define CE5_CORE_2_RESET			REG(0x3E08)
116#define CE5_CORE_3_RESET			REG(0x3E0C)
117#define CE5_AHB_RESET				REG(0x3E10)
118#define NSS_RESET				REG(0x3E20)
119#define GMAC_AHB_RESET				REG(0x3E24)
120#define MACSEC_CORE1_RESET			REG(0x3E28)
121#define MACSEC_CORE2_RESET			REG(0x3E2C)
122#define MACSEC_CORE3_RESET			REG(0x3E30)
123#define NSS_TCM_RESET				REG(0x3E40)
124
125enum nss_hal_pvt_pll_status {
126	PLL_NOT_LOCKED,
127	PLL_LOCKED
128};
129
130#endif
131#endif /* __NSS_CLOCKS_H */
132