. 2 4H @8 q < UUu H? n A < K UUu XM W N ] a e N 0u @ a UUu @ . 2 4H @8 q < UUu H? n A < K UUu XM W N ] a e ! 0u F @ . , 2 4H @8 q < UUu H? n A < K % XM W N ] a e N 0u UU @ . x 2 n N @8 d < ] H? X 8 A U m K K XM H . N H a 9 e 7 'vb 0u 0 M v^ K @ H < . P 2 I @8 B < > H? ; ^B A 9 I $ K 2 XM 0 | N 0 ] ( a & fff e $ N 0u @ $I 3 >V 2 @ 0 ( $ N . IUU 2 C @8 = < 9 H? 6 " A 4a K -UU XM ,q N , a Fff e C 0u : -UU @ - pll%d reg%d chipc%d . R N e T u* . N e N a' @ ! ? @ P ? % " 2 5 ? @ x .` ` c ` ,` (` @ @ ` @ @ ,` c (p & ` @ w @ @ ! C @ $ $ ( @ @ rmin rmax r%dt r%dd . N 0 e ] . @ @ 1 fO ` @ @ 1 ` @ @ | ` 0 P ` P 1 ff ` @ . 2 @8 < H? A K XM N ] a e 0u @ @ P ` P 1 33 ` @ @ @ | ` @ @ | ` P ` P 1 33 ` P ` P 1 333 ` xtalfreq Invalid/Unsupported xtal value %d P b h `S clkreq_conf cbuckout cldo_ldo2 cldo_pwm force_pwm_cbuck dacrate2g
GCC: (Buildroot 2012.02) 4.5.3
.symtab .strtab .shstrtab .rel.text .data .bss .ARM.extab .rel.ARM.exidx .rel.rodata .rodata.str1.1 .comment .note.GNU-stack .ARM.attributes
hndpmu.c $a si_pmu_res_depfltr_bb $d si_pmu_res_depfltr_ncb si_pmu_res_depfltr_paldo si_pmu_res_depfltr_npaldo si_pmu1_xtaltab0 si_pmu1_xtaldef0 si_pmu_res_deps si_pmu_resdeptbl_upd si_pmu0_pllinit0 si_pmu_get_rsc_positions.clone.0 si_pmu_htclk_mask.clone.1 si_pmu_pll_on si_pmu_enb_slow_clk.clone.5 si_pmu0_alpclk0.clone.10 si_pmu1_alpclk0.clone.11 si_pmu_pllctrlreg_update.clone.7.clone.14 si_4706_pmu_clock.clone.16 si_pmu_res_masks si_pmu_res_uptime si_pmu_set_lpoclk si_set_bb_vcofreq_frac.clone.15 si_pmu_pll_off si_pmu2_pllinit0 si_pmu_spuravoid_pllupdate.clone.13 si_pmu5_clock si_pmu1_pllfvco0 si_pmu1_cpuclk0 si_pmu1_pllinit1 si_pmu1_pllinit0 pmu1_xtaltab0_880 pmu1_xtaltab0_880_4329 pmu1_xtaltab0_1760 pmu1_xtaltab0_1440 pmu1_xtaltab0_960 pmu0_xtaltab0 rstr_pllD rstr_regD rstr_chipcD pmu2_xtaltab0_adfll_485 pmu2_xtaltab0_adfll_480 bcm4328a0_res_depend bcm4328a0_res_updown bcm4325a0_res_depend bcm4325a0_res_updown bcm4315a0_res_depend bcm4315a0_res_updown bcm4329_res_depend bcm4329_res_updown bcm4319a0_res_depend bcm4319a0_res_updown bcm4336a0_res_depend bcm4336a0_res_updown bcm4330a0_res_depend bcm4330a0_res_updown bcm4334b0_res_depend bcm4334b0_res_updown bcm4334a0_res_depend bcm4334a0_res_updown bcm4324a0_res_depend bcm4324a0_res_updown bcm4335b0_res_depend bcm4335_res_updown bcm4345_res_depend bcm4345_res_updown bcm4350_res_pciewar bcm4350_res_depend bcm4350_res_updown bcm4360B1_res_updown bcm43602_res_pciewar bcm43602_res_depend bcm43602_res_updown bcm4334b0_res_hsic_depend bcm4360_res_updown bcm4324b0_res_updown rstr_rmin rstr_rmax rstr_rDt rstr_rDd pmu2_xtaltab0_adfll_492 spuravoid_4324 C.252.38566 C.253.38567 sdiod_drive_strength_tab1 sdiod_drive_strength_tab2 sdiod_drive_strength_tab3 sdiod_drive_strength_tab4_1v8 sdiod_drive_strength_tab5_1v8 sdiod_drive_strength_tab6_1v8 sdiod_drive_strength_tab7_3v3 pmu1_pllctrl_tab_4335_961mhz pmu1_xtaltab0_4335_drv pmu1_xtaltab0_4345 pmu1_pllctrl_tab_4350C0_963mhz pmu1_xtaltab0_4350 pmu1_pllctrl_tab_43242A1 pmu1_xtaltab0_43242 pmu1_pllctrl_tab_43242A0 pmu1_pllctrl_tab_4350_963mhz pmu1_pllctrl_tab_4335_968mhz rstr_xtalfreq rstr_Invalid_Unsupported_xtal_value_D C.1613.45006 rstr_clkreq_conf rstr_cbuckout rstr_cldo_ldo2 rstr_cldo_pwm rstr_force_pwm_cbuck rstr_dacrate2g rsc_4313 rsc_4314 rsc_4315 rsc_4319 rsc_4322 rsc_4324 rsc_4325 rsc_4329 rsc_4330 rsc_43236 rsc_4334 rsc_4335 rsc_4336 rsc_4350 rsc_4352 rsc_4360 rsc_43143 rsc_43239 rsc_43602 ilpcycles_per_sec __aeabi_unwind_cpp_pr0 si_findcoreidx si_corereg_addr osl_pcie_rreg outer_cache osl_delay __aeabi_unwind_cpp_pr1 __aeabi_uidiv si_pmu_chipcontrol si_pmu_corereg si_is_otp_disabled si_pcie_get_L1substate si_pmu_regcontrol getintvar si_gci_chipcontrol si_pmu_pllcontrol si_pmu_pllupd __aeabi_idiv __aeabi_uidivmod si_setcoreidx bcm_uint64_multiple_add bcm_uint64_divide si_pmu_otp_pllcontrol snprintf getvar bcm_strtoul si_pmu_otp_regcontrol si_pmu_otp_chipcontrol si_pmu_set_switcher_voltage si_pmu_set_ldo_voltage si_pmu_paref_ldo_enable si_pmu_fast_pwrup_delay si_coreidx si_ilp_clock si_pmu_force_ilp si_pmu_minresmask_htavail_set si_pll_minresmask_reset si_pmu_def_alp_clock si_pmu_get_pmutimer si_pmu_get_pmutime_diff si_pmu_wait_for_res_pending si_pmu_wait_for_steady_state si_pmu_pllreset si_osh si_pmu_res_init si_corereg si_pmu_pll_off_PARR si_switch_core si_restore_core si_pmu_is_autoresetphyclk_disabled si_pmu_switch_on_PARLDO si_pmu_get_bb_vcofreq si_pmu_alp_clock si_alp_clock si_pmu_ilp_clock_set si_pmu_ilp_clock si_sdiod_drive_strength_init si_pmu_init si_pmu_otp_power si_pmu_rcal si_pmu_spuravoid si_pmu_spuravoid_isdone si_pmu_cal_fvco bcm_uint64_right_shift si_pmu_si_clock si_pmu_mem_clock si_pmu_cpu_clock si_pmu_fvco_pllreg si_mac_clk si_pmu_update_pllcontrol printk si_pmu_gband_spurwar si_pmu_is_otp_powered si_pmu_sprom_enable si_pmu_is_sprom_enabled si_pmu_chip_init si_pmu_swreg_init si_pmu_radio_enable si_wrapperreg si_pmu_waitforclk_on_backplane si_pmu_measure_alpclk si_pmu_slow_clk_reinit si_pmu_set_4330_plldivs si_pmu_pll_init si_pmu_res_minmax_update g_si_pmutmr_lock_arg g_si_pmutmr_lock_cb g_si_pmutmr_unlock_cb cbuck2vreg_tbl