1/* 2 * Generic Broadcom Home Networking Division (HND) DMA engine HW interface 3 * This supports the following chips: BCM42xx, 44xx, 47xx . 4 * 5 * Copyright (C) 2015, Broadcom Corporation. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 14 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 16 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 17 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $Id: sbhnddma.h 452437 2014-01-30 11:59:09Z $ 20 */ 21 22#ifndef _sbhnddma_h_ 23#define _sbhnddma_h_ 24 25/* DMA structure: 26 * support two DMA engines: 32 bits address or 64 bit addressing 27 * basic DMA register set is per channel(transmit or receive) 28 * a pair of channels is defined for convenience 29 */ 30 31 32/* 32 bits addressing */ 33 34/* dma registers per channel(xmt or rcv) */ 35typedef volatile struct { 36 uint32 control; /* enable, et al */ 37 uint32 addr; /* descriptor ring base address (4K aligned) */ 38 uint32 ptr; /* last descriptor posted to chip */ 39 uint32 status; /* current active descriptor, et al */ 40} dma32regs_t; 41 42typedef volatile struct { 43 dma32regs_t xmt; /* dma tx channel */ 44 dma32regs_t rcv; /* dma rx channel */ 45} dma32regp_t; 46 47typedef volatile struct { /* diag access */ 48 uint32 fifoaddr; /* diag address */ 49 uint32 fifodatalow; /* low 32bits of data */ 50 uint32 fifodatahigh; /* high 32bits of data */ 51 uint32 pad; /* reserved */ 52} dma32diag_t; 53 54/* 55 * DMA Descriptor 56 * Descriptors are only read by the hardware, never written back. 57 */ 58typedef volatile struct { 59 uint32 ctrl; /* misc control bits & bufcount */ 60 uint32 addr; /* data buffer address */ 61} dma32dd_t; 62 63/* 64 * Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page. 65 */ 66#define D32RINGALIGN_BITS 12 67#define D32MAXRINGSZ (1 << D32RINGALIGN_BITS) 68#define D32RINGALIGN (1 << D32RINGALIGN_BITS) 69 70#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t)) 71 72/* transmit channel control */ 73#define XC_XE ((uint32)1 << 0) /* transmit enable */ 74#define XC_SE ((uint32)1 << 1) /* transmit suspend request */ 75#define XC_LE ((uint32)1 << 2) /* loopback enable */ 76#define XC_FL ((uint32)1 << 4) /* flush request */ 77#ifdef USE_4345B0_MR_MASK_2BITS_IN_ROM 78#define XC_MR_MASK 0x000000C0 /* Multiple outstanding reads */ 79#else /* USE_4345B0_MR_MASK_2BITS_IN_ROM */ 80#define XC_MR_MASK 0x000001C0 /* Multiple outstanding reads */ 81#endif /* USE_4345B0_MR_MASK_2BITS_IN_ROM */ 82#define XC_MR_SHIFT 6 83#define XC_PD ((uint32)1 << 11) /* parity check disable */ 84#define XC_AE ((uint32)3 << 16) /* address extension bits */ 85#define XC_AE_SHIFT 16 86#define XC_BL_MASK 0x001C0000 /* BurstLen bits */ 87#define XC_BL_SHIFT 18 88#define XC_PC_MASK 0x00E00000 /* Prefetch control */ 89#define XC_PC_SHIFT 21 90#define XC_PT_MASK 0x03000000 /* Prefetch threshold */ 91#define XC_PT_SHIFT 24 92 93/* Multiple outstanding reads */ 94#define DMA_MR_1 0 95#define DMA_MR_2 1 96#define DMA_MR_4 2 97#define DMA_MR_8 3 98#define DMA_MR_12 4 99#define DMA_MR_16 5 100#define DMA_MR_20 6 101#define DMA_MR_32 7 102 103/* DMA Burst Length in bytes */ 104#define DMA_BL_16 0 105#define DMA_BL_32 1 106#define DMA_BL_64 2 107#define DMA_BL_128 3 108#define DMA_BL_256 4 109#define DMA_BL_512 5 110#define DMA_BL_1024 6 111 112/* Prefetch control */ 113#define DMA_PC_0 0 114#define DMA_PC_4 1 115#define DMA_PC_8 2 116#define DMA_PC_16 3 117/* others: reserved */ 118 119/* Prefetch threshold */ 120#define DMA_PT_1 0 121#define DMA_PT_2 1 122#define DMA_PT_4 2 123#define DMA_PT_8 3 124 125/* transmit descriptor table pointer */ 126#define XP_LD_MASK 0xfff /* last valid descriptor */ 127 128/* transmit channel status */ 129#define XS_CD_MASK 0x0fff /* current descriptor pointer */ 130#define XS_XS_MASK 0xf000 /* transmit state */ 131#define XS_XS_SHIFT 12 132#define XS_XS_DISABLED 0x0000 /* disabled */ 133#define XS_XS_ACTIVE 0x1000 /* active */ 134#define XS_XS_IDLE 0x2000 /* idle wait */ 135#define XS_XS_STOPPED 0x3000 /* stopped */ 136#define XS_XS_SUSP 0x4000 /* suspend pending */ 137#define XS_XE_MASK 0xf0000 /* transmit errors */ 138#define XS_XE_SHIFT 16 139#define XS_XE_NOERR 0x00000 /* no error */ 140#define XS_XE_DPE 0x10000 /* descriptor protocol error */ 141#define XS_XE_DFU 0x20000 /* data fifo underrun */ 142#define XS_XE_BEBR 0x30000 /* bus error on buffer read */ 143#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */ 144#define XS_AD_MASK 0xfff00000 /* active descriptor */ 145#define XS_AD_SHIFT 20 146 147/* receive channel control */ 148#define RC_RE ((uint32)1 << 0) /* receive enable */ 149#define RC_RO_MASK 0xfe /* receive frame offset */ 150#define RC_RO_SHIFT 1 151#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */ 152#define RC_SH ((uint32)1 << 9) /* separate rx header descriptor enable */ 153#define RC_OC ((uint32)1 << 10) /* overflow continue */ 154#define RC_PD ((uint32)1 << 11) /* parity check disable */ 155#define RC_AE ((uint32)3 << 16) /* address extension bits */ 156#define RC_AE_SHIFT 16 157#define RC_BL_MASK 0x001C0000 /* BurstLen bits */ 158#define RC_BL_SHIFT 18 159#define RC_PC_MASK 0x00E00000 /* Prefetch control */ 160#define RC_PC_SHIFT 21 161#define RC_PT_MASK 0x03000000 /* Prefetch threshold */ 162#define RC_PT_SHIFT 24 163 164/* receive descriptor table pointer */ 165#define RP_LD_MASK 0xfff /* last valid descriptor */ 166 167/* receive channel status */ 168#define RS_CD_MASK 0x0fff /* current descriptor pointer */ 169#define RS_RS_MASK 0xf000 /* receive state */ 170#define RS_RS_SHIFT 12 171#define RS_RS_DISABLED 0x0000 /* disabled */ 172#define RS_RS_ACTIVE 0x1000 /* active */ 173#define RS_RS_IDLE 0x2000 /* idle wait */ 174#define RS_RS_STOPPED 0x3000 /* reserved */ 175#define RS_RE_MASK 0xf0000 /* receive errors */ 176#define RS_RE_SHIFT 16 177#define RS_RE_NOERR 0x00000 /* no error */ 178#define RS_RE_DPE 0x10000 /* descriptor protocol error */ 179#define RS_RE_DFO 0x20000 /* data fifo overflow */ 180#define RS_RE_BEBW 0x30000 /* bus error on buffer write */ 181#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */ 182#define RS_AD_MASK 0xfff00000 /* active descriptor */ 183#define RS_AD_SHIFT 20 184 185/* fifoaddr */ 186#define FA_OFF_MASK 0xffff /* offset */ 187#define FA_SEL_MASK 0xf0000 /* select */ 188#define FA_SEL_SHIFT 16 189#define FA_SEL_XDD 0x00000 /* transmit dma data */ 190#define FA_SEL_XDP 0x10000 /* transmit dma pointers */ 191#define FA_SEL_RDD 0x40000 /* receive dma data */ 192#define FA_SEL_RDP 0x50000 /* receive dma pointers */ 193#define FA_SEL_XFD 0x80000 /* transmit fifo data */ 194#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */ 195#define FA_SEL_RFD 0xc0000 /* receive fifo data */ 196#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */ 197#define FA_SEL_RSD 0xe0000 /* receive frame status data */ 198#define FA_SEL_RSP 0xf0000 /* receive frame status pointers */ 199 200/* descriptor control flags */ 201#define CTRL_BC_MASK 0x00001fff /* buffer byte count, real data len must <= 4KB */ 202#define CTRL_AE ((uint32)3 << 16) /* address extension bits */ 203#define CTRL_AE_SHIFT 16 204#define CTRL_PARITY ((uint32)3 << 18) /* parity bit */ 205#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */ 206#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */ 207#define CTRL_EOF ((uint32)1 << 30) /* end of frame */ 208#define CTRL_SOF ((uint32)1 << 31) /* start of frame */ 209 210/* control flags in the range [27:20] are core-specific and not defined here */ 211#define CTRL_CORE_MASK 0x0ff00000 212 213/* 64 bits addressing */ 214 215/* dma registers per channel(xmt or rcv) */ 216typedef volatile struct { 217 uint32 control; /* enable, et al */ 218 uint32 ptr; /* last descriptor posted to chip */ 219 uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */ 220 uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */ 221 uint32 status0; /* current descriptor, xmt state */ 222 uint32 status1; /* active descriptor, xmt error */ 223} dma64regs_t; 224 225typedef volatile struct { 226 dma64regs_t tx; /* dma64 tx channel */ 227 dma64regs_t rx; /* dma64 rx channel */ 228} dma64regp_t; 229 230typedef volatile struct { /* diag access */ 231 uint32 fifoaddr; /* diag address */ 232 uint32 fifodatalow; /* low 32bits of data */ 233 uint32 fifodatahigh; /* high 32bits of data */ 234 uint32 pad; /* reserved */ 235} dma64diag_t; 236 237/* 238 * DMA Descriptor 239 * Descriptors are only read by the hardware, never written back. 240 */ 241typedef volatile struct { 242 uint32 ctrl1; /* misc control bits */ 243 uint32 ctrl2; /* buffer count and address extension */ 244 uint32 addrlow; /* memory address of the date buffer, bits 31:0 */ 245 uint32 addrhigh; /* memory address of the date buffer, bits 63:32 */ 246} dma64dd_t; 247 248/* 249 * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss. 250 */ 251#define D64RINGALIGN_BITS 13 252#define D64MAXRINGSZ (1 << D64RINGALIGN_BITS) 253#define D64RINGBOUNDARY (1 << D64RINGALIGN_BITS) 254 255#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t)) 256 257/* for cores with large descriptor ring support, descriptor ring size can be up to 4096 */ 258#define D64MAXDD_LARGE ((1 << 16) / sizeof (dma64dd_t)) 259 260/* for cores with large descriptor ring support (4k descriptors), descriptor ring cannot cross 261 * 64K boundary 262 */ 263#define D64RINGBOUNDARY_LARGE (1 << 16) 264 265/* 266 * Default DMA Burstlen values for USBRev >= 12 and SDIORev >= 11. 267 * When this field contains the value N, the burst length is 2**(N + 4) bytes. 268 */ 269#define D64_DEF_USBBURSTLEN 2 270#define D64_DEF_SDIOBURSTLEN 1 271 272 273#ifndef D64_USBBURSTLEN 274#define D64_USBBURSTLEN DMA_BL_64 275#endif 276#ifndef D64_SDIOBURSTLEN 277#define D64_SDIOBURSTLEN DMA_BL_32 278#endif 279 280/* transmit channel control */ 281#define D64_XC_XE 0x00000001 /* transmit enable */ 282#define D64_XC_SE 0x00000002 /* transmit suspend request */ 283#define D64_XC_LE 0x00000004 /* loopback enable */ 284#define D64_XC_FL 0x00000010 /* flush request */ 285 286/* XX: followng ifdef is added just to avoid the ROM abandon on 4345B0 */ 287#ifdef USE_4345B0_MR_MASK_2BITS_IN_ROM 288#define D64_XC_MR_MASK 0x000000C0 /* Multiple outstanding reads */ 289#else /* USE_4345B0_MR_MASK_2BITS_IN_ROM */ 290#define D64_XC_MR_MASK 0x000001C0 /* Multiple outstanding reads */ 291#endif /* USE_4345B0_MR_MASK_2BITS_IN_ROM */ 292 293#define D64_XC_MR_SHIFT 6 294#define D64_XC_PD 0x00000800 /* parity check disable */ 295#define D64_XC_AE 0x00030000 /* address extension bits */ 296#define D64_XC_AE_SHIFT 16 297#define D64_XC_BL_MASK 0x001C0000 /* BurstLen bits */ 298#define D64_XC_BL_SHIFT 18 299#define D64_XC_PC_MASK 0x00E00000 /* Prefetch control */ 300#define D64_XC_PC_SHIFT 21 301#define D64_XC_PT_MASK 0x03000000 /* Prefetch threshold */ 302#define D64_XC_PT_SHIFT 24 303 304/* transmit descriptor table pointer */ 305#define D64_XP_LD_MASK 0x00001fff /* last valid descriptor */ 306 307/* transmit channel status */ 308#define D64_XS0_CD_MASK (di->d64_xs0_cd_mask) /* current descriptor pointer */ 309#define D64_XS0_XS_MASK 0xf0000000 /* transmit state */ 310#define D64_XS0_XS_SHIFT 28 311#define D64_XS0_XS_DISABLED 0x00000000 /* disabled */ 312#define D64_XS0_XS_ACTIVE 0x10000000 /* active */ 313#define D64_XS0_XS_IDLE 0x20000000 /* idle wait */ 314#define D64_XS0_XS_STOPPED 0x30000000 /* stopped */ 315#define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */ 316 317#define D64_XS1_AD_MASK (di->d64_xs1_ad_mask) /* active descriptor */ 318#define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */ 319#define D64_XS1_XE_SHIFT 28 320#define D64_XS1_XE_NOERR 0x00000000 /* no error */ 321#define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */ 322#define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */ 323#define D64_XS1_XE_DTE 0x30000000 /* data transfer error */ 324#define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */ 325#define D64_XS1_XE_COREE 0x50000000 /* core error */ 326 327/* receive channel control */ 328#define D64_RC_RE 0x00000001 /* receive enable */ 329#define D64_RC_RO_MASK 0x000000fe /* receive frame offset */ 330#define D64_RC_RO_SHIFT 1 331#define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */ 332#define D64_RC_SH 0x00000200 /* separate rx header descriptor enable */ 333#define D64_RC_SHIFT 9 /* separate rx header descriptor enable */ 334#define D64_RC_OC 0x00000400 /* overflow continue */ 335#define D64_RC_PD 0x00000800 /* parity check disable */ 336#define D64_RC_SA 0x00002000 /* select active */ 337#define D64_RC_GE 0x00004000 /* Glom enable */ 338#define D64_RC_AE 0x00030000 /* address extension bits */ 339#define D64_RC_AE_SHIFT 16 340#define D64_RC_BL_MASK 0x001C0000 /* BurstLen bits */ 341#define D64_RC_BL_SHIFT 18 342#define D64_RC_PC_MASK 0x00E00000 /* Prefetch control */ 343#define D64_RC_PC_SHIFT 21 344#define D64_RC_PT_MASK 0x03000000 /* Prefetch threshold */ 345#define D64_RC_PT_SHIFT 24 346 347/* flags for dma controller */ 348#define DMA_CTRL_PEN (1 << 0) /* partity enable */ 349#define DMA_CTRL_ROC (1 << 1) /* rx overflow continue */ 350#define DMA_CTRL_RXMULTI (1 << 2) /* allow rx scatter to multiple descriptors */ 351#define DMA_CTRL_UNFRAMED (1 << 3) /* Unframed Rx/Tx data */ 352#define DMA_CTRL_USB_BOUNDRY4KB_WAR (1 << 4) 353#define DMA_CTRL_DMA_AVOIDANCE_WAR (1 << 5) /* DMA avoidance WAR for 4331 */ 354#define DMA_CTRL_RXSINGLE (1 << 6) /* always single buffer */ 355#define DMA_CTRL_SDIO_RXGLOM (1 << 7) /* DMA Rx glome is supported */ 356/* receive descriptor table pointer */ 357#define D64_RP_LD_MASK 0x00001fff /* last valid descriptor */ 358 359/* receive channel status */ 360#define D64_RS0_CD_MASK (di->d64_rs0_cd_mask) /* current descriptor pointer */ 361#define D64_RS0_RS_MASK 0xf0000000 /* receive state */ 362#define D64_RS0_RS_SHIFT 28 363#define D64_RS0_RS_DISABLED 0x00000000 /* disabled */ 364#define D64_RS0_RS_ACTIVE 0x10000000 /* active */ 365#define D64_RS0_RS_IDLE 0x20000000 /* idle wait */ 366#define D64_RS0_RS_STOPPED 0x30000000 /* stopped */ 367#define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */ 368 369#define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */ 370#define D64_RS1_RE_MASK 0xf0000000 /* receive errors */ 371#define D64_RS1_RE_SHIFT 28 372#define D64_RS1_RE_NOERR 0x00000000 /* no error */ 373#define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */ 374#define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */ 375#define D64_RS1_RE_DTE 0x30000000 /* data transfer error */ 376#define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */ 377#define D64_RS1_RE_COREE 0x50000000 /* core error */ 378 379/* fifoaddr */ 380#define D64_FA_OFF_MASK 0xffff /* offset */ 381#define D64_FA_SEL_MASK 0xf0000 /* select */ 382#define D64_FA_SEL_SHIFT 16 383#define D64_FA_SEL_XDD 0x00000 /* transmit dma data */ 384#define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */ 385#define D64_FA_SEL_RDD 0x40000 /* receive dma data */ 386#define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */ 387#define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */ 388#define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */ 389#define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */ 390#define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */ 391#define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */ 392#define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */ 393 394/* descriptor control flags 1 */ 395#define D64_CTRL_COREFLAGS 0x0ff00000 /* core specific flags */ 396#define D64_CTRL1_NOTPCIE ((uint32)1 << 18) /* buirst size control */ 397#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */ 398#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */ 399#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */ 400#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */ 401 402/* descriptor control flags 2 */ 403#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count. real data len must <= 16KB */ 404#define D64_CTRL2_AE 0x00030000 /* address extension bits */ 405#define D64_CTRL2_AE_SHIFT 16 406#define D64_CTRL2_PARITY 0x00040000 /* parity bit */ 407 408/* control flags in the range [27:20] are core-specific and not defined here */ 409#define D64_CTRL_CORE_MASK 0x0ff00000 410 411#define D64_RX_FRM_STS_LEN 0x0000ffff /* frame length mask */ 412#define D64_RX_FRM_STS_OVFL 0x00800000 /* RxOverFlow */ 413#define D64_RX_FRM_STS_DSCRCNT 0x0f000000 /* no. of descriptors used - 1, d11corerev >= 22 */ 414#define D64_RX_FRM_STS_DATATYPE 0xf0000000 /* core-dependent data type */ 415 416/* receive frame status */ 417typedef volatile struct { 418 uint16 len; 419 uint16 flags; 420} dma_rxh_t; 421 422#endif /* _sbhnddma_h_ */ 423