1/* 2 * SiliconBackplane Chipcommon core hardware definitions. 3 * 4 * The chipcommon core provides chip identification, SB control, 5 * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer, 6 * GPIO interface, extbus, and support for serial and parallel flashes. 7 * 8 * $Id: sbchipc.h 468895 2014-04-09 02:33:06Z $ 9 * 10 * Copyright (C) 2015, Broadcom Corporation. All Rights Reserved. 11 * 12 * Permission to use, copy, modify, and/or distribute this software for any 13 * purpose with or without fee is hereby granted, provided that the above 14 * copyright notice and this permission notice appear in all copies. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 17 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 20 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 21 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 22 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 23 */ 24 25#ifndef _SBCHIPC_H 26#define _SBCHIPC_H 27 28#if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) 29 30/* cpp contortions to concatenate w/arg prescan */ 31#ifndef PAD 32#define _PADLINE(line) pad ## line 33#define _XSTR(line) _PADLINE(line) 34#define PAD _XSTR(__LINE__) 35#endif /* PAD */ 36 37/** 38 * In chipcommon rev 49 the pmu registers have been moved from chipc to the pmu core if the 39 * 'AOBPresent' bit of 'CoreCapabilitiesExt' is set. If this field is set, the traditional chipc to 40 * [pmu|gci|sreng] register interface is deprecated and removed. These register blocks would instead 41 * be assigned their respective chipc-specific address space and connected to the Always On 42 * Backplane via the APB interface. 43 */ 44typedef volatile struct { 45 uint32 PAD[384]; 46 uint32 pmucontrol; /* 0x600 */ 47 uint32 pmucapabilities; 48 uint32 pmustatus; 49 uint32 res_state; 50 uint32 res_pending; 51 uint32 pmutimer; 52 uint32 min_res_mask; 53 uint32 max_res_mask; 54 uint32 res_table_sel; 55 uint32 res_dep_mask; 56 uint32 res_updn_timer; 57 uint32 res_timer; 58 uint32 clkstretch; 59 uint32 pmuwatchdog; 60 uint32 gpiosel; /* 0x638, rev >= 1 */ 61 uint32 gpioenable; /* 0x63c, rev >= 1 */ 62 uint32 res_req_timer_sel; 63 uint32 res_req_timer; 64 uint32 res_req_mask; 65 uint32 PAD; 66 uint32 chipcontrol_addr; /* 0x650 */ 67 uint32 chipcontrol_data; /* 0x654 */ 68 uint32 regcontrol_addr; 69 uint32 regcontrol_data; 70 uint32 pllcontrol_addr; 71 uint32 pllcontrol_data; 72 uint32 pmustrapopt; /* 0x668, corerev >= 28 */ 73 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ 74 uint32 retention_ctl; /* 0x670 */ 75 uint32 PAD[3]; 76 uint32 retention_grpidx; /* 0x680 */ 77 uint32 retention_grpctl; /* 0x684 */ 78 uint32 PAD[20]; 79 uint32 pmucontrol_ext; /* 0x6d8 */ 80 uint32 slowclkperiod; /* 0x6dc */ 81 uint32 PAD[8]; 82 uint32 pmuintmask0; /* 0x700 */ 83 uint32 pmuintmask1; /* 0x704 */ 84 uint32 PAD[14]; 85 uint32 pmuintstatus; /* 0x740 */ 86} pmuregs_t; 87 88typedef struct eci_prerev35 { 89 uint32 eci_output; 90 uint32 eci_control; 91 uint32 eci_inputlo; 92 uint32 eci_inputmi; 93 uint32 eci_inputhi; 94 uint32 eci_inputintpolaritylo; 95 uint32 eci_inputintpolaritymi; 96 uint32 eci_inputintpolarityhi; 97 uint32 eci_intmasklo; 98 uint32 eci_intmaskmi; 99 uint32 eci_intmaskhi; 100 uint32 eci_eventlo; 101 uint32 eci_eventmi; 102 uint32 eci_eventhi; 103 uint32 eci_eventmasklo; 104 uint32 eci_eventmaskmi; 105 uint32 eci_eventmaskhi; 106 uint32 PAD[3]; 107} eci_prerev35_t; 108 109typedef struct eci_rev35 { 110 uint32 eci_outputlo; 111 uint32 eci_outputhi; 112 uint32 eci_controllo; 113 uint32 eci_controlhi; 114 uint32 eci_inputlo; 115 uint32 eci_inputhi; 116 uint32 eci_inputintpolaritylo; 117 uint32 eci_inputintpolarityhi; 118 uint32 eci_intmasklo; 119 uint32 eci_intmaskhi; 120 uint32 eci_eventlo; 121 uint32 eci_eventhi; 122 uint32 eci_eventmasklo; 123 uint32 eci_eventmaskhi; 124 uint32 eci_auxtx; 125 uint32 eci_auxrx; 126 uint32 eci_datatag; 127 uint32 eci_uartescvalue; 128 uint32 eci_autobaudctr; 129 uint32 eci_uartfifolevel; 130} eci_rev35_t; 131 132typedef struct flash_config { 133 uint32 PAD[19]; 134 /* Flash struct configuration registers (0x18c) for BCM4706 (corerev = 31) */ 135 uint32 flashstrconfig; 136} flash_config_t; 137 138typedef volatile struct { 139 uint32 chipid; /* 0x0 */ 140 uint32 capabilities; 141 uint32 corecontrol; /* corerev >= 1 */ 142 uint32 bist; 143 144 /* OTP */ 145 uint32 otpstatus; /* 0x10, corerev >= 10 */ 146 uint32 otpcontrol; 147 uint32 otpprog; 148 uint32 otplayout; /* corerev >= 23 */ 149 150 /* Interrupt control */ 151 uint32 intstatus; /* 0x20 */ 152 uint32 intmask; 153 154 /* Chip specific regs */ 155 uint32 chipcontrol; /* 0x28, rev >= 11 */ 156 uint32 chipstatus; /* 0x2c, rev >= 11 */ 157 158 /* Jtag Master */ 159 uint32 jtagcmd; /* 0x30, rev >= 10 */ 160 uint32 jtagir; 161 uint32 jtagdr; 162 uint32 jtagctrl; 163 164 /* serial flash interface registers */ 165 uint32 flashcontrol; /* 0x40 */ 166 uint32 flashaddress; 167 uint32 flashdata; 168 uint32 otplayoutextension; /* rev >= 35 */ 169 170 /* Silicon backplane configuration broadcast control */ 171 uint32 broadcastaddress; /* 0x50 */ 172 uint32 broadcastdata; 173 174 /* gpio - cleared only by power-on-reset */ 175 uint32 gpiopullup; /* 0x58, corerev >= 20 */ 176 uint32 gpiopulldown; /* 0x5c, corerev >= 20 */ 177 uint32 gpioin; /* 0x60 */ 178 uint32 gpioout; /* 0x64 */ 179 uint32 gpioouten; /* 0x68 */ 180 uint32 gpiocontrol; /* 0x6C */ 181 uint32 gpiointpolarity; /* 0x70 */ 182 uint32 gpiointmask; /* 0x74 */ 183 184 /* GPIO events corerev >= 11 */ 185 uint32 gpioevent; 186 uint32 gpioeventintmask; 187 188 /* Watchdog timer */ 189 uint32 watchdog; /* 0x80 */ 190 191 /* GPIO events corerev >= 11 */ 192 uint32 gpioeventintpolarity; 193 194 /* GPIO based LED powersave registers corerev >= 16 */ 195 uint32 gpiotimerval; /* 0x88 */ 196 uint32 gpiotimeroutmask; 197 198 /* clock control */ 199 uint32 clockcontrol_n; /* 0x90 */ 200 uint32 clockcontrol_sb; /* aka m0 */ 201 uint32 clockcontrol_pci; /* aka m1 */ 202 uint32 clockcontrol_m2; /* mii/uart/mipsref */ 203 uint32 clockcontrol_m3; /* cpu */ 204 uint32 clkdiv; /* corerev >= 3 */ 205 uint32 gpiodebugsel; /* corerev >= 28 */ 206 uint32 capabilities_ext; /* 0xac */ 207 208 /* pll delay registers (corerev >= 4) */ 209 uint32 pll_on_delay; /* 0xb0 */ 210 uint32 fref_sel_delay; 211 uint32 slow_clk_ctl; /* 5 < corerev < 10 */ 212 uint32 PAD; 213 214 /* Instaclock registers (corerev >= 10) */ 215 uint32 system_clk_ctl; /* 0xc0 */ 216 uint32 clkstatestretch; 217 uint32 PAD[2]; 218 219 /* Indirect backplane access (corerev >= 22) */ 220 uint32 bp_addrlow; /* 0xd0 */ 221 uint32 bp_addrhigh; 222 uint32 bp_data; 223 uint32 PAD; 224 uint32 bp_indaccess; 225 /* SPI registers, corerev >= 37 */ 226 uint32 gsioctrl; 227 uint32 gsioaddress; 228 uint32 gsiodata; 229 230 /* More clock dividers (corerev >= 32) */ 231 uint32 clkdiv2; 232 /* FAB ID (corerev >= 40) */ 233 uint32 otpcontrol1; 234 uint32 fabid; /* 0xf8 */ 235 236 /* In AI chips, pointer to erom */ 237 uint32 eromptr; /* 0xfc */ 238 239 /* ExtBus control registers (corerev >= 3) */ 240 uint32 pcmcia_config; /* 0x100 */ 241 uint32 pcmcia_memwait; 242 uint32 pcmcia_attrwait; 243 uint32 pcmcia_iowait; 244 uint32 ide_config; 245 uint32 ide_memwait; 246 uint32 ide_attrwait; 247 uint32 ide_iowait; 248 uint32 prog_config; 249 uint32 prog_waitcount; 250 uint32 flash_config; 251 uint32 flash_waitcount; 252 uint32 SECI_config; /* 0x130 SECI configuration */ 253 uint32 SECI_status; 254 uint32 SECI_statusmask; 255 uint32 SECI_rxnibchanged; 256 257 union { /* 0x140 */ 258 /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */ 259 struct eci_prerev35 lt35; 260 struct eci_rev35 ge35; 261 /* Other interfaces */ 262 struct flash_config flashconf; 263 uint32 PAD[20]; 264 } eci; 265 266 /* SROM interface (corerev >= 32) */ 267 uint32 sromcontrol; /* 0x190 */ 268 uint32 sromaddress; 269 uint32 sromdata; 270 uint32 PAD[1]; /* 0x19C */ 271 /* NAND flash registers for BCM4706 (corerev = 31) */ 272 uint32 nflashctrl; /* 0x1a0 */ 273 uint32 nflashconf; 274 uint32 nflashcoladdr; 275 uint32 nflashrowaddr; 276 uint32 nflashdata; 277 uint32 nflashwaitcnt0; /* 0x1b4 */ 278 uint32 PAD[2]; 279 280 uint32 seci_uart_data; /* 0x1C0 */ 281 uint32 seci_uart_bauddiv; 282 uint32 seci_uart_fcr; 283 uint32 seci_uart_lcr; 284 uint32 seci_uart_mcr; 285 uint32 seci_uart_lsr; 286 uint32 seci_uart_msr; 287 uint32 seci_uart_baudadj; 288 /* Clock control and hardware workarounds (corerev >= 20) */ 289 uint32 clk_ctl_st; /* 0x1e0 */ 290 uint32 hw_war; 291 uint32 PAD[70]; 292 293 /* UARTs */ 294 uint8 uart0data; /* 0x300 */ 295 uint8 uart0imr; 296 uint8 uart0fcr; 297 uint8 uart0lcr; 298 uint8 uart0mcr; 299 uint8 uart0lsr; 300 uint8 uart0msr; 301 uint8 uart0scratch; 302 uint8 PAD[248]; /* corerev >= 1 */ 303 304 uint8 uart1data; /* 0x400 */ 305 uint8 uart1imr; 306 uint8 uart1fcr; 307 uint8 uart1lcr; 308 uint8 uart1mcr; 309 uint8 uart1lsr; 310 uint8 uart1msr; 311 uint8 uart1scratch; /* 0x407 */ 312 uint32 PAD[62]; 313 314 /* save/restore, corerev >= 48 */ 315 uint32 sr_capability; /* 0x500 */ 316 uint32 sr_control0; /* 0x504 */ 317 uint32 sr_control1; /* 0x508 */ 318 uint32 gpio_control; /* 0x50C */ 319 uint32 PAD[60]; 320 321 /* PMU registers (corerev >= 20) */ 322 /* Note: all timers driven by ILP clock are updated asynchronously to HT/ALP. 323 * The CPU must read them twice, compare, and retry if different. 324 */ 325 uint32 pmucontrol; /* 0x600 */ 326 uint32 pmucapabilities; 327 uint32 pmustatus; 328 uint32 res_state; 329 uint32 res_pending; 330 uint32 pmutimer; 331 uint32 min_res_mask; 332 uint32 max_res_mask; 333 uint32 res_table_sel; 334 uint32 res_dep_mask; 335 uint32 res_updn_timer; 336 uint32 res_timer; 337 uint32 clkstretch; 338 uint32 pmuwatchdog; 339 uint32 gpiosel; /* 0x638, rev >= 1 */ 340 uint32 gpioenable; /* 0x63c, rev >= 1 */ 341 uint32 res_req_timer_sel; 342 uint32 res_req_timer; 343 uint32 res_req_mask; 344 uint32 PAD; 345 uint32 chipcontrol_addr; /* 0x650 */ 346 uint32 chipcontrol_data; /* 0x654 */ 347 uint32 regcontrol_addr; 348 uint32 regcontrol_data; 349 uint32 pllcontrol_addr; 350 uint32 pllcontrol_data; 351 uint32 pmustrapopt; /* 0x668, corerev >= 28 */ 352 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ 353 uint32 retention_ctl; /* 0x670 */ 354 uint32 PAD[3]; 355 uint32 retention_grpidx; /* 0x680 */ 356 uint32 retention_grpctl; /* 0x684 */ 357 uint32 PAD[20]; 358 uint32 pmucontrol_ext; /* 0x6d8 */ 359 uint32 slowclkperiod; /* 0x6dc */ 360 uint32 PAD[8]; 361 uint32 pmuintmask0; /* 0x700 */ 362 uint32 pmuintmask1; /* 0x704 */ 363 uint32 PAD[14]; 364 uint32 pmuintstatus; /* 0x740 */ 365 uint32 PAD[47]; 366 uint16 sromotp[512]; /* 0x800 */ 367#ifdef NFLASH_SUPPORT 368 /* Nand flash MLC controller registers (corerev >= 38) */ 369 uint32 nand_revision; /* 0xC00 */ 370 uint32 nand_cmd_start; 371 uint32 nand_cmd_addr_x; 372 uint32 nand_cmd_addr; 373 uint32 nand_cmd_end_addr; 374 uint32 nand_cs_nand_select; 375 uint32 nand_cs_nand_xor; 376 uint32 PAD; 377 uint32 nand_spare_rd0; 378 uint32 nand_spare_rd4; 379 uint32 nand_spare_rd8; 380 uint32 nand_spare_rd12; 381 uint32 nand_spare_wr0; 382 uint32 nand_spare_wr4; 383 uint32 nand_spare_wr8; 384 uint32 nand_spare_wr12; 385 uint32 nand_acc_control; 386 uint32 PAD; 387 uint32 nand_config; 388 uint32 PAD; 389 uint32 nand_timing_1; 390 uint32 nand_timing_2; 391 uint32 nand_semaphore; 392 uint32 PAD; 393 uint32 nand_devid; 394 uint32 nand_devid_x; 395 uint32 nand_block_lock_status; 396 uint32 nand_intfc_status; 397 uint32 nand_ecc_corr_addr_x; 398 uint32 nand_ecc_corr_addr; 399 uint32 nand_ecc_unc_addr_x; 400 uint32 nand_ecc_unc_addr; 401 uint32 nand_read_error_count; 402 uint32 nand_corr_stat_threshold; 403 uint32 PAD[2]; 404 uint32 nand_read_addr_x; 405 uint32 nand_read_addr; 406 uint32 nand_page_program_addr_x; 407 uint32 nand_page_program_addr; 408 uint32 nand_copy_back_addr_x; 409 uint32 nand_copy_back_addr; 410 uint32 nand_block_erase_addr_x; 411 uint32 nand_block_erase_addr; 412 uint32 nand_inv_read_addr_x; 413 uint32 nand_inv_read_addr; 414 uint32 PAD[2]; 415 uint32 nand_blk_wr_protect; 416 uint32 PAD[3]; 417 uint32 nand_acc_control_cs1; 418 uint32 nand_config_cs1; 419 uint32 nand_timing_1_cs1; 420 uint32 nand_timing_2_cs1; 421 uint32 PAD[20]; 422 uint32 nand_spare_rd16; 423 uint32 nand_spare_rd20; 424 uint32 nand_spare_rd24; 425 uint32 nand_spare_rd28; 426 uint32 nand_cache_addr; 427 uint32 nand_cache_data; 428 uint32 nand_ctrl_config; 429 uint32 nand_ctrl_status; 430#endif /* NFLASH_SUPPORT */ 431 uint32 gci_corecaps0; /* GCI starting at 0xC00 */ 432 uint32 gci_corecaps1; 433 uint32 gci_corecaps2; 434 uint32 gci_corectrl; 435 uint32 gci_corestat; /* 0xC10 */ 436 uint32 gci_intstat; /* 0xC14 */ 437 uint32 gci_intmask; /* 0xC18 */ 438 uint32 gci_wakemask; /* 0xC1C */ 439 uint32 gci_levelintstat; /* 0xC20 */ 440 uint32 gci_eventintstat; /* 0xC24 */ 441 uint32 PAD[6]; 442 uint32 gci_indirect_addr; /* 0xC40 */ 443 uint32 gci_gpioctl; /* 0xC44 */ 444 uint32 gci_gpiostatus; 445 uint32 gci_gpiomask; /* 0xC4C */ 446 uint32 PAD; 447 uint32 gci_miscctl; /* 0xC54 */ 448 uint32 gci_gpiointmask; 449 uint32 gci_gpiowakemask; 450 uint32 gci_input[32]; /* C60 */ 451 uint32 gci_event[32]; /* CE0 */ 452 uint32 gci_output[4]; /* D60 */ 453 uint32 gci_control_0; /* 0xD70 */ 454 uint32 gci_control_1; /* 0xD74 */ 455 uint32 gci_level_polreg; /* 0xD78 */ 456 uint32 gci_levelintmask; /* 0xD7C */ 457 uint32 gci_eventintmask; /* 0xD80 */ 458 uint32 PAD[3]; 459 uint32 gci_inbandlevelintmask; /* 0xD90 */ 460 uint32 gci_inbandeventintmask; /* 0xD94 */ 461 uint32 PAD[2]; 462 uint32 gci_seciauxtx; /* 0xDA0 */ 463 uint32 gci_seciauxrx; /* 0xDA4 */ 464 uint32 gci_secitx_datatag; /* 0xDA8 */ 465 uint32 gci_secirx_datatag; /* 0xDAC */ 466 uint32 gci_secitx_datamask; /* 0xDB0 */ 467 uint32 gci_seciusef0tx_reg; /* 0xDB4 */ 468 uint32 gci_secif0tx_offset; /* 0xDB8 */ 469 uint32 gci_secif0rx_offset; /* 0xDBC */ 470 uint32 gci_secif1tx_offset; /* 0xDC0 */ 471 uint32 gci_rxfifo_common_ctrl; /* 0xDC4 */ 472 uint32 gci_rxfifoctrl; /* 0xDC8 */ 473 uint32 gci_uartreadid; /* DCC */ 474 uint32 gci_uartescval; /* DD0 */ 475 uint32 PAD; 476 uint32 gci_secififolevel; /* DD8 */ 477 uint32 gci_seciuartdata; /* DDC */ 478 uint32 gci_secibauddiv; /* DE0 */ 479 uint32 gci_secifcr; /* DE4 */ 480 uint32 gci_secilcr; /* DE8 */ 481 uint32 gci_secimcr; /* DEC */ 482 uint32 gci_secilsr; /* DF0 */ 483 uint32 gci_secimsr; /* DF4 */ 484 uint32 gci_baudadj; /* DF8 */ 485 uint32 PAD; 486 uint32 gci_chipctrl; /* 0xE00 */ 487 uint32 gci_chipsts; /* 0xE04 */ 488} chipcregs_t; 489 490#endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */ 491 492#if defined(IL_BIGENDIAN) && defined(BCMHND74K) 493/* Selective swapped defines for those registers we need in 494 * big-endian code. 495 */ 496#define CC_CHIPID 4 497#define CC_CAPABILITIES 0 498#define CC_CHIPST 0x28 499#define CC_EROMPTR 0xf8 500 501#else /* !IL_BIGENDIAN || !BCMHND74K */ 502 503#define CC_CHIPID 0 504#define CC_CAPABILITIES 4 505#define CC_CHIPST 0x2c 506#define CC_EROMPTR 0xfc 507 508#endif /* IL_BIGENDIAN && BCMHND74K */ 509 510#define CC_OTPST 0x10 511#define CC_JTAGCMD 0x30 512#define CC_JTAGIR 0x34 513#define CC_JTAGDR 0x38 514#define CC_JTAGCTRL 0x3c 515#define CC_GPIOPU 0x58 516#define CC_GPIOPD 0x5c 517#define CC_GPIOIN 0x60 518#define CC_GPIOOUT 0x64 519#define CC_GPIOOUTEN 0x68 520#define CC_GPIOCTRL 0x6c 521#define CC_GPIOPOL 0x70 522#define CC_GPIOINTM 0x74 523#define CC_WATCHDOG 0x80 524#define CC_CLKC_N 0x90 525#define CC_CLKC_M0 0x94 526#define CC_CLKC_M1 0x98 527#define CC_CLKC_M2 0x9c 528#define CC_CLKC_M3 0xa0 529#define CC_CLKDIV 0xa4 530#define CC_SYS_CLK_CTL 0xc0 531#define CC_CLK_CTL_ST SI_CLK_CTL_ST 532#define PMU_CTL 0x600 533#define PMU_CAP 0x604 534#define PMU_ST 0x608 535#define PMU_RES_STATE 0x60c 536#define PMU_RES_PENDING 0x610 537#define PMU_TIMER 0x614 538#define PMU_MIN_RES_MASK 0x618 539#define PMU_MAX_RES_MASK 0x61c 540#define CC_CHIPCTL_ADDR 0x650 541#define CC_CHIPCTL_DATA 0x654 542#define PMU_REG_CONTROL_ADDR 0x658 543#define PMU_REG_CONTROL_DATA 0x65C 544#define PMU_PLL_CONTROL_ADDR 0x660 545#define PMU_PLL_CONTROL_DATA 0x664 546#define CC_SROM_CTRL 0x190 547#define CC_SROM_OTP 0x800 /* SROM/OTP address space */ 548#define CC_GCI_INDIRECT_ADDR_REG 0xC40 549#define CC_GCI_CHIP_CTRL_REG 0xE00 550#define CC_GCI_CC_OFFSET_2 2 551#define CC_GCI_CC_OFFSET_5 5 552 553#define CHIPCTRLREG0 0x0 554#define CHIPCTRLREG1 0x1 555#define CHIPCTRLREG2 0x2 556#define CHIPCTRLREG3 0x3 557#define CHIPCTRLREG4 0x4 558#define CHIPCTRLREG5 0x5 559#define CHIPCTRLREG6 0x6 560#define REGCTRLREG4 0x4 561#define REGCTRLREG5 0x5 562#define REGCTRLREG6 0x6 563#define MINRESMASKREG 0x618 564#define MAXRESMASKREG 0x61c 565#define CHIPCTRLADDR 0x650 566#define CHIPCTRLDATA 0x654 567#define RSRCTABLEADDR 0x620 568#define PMU_RES_DEP_MASK 0x624 569#define RSRCUPDWNTIME 0x628 570#define PMUREG_RESREQ_MASK 0x68c 571#define EXT_LPO_AVAIL 0x100 572#define LPO_SEL (1 << 0) 573#define CC_EXT_LPO_PU 0x200000 574#define GC_EXT_LPO_PU 0x2 575#define CC_INT_LPO_PU 0x100000 576#define GC_INT_LPO_PU 0x1 577#define EXT_LPO_SEL 0x8 578#define INT_LPO_SEL 0x4 579#define ENABLE_FINE_CBUCK_CTRL (1 << 30) 580#define REGCTRL5_PWM_AUTO_CTRL_MASK 0x007e0000 581#define REGCTRL5_PWM_AUTO_CTRL_SHIFT 17 582#define REGCTRL6_PWM_AUTO_CTRL_MASK 0x3fff0000 583#define REGCTRL6_PWM_AUTO_CTRL_SHIFT 16 584 585#ifdef SR_DEBUG 586#define SUBCORE_POWER_ON 0x0001 587#define PHY_POWER_ON 0x0010 588#define VDDM_POWER_ON 0x0100 589#define MEMLPLDO_POWER_ON 0x1000 590#define SUBCORE_POWER_ON_CHK 0x00040000 591#define PHY_POWER_ON_CHK 0x00080000 592#define VDDM_POWER_ON_CHK 0x00100000 593#define MEMLPLDO_POWER_ON_CHK 0x00200000 594#endif /* SR_DEBUG */ 595 596#ifdef NFLASH_SUPPORT 597/* NAND flash support */ 598#define CC_NAND_REVISION 0xC00 599#define CC_NAND_CMD_START 0xC04 600#define CC_NAND_CMD_ADDR 0xC0C 601#define CC_NAND_SPARE_RD_0 0xC20 602#define CC_NAND_SPARE_RD_4 0xC24 603#define CC_NAND_SPARE_RD_8 0xC28 604#define CC_NAND_SPARE_RD_C 0xC2C 605#define CC_NAND_CONFIG 0xC48 606#define CC_NAND_DEVID 0xC60 607#define CC_NAND_DEVID_EXT 0xC64 608#define CC_NAND_INTFC_STATUS 0xC6C 609#endif /* NFLASH_SUPPORT */ 610 611/* chipid */ 612#define CID_ID_MASK 0x0000ffff /* Chip Id mask */ 613#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */ 614#define CID_REV_SHIFT 16 /* Chip Revision shift */ 615#define CID_PKG_MASK 0x00f00000 /* Package Option mask */ 616#define CID_PKG_SHIFT 20 /* Package Option shift */ 617#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */ 618#define CID_CC_SHIFT 24 619#define CID_TYPE_MASK 0xf0000000 /* Chip Type */ 620#define CID_TYPE_SHIFT 28 621 622/* capabilities */ 623#define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */ 624#define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */ 625#define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */ 626#define CC_CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */ 627#define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */ 628#define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */ 629#define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */ 630#define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */ 631#define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */ 632#define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */ 633#define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ 634#define CC_CAP_PWR_CTL 0x00040000 /* Power control */ 635#define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */ 636#define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */ 637#define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */ 638#define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ 639#define CC_CAP_ROM 0x00800000 /* Internal boot rom active */ 640#define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */ 641#define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */ 642#define CC_CAP_ECI 0x20000000 /* ECI Present, rev >= 21 */ 643#define CC_CAP_SROM 0x40000000 /* Srom Present, rev >= 32 */ 644#define CC_CAP_NFLASH 0x80000000 /* Nand flash present, rev >= 35 */ 645 646#define CC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */ 647#define CC_CAP2_GSIO 0x00000002 /* GSIO (spi/i2c) present, rev >= 37 */ 648 649/* capabilities extension */ 650#define CC_CAP_EXT_SECI_PRESENT 0x00000001 /* SECI present */ 651#define CC_CAP_EXT_GSIO_PRESENT 0x00000002 /* GSIO present */ 652#define CC_CAP_EXT_GCI_PRESENT 0x00000004 /* GCI present */ 653#define CC_CAP_EXT_AOB_PRESENT 0x00000040 /* AOB present */ 654 655/* WL Channel Info to BT via GCI - bits 40 - 47 */ 656#define GCI_WL_CHN_INFO_MASK (0xFF00) 657/* PLL type */ 658#define PLL_NONE 0x00000000 659#define PLL_TYPE1 0x00010000 /* 48MHz base, 3 dividers */ 660#define PLL_TYPE2 0x00020000 /* 48MHz, 4 dividers */ 661#define PLL_TYPE3 0x00030000 /* 25MHz, 2 dividers */ 662#define PLL_TYPE4 0x00008000 /* 48MHz, 4 dividers */ 663#define PLL_TYPE5 0x00018000 /* 25MHz, 4 dividers */ 664#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */ 665#define PLL_TYPE7 0x00038000 /* 25MHz, 4 dividers */ 666 667/* ILP clock */ 668#define ILP_CLOCK 32000 669 670/* ALP clock on pre-PMU chips */ 671#define ALP_CLOCK 20000000 672 673#ifdef CFG_SIM 674#define NS_ALP_CLOCK 84922 675#define NS_SLOW_ALP_CLOCK 84922 676#define NS_CPU_CLOCK 534500 677#define NS_SLOW_CPU_CLOCK 534500 678#define NS_SI_CLOCK 271750 679#define NS_SLOW_SI_CLOCK 271750 680#define NS_FAST_MEM_CLOCK 271750 681#define NS_MEM_CLOCK 271750 682#define NS_SLOW_MEM_CLOCK 271750 683#else 684#define NS_ALP_CLOCK 125000000 685#define NS_SLOW_ALP_CLOCK 100000000 686#define NS_CPU_CLOCK 1000000000 687#define NS_SLOW_CPU_CLOCK 800000000 688#define NS_SI_CLOCK 250000000 689#define NS_SLOW_SI_CLOCK 200000000 690#define NS_FAST_MEM_CLOCK 800000000 691#define NS_MEM_CLOCK 533000000 692#define NS_SLOW_MEM_CLOCK 400000000 693#endif /* CFG_SIM */ 694 695/* HT clock */ 696#define HT_CLOCK 80000000 697 698/* corecontrol */ 699#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */ 700#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ 701#define CC_ASYNCGPIO 0x00000004 /* 1=generate GPIO interrupt without backplane clock */ 702#define CC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */ 703 704/* 4321 chipcontrol */ 705#define CHIPCTRL_4321A0_DEFAULT 0x3a4 706#define CHIPCTRL_4321A1_DEFAULT 0x0a4 707#define CHIPCTRL_4321_PLL_DOWN 0x800000 /* serdes PLL down override */ 708 709/* Fields in the otpstatus register in rev >= 21 */ 710#define OTPS_OL_MASK 0x000000ff 711#define OTPS_OL_MFG 0x00000001 /* manuf row is locked */ 712#define OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */ 713#define OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */ 714#define OTPS_OL_GU 0x00000008 /* general use region is locked */ 715#define OTPS_GUP_MASK 0x00000f00 716#define OTPS_GUP_SHIFT 8 717#define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */ 718#define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */ 719#define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */ 720#define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */ 721#define OTPS_READY 0x00001000 722#define OTPS_RV(x) (1 << (16 + (x))) /* redundancy entry valid */ 723#define OTPS_RV_MASK 0x0fff0000 724#define OTPS_PROGOK 0x40000000 725 726/* Fields in the otpcontrol register in rev >= 21 */ 727#define OTPC_PROGSEL 0x00000001 728#define OTPC_PCOUNT_MASK 0x0000000e 729#define OTPC_PCOUNT_SHIFT 1 730#define OTPC_VSEL_MASK 0x000000f0 731#define OTPC_VSEL_SHIFT 4 732#define OTPC_TMM_MASK 0x00000700 733#define OTPC_TMM_SHIFT 8 734#define OTPC_ODM 0x00000800 735#define OTPC_PROGEN 0x80000000 736 737/* Fields in the 40nm otpcontrol register in rev >= 40 */ 738#define OTPC_40NM_PROGSEL_SHIFT 0 739#define OTPC_40NM_PCOUNT_SHIFT 1 740#define OTPC_40NM_PCOUNT_WR 0xA 741#define OTPC_40NM_PCOUNT_V1X 0xB 742#define OTPC_40NM_REGCSEL_SHIFT 5 743#define OTPC_40NM_REGCSEL_DEF 0x4 744#define OTPC_40NM_PROGIN_SHIFT 8 745#define OTPC_40NM_R2X_SHIFT 10 746#define OTPC_40NM_ODM_SHIFT 11 747#define OTPC_40NM_DF_SHIFT 15 748#define OTPC_40NM_VSEL_SHIFT 16 749#define OTPC_40NM_VSEL_WR 0xA 750#define OTPC_40NM_VSEL_V1X 0xA 751#define OTPC_40NM_VSEL_R1X 0x5 752#define OTPC_40NM_COFAIL_SHIFT 30 753 754#define OTPC1_CPCSEL_SHIFT 0 755#define OTPC1_CPCSEL_DEF 6 756#define OTPC1_TM_SHIFT 8 757#define OTPC1_TM_WR 0x84 758#define OTPC1_TM_V1X 0x84 759#define OTPC1_TM_R1X 0x4 760 761/* Fields in otpprog in rev >= 21 and HND OTP */ 762#define OTPP_COL_MASK 0x000000ff 763#define OTPP_COL_SHIFT 0 764#define OTPP_ROW_MASK 0x0000ff00 765#define OTPP_ROW_SHIFT 8 766#define OTPP_OC_MASK 0x0f000000 767#define OTPP_OC_SHIFT 24 768#define OTPP_READERR 0x10000000 769#define OTPP_VALUE_MASK 0x20000000 770#define OTPP_VALUE_SHIFT 29 771#define OTPP_START_BUSY 0x80000000 772#define OTPP_READ 0x40000000 /* HND OTP */ 773 774/* Fields in otplayout register */ 775#define OTPL_HWRGN_OFF_MASK 0x00000FFF 776#define OTPL_HWRGN_OFF_SHIFT 0 777#define OTPL_WRAP_REVID_MASK 0x00F80000 778#define OTPL_WRAP_REVID_SHIFT 19 779#define OTPL_WRAP_TYPE_MASK 0x00070000 780#define OTPL_WRAP_TYPE_SHIFT 16 781#define OTPL_WRAP_TYPE_65NM 0 782#define OTPL_WRAP_TYPE_40NM 1 783#define OTPL_ROW_SIZE_MASK 0x0000F000 784#define OTPL_ROW_SIZE_SHIFT 12 785 786/* otplayout reg corerev >= 36 */ 787#define OTP_CISFORMAT_NEW 0x80000000 788 789/* Opcodes for OTPP_OC field */ 790#define OTPPOC_READ 0 791#define OTPPOC_BIT_PROG 1 792#define OTPPOC_VERIFY 3 793#define OTPPOC_INIT 4 794#define OTPPOC_SET 5 795#define OTPPOC_RESET 6 796#define OTPPOC_OCST 7 797#define OTPPOC_ROW_LOCK 8 798#define OTPPOC_PRESCN_TEST 9 799 800/* Opcodes for OTPP_OC field (40NM) */ 801#define OTPPOC_READ_40NM 0 802#define OTPPOC_PROG_ENABLE_40NM 1 803#define OTPPOC_PROG_DISABLE_40NM 2 804#define OTPPOC_VERIFY_40NM 3 805#define OTPPOC_WORD_VERIFY_1_40NM 4 806#define OTPPOC_ROW_LOCK_40NM 5 807#define OTPPOC_STBY_40NM 6 808#define OTPPOC_WAKEUP_40NM 7 809#define OTPPOC_WORD_VERIFY_0_40NM 8 810#define OTPPOC_PRESCN_TEST_40NM 9 811#define OTPPOC_BIT_PROG_40NM 10 812#define OTPPOC_WORDPROG_40NM 11 813#define OTPPOC_BURNIN_40NM 12 814#define OTPPOC_AUTORELOAD_40NM 13 815#define OTPPOC_OVST_READ_40NM 14 816#define OTPPOC_OVST_PROG_40NM 15 817 818/* Fields in otplayoutextension */ 819#define OTPLAYOUTEXT_FUSE_MASK 0x3FF 820 821 822/* Jtagm characteristics that appeared at a given corerev */ 823#define JTAGM_CREV_OLD 10 /* Old command set, 16bit max IR */ 824#define JTAGM_CREV_IRP 22 /* Able to do pause-ir */ 825#define JTAGM_CREV_RTI 28 /* Able to do return-to-idle */ 826 827/* jtagcmd */ 828#define JCMD_START 0x80000000 829#define JCMD_BUSY 0x80000000 830#define JCMD_STATE_MASK 0x60000000 831#define JCMD_STATE_TLR 0x00000000 /* Test-logic-reset */ 832#define JCMD_STATE_PIR 0x20000000 /* Pause IR */ 833#define JCMD_STATE_PDR 0x40000000 /* Pause DR */ 834#define JCMD_STATE_RTI 0x60000000 /* Run-test-idle */ 835#define JCMD0_ACC_MASK 0x0000f000 836#define JCMD0_ACC_IRDR 0x00000000 837#define JCMD0_ACC_DR 0x00001000 838#define JCMD0_ACC_IR 0x00002000 839#define JCMD0_ACC_RESET 0x00003000 840#define JCMD0_ACC_IRPDR 0x00004000 841#define JCMD0_ACC_PDR 0x00005000 842#define JCMD0_IRW_MASK 0x00000f00 843#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */ 844#define JCMD_ACC_IRDR 0x00000000 845#define JCMD_ACC_DR 0x00010000 846#define JCMD_ACC_IR 0x00020000 847#define JCMD_ACC_RESET 0x00030000 848#define JCMD_ACC_IRPDR 0x00040000 849#define JCMD_ACC_PDR 0x00050000 850#define JCMD_ACC_PIR 0x00060000 851#define JCMD_ACC_IRDR_I 0x00070000 /* rev 28: return to run-test-idle */ 852#define JCMD_ACC_DR_I 0x00080000 /* rev 28: return to run-test-idle */ 853#define JCMD_IRW_MASK 0x00001f00 854#define JCMD_IRW_SHIFT 8 855#define JCMD_DRW_MASK 0x0000003f 856 857/* jtagctrl */ 858#define JCTRL_FORCE_CLK 4 /* Force clock */ 859#define JCTRL_EXT_EN 2 /* Enable external targets */ 860#define JCTRL_EN 1 /* Enable Jtag master */ 861 862#define JCTRL_TAPSEL_BIT 0x00000008 /* JtagMasterCtrl tap_sel bit */ 863 864/* Fields in clkdiv */ 865#define CLKD_SFLASH 0x0f000000 866#define CLKD_SFLASH_SHIFT 24 867#define CLKD_OTP 0x000f0000 868#define CLKD_OTP_SHIFT 16 869#define CLKD_JTAG 0x00000f00 870#define CLKD_JTAG_SHIFT 8 871#define CLKD_UART 0x000000ff 872 873#define CLKD2_SROM 0x00000003 874 875/* intstatus/intmask */ 876#define CI_GPIO 0x00000001 /* gpio intr */ 877#define CI_EI 0x00000002 /* extif intr (corerev >= 3) */ 878#define CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */ 879#define CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */ 880#define CI_ECI 0x00000010 /* eci intr (corerev >= 21) */ 881#define CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */ 882#define CI_UART 0x00000040 /* uart intr (corerev >= 21) */ 883#define CI_WDRESET 0x80000000 /* watchdog reset occurred */ 884 885/* slow_clk_ctl */ 886#define SCC_SS_MASK 0x00000007 /* slow clock source mask */ 887#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */ 888#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */ 889#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */ 890#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ 891#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 892 * 0: LPO is enabled 893 */ 894#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 895 * 0: power logic control 896 */ 897#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors 898 * PLL clock disable requests from core 899 */ 900#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't 901 * disable crystal when appropriate 902 */ 903#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ 904#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ 905#define SCC_CD_SHIFT 16 906 907/* system_clk_ctl */ 908#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */ 909#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */ 910#define SYCC_FP 0x00000004 /* ForcePLLOn */ 911#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */ 912#define SYCC_HR 0x00000010 /* Force HT */ 913#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */ 914#define SYCC_CD_SHIFT 16 915 916/* Indirect backplane access */ 917#define BPIA_BYTEEN 0x0000000f 918#define BPIA_SZ1 0x00000001 919#define BPIA_SZ2 0x00000003 920#define BPIA_SZ4 0x00000007 921#define BPIA_SZ8 0x0000000f 922#define BPIA_WRITE 0x00000100 923#define BPIA_START 0x00000200 924#define BPIA_BUSY 0x00000200 925#define BPIA_ERROR 0x00000400 926 927/* pcmcia/prog/flash_config */ 928#define CF_EN 0x00000001 /* enable */ 929#define CF_EM_MASK 0x0000000e /* mode */ 930#define CF_EM_SHIFT 1 931#define CF_EM_FLASH 0 /* flash/asynchronous mode */ 932#define CF_EM_SYNC 2 /* synchronous mode */ 933#define CF_EM_PCMCIA 4 /* pcmcia mode */ 934#define CF_DS 0x00000010 /* destsize: 0=8bit, 1=16bit */ 935#define CF_BS 0x00000020 /* byteswap */ 936#define CF_CD_MASK 0x000000c0 /* clock divider */ 937#define CF_CD_SHIFT 6 938#define CF_CD_DIV2 0x00000000 /* backplane/2 */ 939#define CF_CD_DIV3 0x00000040 /* backplane/3 */ 940#define CF_CD_DIV4 0x00000080 /* backplane/4 */ 941#define CF_CE 0x00000100 /* clock enable */ 942#define CF_SB 0x00000200 /* size/bytestrobe (synch only) */ 943 944/* pcmcia_memwait */ 945#define PM_W0_MASK 0x0000003f /* waitcount0 */ 946#define PM_W1_MASK 0x00001f00 /* waitcount1 */ 947#define PM_W1_SHIFT 8 948#define PM_W2_MASK 0x001f0000 /* waitcount2 */ 949#define PM_W2_SHIFT 16 950#define PM_W3_MASK 0x1f000000 /* waitcount3 */ 951#define PM_W3_SHIFT 24 952 953/* pcmcia_attrwait */ 954#define PA_W0_MASK 0x0000003f /* waitcount0 */ 955#define PA_W1_MASK 0x00001f00 /* waitcount1 */ 956#define PA_W1_SHIFT 8 957#define PA_W2_MASK 0x001f0000 /* waitcount2 */ 958#define PA_W2_SHIFT 16 959#define PA_W3_MASK 0x1f000000 /* waitcount3 */ 960#define PA_W3_SHIFT 24 961 962/* pcmcia_iowait */ 963#define PI_W0_MASK 0x0000003f /* waitcount0 */ 964#define PI_W1_MASK 0x00001f00 /* waitcount1 */ 965#define PI_W1_SHIFT 8 966#define PI_W2_MASK 0x001f0000 /* waitcount2 */ 967#define PI_W2_SHIFT 16 968#define PI_W3_MASK 0x1f000000 /* waitcount3 */ 969#define PI_W3_SHIFT 24 970 971/* prog_waitcount */ 972#define PW_W0_MASK 0x0000001f /* waitcount0 */ 973#define PW_W1_MASK 0x00001f00 /* waitcount1 */ 974#define PW_W1_SHIFT 8 975#define PW_W2_MASK 0x001f0000 /* waitcount2 */ 976#define PW_W2_SHIFT 16 977#define PW_W3_MASK 0x1f000000 /* waitcount3 */ 978#define PW_W3_SHIFT 24 979 980#define PW_W0 0x0000000c 981#define PW_W1 0x00000a00 982#define PW_W2 0x00020000 983#define PW_W3 0x01000000 984 985/* flash_waitcount */ 986#define FW_W0_MASK 0x0000003f /* waitcount0 */ 987#define FW_W1_MASK 0x00001f00 /* waitcount1 */ 988#define FW_W1_SHIFT 8 989#define FW_W2_MASK 0x001f0000 /* waitcount2 */ 990#define FW_W2_SHIFT 16 991#define FW_W3_MASK 0x1f000000 /* waitcount3 */ 992#define FW_W3_SHIFT 24 993 994/* When Srom support present, fields in sromcontrol */ 995#define SRC_START 0x80000000 996#define SRC_BUSY 0x80000000 997#define SRC_OPCODE 0x60000000 998#define SRC_OP_READ 0x00000000 999#define SRC_OP_WRITE 0x20000000 1000#define SRC_OP_WRDIS 0x40000000 1001#define SRC_OP_WREN 0x60000000 1002#define SRC_OTPSEL 0x00000010 1003#define SRC_OTPPRESENT 0x00000020 1004#define SRC_LOCK 0x00000008 1005#define SRC_SIZE_MASK 0x00000006 1006#define SRC_SIZE_1K 0x00000000 1007#define SRC_SIZE_4K 0x00000002 1008#define SRC_SIZE_16K 0x00000004 1009#define SRC_SIZE_SHIFT 1 1010#define SRC_PRESENT 0x00000001 1011 1012/* Fields in pmucontrol */ 1013#define PCTL_ILP_DIV_MASK 0xffff0000 1014#define PCTL_ILP_DIV_SHIFT 16 1015#define PCTL_LQ_REQ_EN 0x00008000 1016#define PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */ 1017#define PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */ 1018#define PCTL_HT_REQ_EN 0x00000100 1019#define PCTL_ALP_REQ_EN 0x00000080 1020#define PCTL_XTALFREQ_MASK 0x0000007c 1021#define PCTL_XTALFREQ_SHIFT 2 1022#define PCTL_ILP_DIV_EN 0x00000002 1023#define PCTL_LPO_SEL 0x00000001 1024 1025/* Fields in pmucontrol_ext */ 1026#define PCTLEX_FTE_MASK (1 << 0) 1027#define PCTLEX_FTE_SHIFT 0 1028 1029/* Retention Control */ 1030#define PMU_RCTL_CLK_DIV_SHIFT 0 1031#define PMU_RCTL_CHAIN_LEN_SHIFT 12 1032#define PMU_RCTL_MACPHY_DISABLE_SHIFT 26 1033#define PMU_RCTL_MACPHY_DISABLE_MASK (1 << 26) 1034#define PMU_RCTL_LOGIC_DISABLE_SHIFT 27 1035#define PMU_RCTL_LOGIC_DISABLE_MASK (1 << 27) 1036#define PMU_RCTL_MEMSLP_LOG_SHIFT 28 1037#define PMU_RCTL_MEMSLP_LOG_MASK (1 << 28) 1038#define PMU_RCTL_MEMRETSLP_LOG_SHIFT 29 1039#define PMU_RCTL_MEMRETSLP_LOG_MASK (1 << 29) 1040 1041/* Retention Group Control */ 1042#define PMU_RCTLGRP_CHAIN_LEN_SHIFT 0 1043#define PMU_RCTLGRP_RMODE_ENABLE_SHIFT 14 1044#define PMU_RCTLGRP_RMODE_ENABLE_MASK (1 << 14) 1045#define PMU_RCTLGRP_DFT_ENABLE_SHIFT 15 1046#define PMU_RCTLGRP_DFT_ENABLE_MASK (1 << 15) 1047#define PMU_RCTLGRP_NSRST_DISABLE_SHIFT 16 1048#define PMU_RCTLGRP_NSRST_DISABLE_MASK (1 << 16) 1049/* Retention Group Control special for 4334 */ 1050#define PMU4334_RCTLGRP_CHAIN_LEN_GRP0 338 1051#define PMU4334_RCTLGRP_CHAIN_LEN_GRP1 315 1052/* Retention Group Control special for 43341 */ 1053#define PMU43341_RCTLGRP_CHAIN_LEN_GRP0 366 1054#define PMU43341_RCTLGRP_CHAIN_LEN_GRP1 330 1055 1056/* Fields in clkstretch */ 1057#define CSTRETCH_HT 0xffff0000 1058#define CSTRETCH_ALP 0x0000ffff 1059 1060/* gpiotimerval */ 1061#define GPIO_ONTIME_SHIFT 16 1062 1063/* clockcontrol_n */ 1064#define CN_N1_MASK 0x3f /* n1 control */ 1065#define CN_N2_MASK 0x3f00 /* n2 control */ 1066#define CN_N2_SHIFT 8 1067#define CN_PLLC_MASK 0xf0000 /* pll control */ 1068#define CN_PLLC_SHIFT 16 1069 1070/* clockcontrol_sb/pci/uart */ 1071#define CC_M1_MASK 0x3f /* m1 control */ 1072#define CC_M2_MASK 0x3f00 /* m2 control */ 1073#define CC_M2_SHIFT 8 1074#define CC_M3_MASK 0x3f0000 /* m3 control */ 1075#define CC_M3_SHIFT 16 1076#define CC_MC_MASK 0x1f000000 /* mux control */ 1077#define CC_MC_SHIFT 24 1078 1079/* N3M Clock control magic field values */ 1080#define CC_F6_2 0x02 /* A factor of 2 in */ 1081#define CC_F6_3 0x03 /* 6-bit fields like */ 1082#define CC_F6_4 0x05 /* N1, M1 or M3 */ 1083#define CC_F6_5 0x09 1084#define CC_F6_6 0x11 1085#define CC_F6_7 0x21 1086 1087#define CC_F5_BIAS 5 /* 5-bit fields get this added */ 1088 1089#define CC_MC_BYPASS 0x08 1090#define CC_MC_M1 0x04 1091#define CC_MC_M1M2 0x02 1092#define CC_MC_M1M2M3 0x01 1093#define CC_MC_M1M3 0x11 1094 1095/* Type 2 Clock control magic field values */ 1096#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */ 1097#define CC_T2M2_BIAS 3 /* m2 bias */ 1098 1099#define CC_T2MC_M1BYP 1 1100#define CC_T2MC_M2BYP 2 1101#define CC_T2MC_M3BYP 4 1102 1103/* Type 6 Clock control magic field values */ 1104#define CC_T6_MMASK 1 /* bits of interest in m */ 1105#define CC_T6_M0 120000000 /* sb clock for m = 0 */ 1106#define CC_T6_M1 100000000 /* sb clock for m = 1 */ 1107#define SB2MIPS_T6(sb) (2 * (sb)) 1108 1109/* Common clock base */ 1110#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */ 1111#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLLs */ 1112 1113/* Clock control values for 200MHz in 5350 */ 1114#define CLKC_5350_N 0x0311 1115#define CLKC_5350_M 0x04020009 1116 1117/* Flash types in the chipcommon capabilities register */ 1118#define FLASH_NONE 0x000 /* No flash */ 1119#define SFLASH_ST 0x100 /* ST serial flash */ 1120#define SFLASH_AT 0x200 /* Atmel serial flash */ 1121#define NFLASH 0x300 1122#define PFLASH 0x700 /* Parallel flash */ 1123#define QSPIFLASH_ST 0x800 1124#define QSPIFLASH_AT 0x900 1125 1126/* Bits in the ExtBus config registers */ 1127#define CC_CFG_EN 0x0001 /* Enable */ 1128#define CC_CFG_EM_MASK 0x000e /* Extif Mode */ 1129#define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */ 1130#define CC_CFG_EM_SYNC 0x0002 /* Synchronous */ 1131#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */ 1132#define CC_CFG_EM_IDE 0x0006 /* IDE */ 1133#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ 1134#define CC_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */ 1135#define CC_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */ 1136#define CC_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */ 1137#define CC_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */ 1138 1139/* ExtBus address space */ 1140#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */ 1141#define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */ 1142#define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */ 1143#define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */ 1144#define CC_EB_IDE 0x1a800000 /* IDE memory base */ 1145#define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */ 1146#define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */ 1147#define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */ 1148#define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */ 1149 1150 1151/* Start/busy bit in flashcontrol */ 1152#define SFLASH_OPCODE 0x000000ff 1153#define SFLASH_ACTION 0x00000700 1154#define SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ 1155#define SFLASH_START 0x80000000 1156#define SFLASH_BUSY SFLASH_START 1157 1158/* flashcontrol action codes */ 1159#define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */ 1160#define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */ 1161#define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 addr bytes */ 1162#define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addr & 1 data bytes */ 1163#define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addr & 4 data bytes */ 1164#define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addr, 4 don't care & 4 data bytes */ 1165#define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addr, 1 don't care & 4 data bytes */ 1166 1167/* flashcontrol action+opcodes for ST flashes */ 1168#define SFLASH_ST_WREN 0x0006 /* Write Enable */ 1169#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */ 1170#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */ 1171#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */ 1172#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */ 1173#define SFLASH_ST_PP 0x0302 /* Page Program */ 1174#define SFLASH_ST_SE 0x02d8 /* Sector Erase */ 1175#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */ 1176#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */ 1177#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */ 1178#define SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */ 1179#define SFLASH_ST_SSE 0x0220 /* Sub-sector Erase */ 1180 1181#define SFLASH_MXIC_RDID 0x0390 /* Read Manufacture ID */ 1182#define SFLASH_MXIC_MFID 0xc2 /* MXIC Manufacture ID */ 1183 1184/* Status register bits for ST flashes */ 1185#define SFLASH_ST_WIP 0x01 /* Write In Progress */ 1186#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */ 1187#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */ 1188#define SFLASH_ST_BP_SHIFT 2 1189#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */ 1190 1191/* flashcontrol action+opcodes for Atmel flashes */ 1192#define SFLASH_AT_READ 0x07e8 1193#define SFLASH_AT_PAGE_READ 0x07d2 1194#define SFLASH_AT_BUF1_READ 1195#define SFLASH_AT_BUF2_READ 1196#define SFLASH_AT_STATUS 0x01d7 1197#define SFLASH_AT_BUF1_WRITE 0x0384 1198#define SFLASH_AT_BUF2_WRITE 0x0387 1199#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 1200#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 1201#define SFLASH_AT_BUF1_PROGRAM 0x0288 1202#define SFLASH_AT_BUF2_PROGRAM 0x0289 1203#define SFLASH_AT_PAGE_ERASE 0x0281 1204#define SFLASH_AT_BLOCK_ERASE 0x0250 1205#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 1206#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 1207#define SFLASH_AT_BUF1_LOAD 0x0253 1208#define SFLASH_AT_BUF2_LOAD 0x0255 1209#define SFLASH_AT_BUF1_COMPARE 0x0260 1210#define SFLASH_AT_BUF2_COMPARE 0x0261 1211#define SFLASH_AT_BUF1_REPROGRAM 0x0258 1212#define SFLASH_AT_BUF2_REPROGRAM 0x0259 1213 1214/* Status register bits for Atmel flashes */ 1215#define SFLASH_AT_READY 0x80 1216#define SFLASH_AT_MISMATCH 0x40 1217#define SFLASH_AT_ID_MASK 0x38 1218#define SFLASH_AT_ID_SHIFT 3 1219 1220/* SPI register bits, corerev >= 37 */ 1221#define GSIO_START 0x80000000 1222#define GSIO_BUSY GSIO_START 1223 1224/* 1225 * These are the UART port assignments, expressed as offsets from the base 1226 * register. These assignments should hold for any serial port based on 1227 * a 8250, 16450, or 16550(A). 1228 */ 1229 1230#define UART_RX 0 /* In: Receive buffer (DLAB=0) */ 1231#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ 1232#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ 1233#define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */ 1234#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ 1235#define UART_IIR 2 /* In: Interrupt Identity Register */ 1236#define UART_FCR 2 /* Out: FIFO Control Register */ 1237#define UART_LCR 3 /* Out: Line Control Register */ 1238#define UART_MCR 4 /* Out: Modem Control Register */ 1239#define UART_LSR 5 /* In: Line Status Register */ 1240#define UART_MSR 6 /* In: Modem Status Register */ 1241#define UART_SCR 7 /* I/O: Scratch Register */ 1242#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 1243#define UART_LCR_WLEN8 0x03 /* Word length: 8 bits */ 1244#define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */ 1245#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 1246#define UART_LSR_RX_FIFO 0x80 /* Receive FIFO error */ 1247#define UART_LSR_TDHR 0x40 /* Data-hold-register empty */ 1248#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 1249#define UART_LSR_BREAK 0x10 /* Break interrupt */ 1250#define UART_LSR_FRAMING 0x08 /* Framing error */ 1251#define UART_LSR_PARITY 0x04 /* Parity error */ 1252#define UART_LSR_OVERRUN 0x02 /* Overrun error */ 1253#define UART_LSR_RXRDY 0x01 /* Receiver ready */ 1254#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */ 1255#define UART_FCR_TX_FIFO_RESET 0x04 /* FIFO control register bit controlling Tx FIFO Reset */ 1256#define UART_FCR_RX_FIFO_RESET 0x02 /* FIFO control register bit controlling Rx FIFO Reset */ 1257 1258/* Interrupt Identity Register (IIR) bits */ 1259#define UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */ 1260#define UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */ 1261#define UART_IIR_MDM_CHG 0x0 /* Modem status changed */ 1262#define UART_IIR_NOINT 0x1 /* No interrupt pending */ 1263#define UART_IIR_THRE 0x2 /* THR empty */ 1264#define UART_IIR_RCVD_DATA 0x4 /* Received data available */ 1265#define UART_IIR_RCVR_STATUS 0x6 /* Receiver status */ 1266#define UART_IIR_CHAR_TIME 0xc /* Character time */ 1267 1268/* Interrupt Enable Register (IER) bits */ 1269#define UART_IER_PTIME 128 /* Programmable THRE Interrupt Mode Enable */ 1270#define UART_IER_EDSSI 8 /* enable modem status interrupt */ 1271#define UART_IER_ELSI 4 /* enable receiver line status interrupt */ 1272#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */ 1273#define UART_IER_ERBFI 1 /* enable data available interrupt */ 1274 1275/* pmustatus */ 1276#define PST_SLOW_WR_PENDING 0x0400 1277#define PST_EXTLPOAVAIL 0x0100 1278#define PST_WDRESET 0x0080 1279#define PST_INTPEND 0x0040 1280#define PST_SBCLKST 0x0030 1281#define PST_SBCLKST_ILP 0x0010 1282#define PST_SBCLKST_ALP 0x0020 1283#define PST_SBCLKST_HT 0x0030 1284#define PST_ALPAVAIL 0x0008 1285#define PST_HTAVAIL 0x0004 1286#define PST_RESINIT 0x0003 1287 1288/* pmucapabilities */ 1289#define PCAP_REV_MASK 0x000000ff 1290#define PCAP_RC_MASK 0x00001f00 1291#define PCAP_RC_SHIFT 8 1292#define PCAP_TC_MASK 0x0001e000 1293#define PCAP_TC_SHIFT 13 1294#define PCAP_PC_MASK 0x001e0000 1295#define PCAP_PC_SHIFT 17 1296#define PCAP_VC_MASK 0x01e00000 1297#define PCAP_VC_SHIFT 21 1298#define PCAP_CC_MASK 0x1e000000 1299#define PCAP_CC_SHIFT 25 1300#define PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */ 1301#define PCAP5_PC_SHIFT 17 1302#define PCAP5_VC_MASK 0x07c00000 1303#define PCAP5_VC_SHIFT 22 1304#define PCAP5_CC_MASK 0xf8000000 1305#define PCAP5_CC_SHIFT 27 1306 1307/* PMU Resource Request Timer registers */ 1308/* This is based on PmuRev0 */ 1309#define PRRT_TIME_MASK 0x03ff 1310#define PRRT_INTEN 0x0400 1311#define PRRT_REQ_ACTIVE 0x0800 1312#define PRRT_ALP_REQ 0x1000 1313#define PRRT_HT_REQ 0x2000 1314#define PRRT_HQ_REQ 0x4000 1315 1316/* PMU resource bit position */ 1317#define PMURES_BIT(bit) (1 << (bit)) 1318 1319/* PMU resource number limit */ 1320#define PMURES_MAX_RESNUM 30 1321 1322/* PMU chip control0 register */ 1323#define PMU_CHIPCTL0 0 1324#define PMU43143_CC0_SDIO_DRSTR_OVR (1 << 31) /* sdio drive strength override enable */ 1325 1326/* clock req types */ 1327#define PMU_CC1_CLKREQ_TYPE_SHIFT 19 1328#define PMU_CC1_CLKREQ_TYPE_MASK (1 << PMU_CC1_CLKREQ_TYPE_SHIFT) 1329 1330#define CLKREQ_TYPE_CONFIG_OPENDRAIN 0 1331#define CLKREQ_TYPE_CONFIG_PUSHPULL 1 1332 1333/* PMU chip control1 register */ 1334#define PMU_CHIPCTL1 1 1335#define PMU_CC1_RXC_DLL_BYPASS 0x00010000 1336#define PMU_CC1_ENABLE_BBPLL_PWR_DOWN 0x00000010 1337 1338#define PMU_CC1_IF_TYPE_MASK 0x00000030 1339#define PMU_CC1_IF_TYPE_RMII 0x00000000 1340#define PMU_CC1_IF_TYPE_MII 0x00000010 1341#define PMU_CC1_IF_TYPE_RGMII 0x00000020 1342 1343#define PMU_CC1_SW_TYPE_MASK 0x000000c0 1344#define PMU_CC1_SW_TYPE_EPHY 0x00000000 1345#define PMU_CC1_SW_TYPE_EPHYMII 0x00000040 1346#define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 1347#define PMU_CC1_SW_TYPE_RGMII 0x000000c0 1348 1349/* PMU chip control2 register */ 1350#define PMU_CHIPCTL2 2 1351#define PMU_CC2_FORCE_SUBCORE_PWR_SWITCH_ON (1 << 18) 1352#define PMU_CC2_FORCE_PHY_PWR_SWITCH_ON (1 << 19) 1353#define PMU_CC2_FORCE_VDDM_PWR_SWITCH_ON (1 << 20) 1354#define PMU_CC2_FORCE_MEMLPLDO_PWR_SWITCH_ON (1 << 21) 1355 1356/* PMU chip control3 register */ 1357#define PMU_CHIPCTL3 3 1358 1359#define PMU_CC3_ENABLE_SDIO_WAKEUP_SHIFT 19 1360#define PMU_CC3_ENABLE_RF_SHIFT 22 1361#define PMU_CC3_RF_DISABLE_IVALUE_SHIFT 23 1362 1363/* PMU chip control5 register */ 1364#define PMU_CHIPCTL5 5 1365 1366/* PMU chip control6 register */ 1367#define PMU_CHIPCTL6 6 1368#define PMU_CC6_ENABLE_CLKREQ_WAKEUP (1 << 4) 1369#define PMU_CC6_ENABLE_PMU_WAKEUP_ALP (1 << 6) 1370 1371/* PMU chip control7 register */ 1372#define PMU_CHIPCTL7 7 1373#define PMU_CC7_ENABLE_L2REFCLKPAD_PWRDWN (1 << 25) 1374#define PMU_CC7_ENABLE_MDIO_RESET_WAR (1 << 27) 1375 1376 1377/* PMU corerev and chip specific PLL controls. 1378 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number 1379 * to differentiate different PLLs controlled by the same PMU rev. 1380 */ 1381/* pllcontrol registers */ 1382/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ 1383#define PMU0_PLL0_PLLCTL0 0 1384#define PMU0_PLL0_PC0_PDIV_MASK 1 1385#define PMU0_PLL0_PC0_PDIV_FREQ 25000 1386#define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 1387#define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 1388#define PMU0_PLL0_PC0_DIV_ARM_BASE 8 1389 1390/* PC0_DIV_ARM for PLLOUT_ARM */ 1391#define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 1392#define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 1393#define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 1394#define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ 1395#define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 1396#define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 1397#define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 1398#define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 1399 1400/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ 1401#define PMU0_PLL0_PLLCTL1 1 1402#define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 1403#define PMU0_PLL0_PC1_WILD_INT_SHIFT 28 1404#define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 1405#define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 1406#define PMU0_PLL0_PC1_STOP_MOD 0x00000040 1407 1408/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ 1409#define PMU0_PLL0_PLLCTL2 2 1410#define PMU0_PLL0_PC2_WILD_INT_MASK 0xf 1411#define PMU0_PLL0_PC2_WILD_INT_SHIFT 4 1412 1413/* pllcontrol registers */ 1414/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 1415#define PMU1_PLL0_PLLCTL0 0 1416#define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 1417#define PMU1_PLL0_PC0_P1DIV_SHIFT 20 1418#define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 1419#define PMU1_PLL0_PC0_P2DIV_SHIFT 24 1420 1421/* m<x>div */ 1422#define PMU1_PLL0_PLLCTL1 1 1423#define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff 1424#define PMU1_PLL0_PC1_M1DIV_SHIFT 0 1425#define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 1426#define PMU1_PLL0_PC1_M2DIV_SHIFT 8 1427#define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 1428#define PMU1_PLL0_PC1_M3DIV_SHIFT 16 1429#define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 1430#define PMU1_PLL0_PC1_M4DIV_SHIFT 24 1431#define PMU1_PLL0_PC1_M4DIV_BY_9 9 1432#define PMU1_PLL0_PC1_M4DIV_BY_18 0x12 1433#define PMU1_PLL0_PC1_M4DIV_BY_36 0x24 1434#define PMU1_PLL0_PC1_M4DIV_BY_60 0x3C 1435 1436#define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 1437#define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 1438#define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 1439 1440/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 1441#define PMU1_PLL0_PLLCTL2 2 1442#define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff 1443#define PMU1_PLL0_PC2_M5DIV_SHIFT 0 1444#define PMU1_PLL0_PC2_M5DIV_BY_12 0xc 1445#define PMU1_PLL0_PC2_M5DIV_BY_18 0x12 1446#define PMU1_PLL0_PC2_M5DIV_BY_36 0x24 1447#define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 1448#define PMU1_PLL0_PC2_M6DIV_SHIFT 8 1449#define PMU1_PLL0_PC2_M6DIV_BY_18 0x12 1450#define PMU1_PLL0_PC2_M6DIV_BY_36 0x24 1451#define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 1452#define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 1453#define PMU1_PLL0_PC2_NDIV_MODE_MASH 1 1454#define PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */ 1455#define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 1456#define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 1457 1458/* ndiv_frac */ 1459#define PMU1_PLL0_PLLCTL3 3 1460#define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff 1461#define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 1462 1463/* pll_ctrl */ 1464#define PMU1_PLL0_PLLCTL4 4 1465 1466/* pll_ctrl, vco_rng, clkdrive_ch<x> */ 1467#define PMU1_PLL0_PLLCTL5 5 1468#define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 1469#define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 1470 1471#define PMU1_PLL0_PLLCTL6 6 1472#define PMU1_PLL0_PLLCTL7 7 1473 1474/* PMU rev 2 control words */ 1475#define PMU2_PHY_PLL_PLLCTL 4 1476#define PMU2_SI_PLL_PLLCTL 10 1477 1478/* PMU rev 2 */ 1479/* pllcontrol registers */ 1480/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 1481#define PMU2_PLL_PLLCTL0 0 1482#define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 1483#define PMU2_PLL_PC0_P1DIV_SHIFT 20 1484#define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 1485#define PMU2_PLL_PC0_P2DIV_SHIFT 24 1486 1487/* m<x>div */ 1488#define PMU2_PLL_PLLCTL1 1 1489#define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff 1490#define PMU2_PLL_PC1_M1DIV_SHIFT 0 1491#define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 1492#define PMU2_PLL_PC1_M2DIV_SHIFT 8 1493#define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 1494#define PMU2_PLL_PC1_M3DIV_SHIFT 16 1495#define PMU2_PLL_PC1_M4DIV_MASK 0xff000000 1496#define PMU2_PLL_PC1_M4DIV_SHIFT 24 1497 1498/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 1499#define PMU2_PLL_PLLCTL2 2 1500#define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff 1501#define PMU2_PLL_PC2_M5DIV_SHIFT 0 1502#define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 1503#define PMU2_PLL_PC2_M6DIV_SHIFT 8 1504#define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 1505#define PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 1506#define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 1507#define PMU2_PLL_PC2_NDIV_INT_SHIFT 20 1508 1509/* ndiv_frac */ 1510#define PMU2_PLL_PLLCTL3 3 1511#define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff 1512#define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 1513 1514/* pll_ctrl */ 1515#define PMU2_PLL_PLLCTL4 4 1516 1517/* pll_ctrl, vco_rng, clkdrive_ch<x> */ 1518#define PMU2_PLL_PLLCTL5 5 1519#define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 1520#define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 1521#define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 1522#define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 1523#define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 1524#define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 1525#define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 1526#define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 1527#define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 1528#define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 1529#define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 1530#define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 1531 1532/* PMU rev 5 (& 6) */ 1533#define PMU5_PLL_P1P2_OFF 0 1534#define PMU5_PLL_P1_MASK 0x0f000000 1535#define PMU5_PLL_P1_SHIFT 24 1536#define PMU5_PLL_P2_MASK 0x00f00000 1537#define PMU5_PLL_P2_SHIFT 20 1538#define PMU5_PLL_M14_OFF 1 1539#define PMU5_PLL_MDIV_MASK 0x000000ff 1540#define PMU5_PLL_MDIV_WIDTH 8 1541#define PMU5_PLL_NM5_OFF 2 1542#define PMU5_PLL_NDIV_MASK 0xfff00000 1543#define PMU5_PLL_NDIV_SHIFT 20 1544#define PMU5_PLL_NDIV_MODE_MASK 0x000e0000 1545#define PMU5_PLL_NDIV_MODE_SHIFT 17 1546#define PMU5_PLL_FMAB_OFF 3 1547#define PMU5_PLL_MRAT_MASK 0xf0000000 1548#define PMU5_PLL_MRAT_SHIFT 28 1549#define PMU5_PLL_ABRAT_MASK 0x08000000 1550#define PMU5_PLL_ABRAT_SHIFT 27 1551#define PMU5_PLL_FDIV_MASK 0x07ffffff 1552#define PMU5_PLL_PLLCTL_OFF 4 1553#define PMU5_PLL_PCHI_OFF 5 1554#define PMU5_PLL_PCHI_MASK 0x0000003f 1555 1556/* pmu XtalFreqRatio */ 1557#define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF 1558#define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 1559#define PMU_XTALFREQ_REG_MEASURE_SHIFT 31 1560 1561/* Divider allocation in 4716/47162/5356/5357 */ 1562#define PMU5_MAINPLL_CPU 1 1563#define PMU5_MAINPLL_MEM 2 1564#define PMU5_MAINPLL_SI 3 1565 1566/* 4706 PMU */ 1567#define PMU4706_MAINPLL_PLL0 0 1568#define PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */ 1569#define PMU6_4706_PROC_P2DIV_MASK 0x000f0000 1570#define PMU6_4706_PROC_P2DIV_SHIFT 16 1571#define PMU6_4706_PROC_P1DIV_MASK 0x0000f000 1572#define PMU6_4706_PROC_P1DIV_SHIFT 12 1573#define PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8 1574#define PMU6_4706_PROC_NDIV_INT_SHIFT 3 1575#define PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007 1576#define PMU6_4706_PROC_NDIV_MODE_SHIFT 0 1577 1578#define PMU7_PLL_PLLCTL7 7 1579#define PMU7_PLL_CTL7_M4DIV_MASK 0xff000000 1580#define PMU7_PLL_CTL7_M4DIV_SHIFT 24 1581#define PMU7_PLL_CTL7_M4DIV_BY_6 6 1582#define PMU7_PLL_CTL7_M4DIV_BY_12 0xc 1583#define PMU7_PLL_CTL7_M4DIV_BY_24 0x18 1584#define PMU7_PLL_PLLCTL8 8 1585#define PMU7_PLL_CTL8_M5DIV_MASK 0x000000ff 1586#define PMU7_PLL_CTL8_M5DIV_SHIFT 0 1587#define PMU7_PLL_CTL8_M5DIV_BY_8 8 1588#define PMU7_PLL_CTL8_M5DIV_BY_12 0xc 1589#define PMU7_PLL_CTL8_M5DIV_BY_24 0x18 1590#define PMU7_PLL_CTL8_M6DIV_MASK 0x0000ff00 1591#define PMU7_PLL_CTL8_M6DIV_SHIFT 8 1592#define PMU7_PLL_CTL8_M6DIV_BY_12 0xc 1593#define PMU7_PLL_CTL8_M6DIV_BY_24 0x18 1594#define PMU7_PLL_PLLCTL11 11 1595#define PMU7_PLL_PLLCTL11_MASK 0xffffff00 1596#define PMU7_PLL_PLLCTL11_VAL 0x22222200 1597 1598/* PMU rev 15 */ 1599#define PMU15_PLL_PLLCTL0 0 1600#define PMU15_PLL_PC0_CLKSEL_MASK 0x00000003 1601#define PMU15_PLL_PC0_CLKSEL_SHIFT 0 1602#define PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC 1603#define PMU15_PLL_PC0_FREQTGT_SHIFT 2 1604#define PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000 1605#define PMU15_PLL_PC0_PRESCALE_SHIFT 22 1606#define PMU15_PLL_PC0_KPCTRL_MASK 0x07000000 1607#define PMU15_PLL_PC0_KPCTRL_SHIFT 24 1608#define PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000 1609#define PMU15_PLL_PC0_FCNTCTRL_SHIFT 27 1610#define PMU15_PLL_PC0_FDCMODE_MASK 0x40000000 1611#define PMU15_PLL_PC0_FDCMODE_SHIFT 30 1612#define PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000 1613#define PMU15_PLL_PC0_CTRLBIAS_SHIFT 31 1614 1615#define PMU15_PLL_PLLCTL1 1 1616#define PMU15_PLL_PC1_BIAS_CTLM_MASK 0x00000060 1617#define PMU15_PLL_PC1_BIAS_CTLM_SHIFT 5 1618#define PMU15_PLL_PC1_BIAS_CTLM_RST_MASK 0x00000040 1619#define PMU15_PLL_PC1_BIAS_CTLM_RST_SHIFT 6 1620#define PMU15_PLL_PC1_BIAS_SS_DIVR_MASK 0x0001FF80 1621#define PMU15_PLL_PC1_BIAS_SS_DIVR_SHIFT 7 1622#define PMU15_PLL_PC1_BIAS_SS_RSTVAL_MASK 0x03FE0000 1623#define PMU15_PLL_PC1_BIAS_SS_RSTVAL_SHIFT 17 1624#define PMU15_PLL_PC1_BIAS_INTG_BW_MASK 0x0C000000 1625#define PMU15_PLL_PC1_BIAS_INTG_BW_SHIFT 26 1626#define PMU15_PLL_PC1_BIAS_INTG_BYP_MASK 0x10000000 1627#define PMU15_PLL_PC1_BIAS_INTG_BYP_SHIFT 28 1628#define PMU15_PLL_PC1_OPENLP_EN_MASK 0x40000000 1629#define PMU15_PLL_PC1_OPENLP_EN_SHIFT 30 1630 1631#define PMU15_PLL_PLLCTL2 2 1632#define PMU15_PLL_PC2_CTEN_MASK 0x00000001 1633#define PMU15_PLL_PC2_CTEN_SHIFT 0 1634 1635#define PMU15_PLL_PLLCTL3 3 1636#define PMU15_PLL_PC3_DITHER_EN_MASK 0x00000001 1637#define PMU15_PLL_PC3_DITHER_EN_SHIFT 0 1638#define PMU15_PLL_PC3_DCOCTLSP_MASK 0xFE000000 1639#define PMU15_PLL_PC3_DCOCTLSP_SHIFT 25 1640#define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_MASK 0x01 1641#define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_SHIFT 0 1642#define PMU15_PLL_PC3_DCOCTLSP_CH0EN_MASK 0x02 1643#define PMU15_PLL_PC3_DCOCTLSP_CH0EN_SHIFT 1 1644#define PMU15_PLL_PC3_DCOCTLSP_CH1EN_MASK 0x04 1645#define PMU15_PLL_PC3_DCOCTLSP_CH1EN_SHIFT 2 1646#define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_MASK 0x18 1647#define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_SHIFT 3 1648#define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_MASK 0x60 1649#define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_SHIFT 5 1650#define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV1 0 1651#define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV2 1 1652#define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV3 2 1653#define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV5 3 1654 1655#define PMU15_PLL_PLLCTL4 4 1656#define PMU15_PLL_PC4_FLLCLK1_DIV_MASK 0x00000007 1657#define PMU15_PLL_PC4_FLLCLK1_DIV_SHIFT 0 1658#define PMU15_PLL_PC4_FLLCLK2_DIV_MASK 0x00000038 1659#define PMU15_PLL_PC4_FLLCLK2_DIV_SHIFT 3 1660#define PMU15_PLL_PC4_FLLCLK3_DIV_MASK 0x000001C0 1661#define PMU15_PLL_PC4_FLLCLK3_DIV_SHIFT 6 1662#define PMU15_PLL_PC4_DBGMODE_MASK 0x00000E00 1663#define PMU15_PLL_PC4_DBGMODE_SHIFT 9 1664#define PMU15_PLL_PC4_FLL480_CTLSP_LK_MASK 0x00001000 1665#define PMU15_PLL_PC4_FLL480_CTLSP_LK_SHIFT 12 1666#define PMU15_PLL_PC4_FLL480_CTLSP_MASK 0x000FE000 1667#define PMU15_PLL_PC4_FLL480_CTLSP_SHIFT 13 1668#define PMU15_PLL_PC4_DINPOL_MASK 0x00100000 1669#define PMU15_PLL_PC4_DINPOL_SHIFT 20 1670#define PMU15_PLL_PC4_CLKOUT_PD_MASK 0x00200000 1671#define PMU15_PLL_PC4_CLKOUT_PD_SHIFT 21 1672#define PMU15_PLL_PC4_CLKDIV2_PD_MASK 0x00400000 1673#define PMU15_PLL_PC4_CLKDIV2_PD_SHIFT 22 1674#define PMU15_PLL_PC4_CLKDIV4_PD_MASK 0x00800000 1675#define PMU15_PLL_PC4_CLKDIV4_PD_SHIFT 23 1676#define PMU15_PLL_PC4_CLKDIV8_PD_MASK 0x01000000 1677#define PMU15_PLL_PC4_CLKDIV8_PD_SHIFT 24 1678#define PMU15_PLL_PC4_CLKDIV16_PD_MASK 0x02000000 1679#define PMU15_PLL_PC4_CLKDIV16_PD_SHIFT 25 1680#define PMU15_PLL_PC4_TEST_EN_MASK 0x04000000 1681#define PMU15_PLL_PC4_TEST_EN_SHIFT 26 1682 1683#define PMU15_PLL_PLLCTL5 5 1684#define PMU15_PLL_PC5_FREQTGT_MASK 0x000FFFFF 1685#define PMU15_PLL_PC5_FREQTGT_SHIFT 0 1686#define PMU15_PLL_PC5_DCOCTLSP_MASK 0x07F00000 1687#define PMU15_PLL_PC5_DCOCTLSP_SHIFT 20 1688#define PMU15_PLL_PC5_PRESCALE_MASK 0x18000000 1689#define PMU15_PLL_PC5_PRESCALE_SHIFT 27 1690 1691#define PMU15_PLL_PLLCTL6 6 1692#define PMU15_PLL_PC6_FREQTGT_MASK 0x000FFFFF 1693#define PMU15_PLL_PC6_FREQTGT_SHIFT 0 1694#define PMU15_PLL_PC6_DCOCTLSP_MASK 0x07F00000 1695#define PMU15_PLL_PC6_DCOCTLSP_SHIFT 20 1696#define PMU15_PLL_PC6_PRESCALE_MASK 0x18000000 1697#define PMU15_PLL_PC6_PRESCALE_SHIFT 27 1698 1699#define PMU15_FREQTGT_480_DEFAULT 0x19AB1 1700#define PMU15_FREQTGT_492_DEFAULT 0x1A4F5 1701#define PMU15_ARM_96MHZ 96000000 /* 96 Mhz */ 1702#define PMU15_ARM_98MHZ 98400000 /* 98.4 Mhz */ 1703#define PMU15_ARM_97MHZ 97000000 /* 97 Mhz */ 1704 1705 1706#define PMU17_PLLCTL2_NDIVTYPE_MASK 0x00000070 1707#define PMU17_PLLCTL2_NDIVTYPE_SHIFT 4 1708 1709#define PMU17_PLLCTL2_NDIV_MODE_INT 0 1710#define PMU17_PLLCTL2_NDIV_MODE_INT1B8 1 1711#define PMU17_PLLCTL2_NDIV_MODE_MASH111 2 1712#define PMU17_PLLCTL2_NDIV_MODE_MASH111B8 3 1713 1714#define PMU17_PLLCTL0_BBPLL_PWRDWN 0 1715#define PMU17_PLLCTL0_BBPLL_DRST 3 1716#define PMU17_PLLCTL0_BBPLL_DISBL_CLK 8 1717 1718/* PLL usage in 4716/47162 */ 1719#define PMU4716_MAINPLL_PLL0 12 1720 1721/* PLL usage in 4335 */ 1722#define PMU4335_PLL0_PC2_P1DIV_MASK 0x000f0000 1723#define PMU4335_PLL0_PC2_P1DIV_SHIFT 16 1724#define PMU4335_PLL0_PC2_NDIV_INT_MASK 0xff800000 1725#define PMU4335_PLL0_PC2_NDIV_INT_SHIFT 23 1726#define PMU4335_PLL0_PC1_MDIV2_MASK 0x0000ff00 1727#define PMU4335_PLL0_PC1_MDIV2_SHIFT 8 1728 1729 1730/* PLL usage in 5356/5357 */ 1731#define PMU5356_MAINPLL_PLL0 0 1732#define PMU5357_MAINPLL_PLL0 0 1733 1734/* 4716/47162 resources */ 1735#define RES4716_PROC_PLL_ON 0x00000040 1736#define RES4716_PROC_HT_AVAIL 0x00000080 1737 1738/* 4716/4717/4718 Chip specific ChipControl register bits */ 1739#define CCTRL_471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared w/ pflash */ 1740 1741/* 5357 Chip specific ChipControl register bits */ 1742/* 2nd - 32-bit reg */ 1743#define CCTRL_5357_I2S_PINS_ENABLE 0x00040000 /* I2S pins enable */ 1744#define CCTRL_5357_I2CSPI_PINS_ENABLE 0x00080000 /* I2C/SPI pins enable */ 1745 1746/* 5354 resources */ 1747#define RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */ 1748#define RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */ 1749#define RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */ 1750#define RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ 1751#define RES5354_ILP_REQUEST 4 /* 0x00010 */ 1752#define RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */ 1753#define RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */ 1754#define RES5354_ROM_SWITCH 7 /* 0x00080 */ 1755#define RES5354_PA_REF_LDO 8 /* 0x00100 */ 1756#define RES5354_RADIO_LDO 9 /* 0x00200 */ 1757#define RES5354_AFE_LDO 10 /* 0x00400 */ 1758#define RES5354_PLL_LDO 11 /* 0x00800 */ 1759#define RES5354_BG_FILTBYP 12 /* 0x01000 */ 1760#define RES5354_TX_FILTBYP 13 /* 0x02000 */ 1761#define RES5354_RX_FILTBYP 14 /* 0x04000 */ 1762#define RES5354_XTAL_PU 15 /* 0x08000 */ 1763#define RES5354_XTAL_EN 16 /* 0x10000 */ 1764#define RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */ 1765#define RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */ 1766#define RES5354_BB_PLL_PU 19 /* 0x80000 */ 1767 1768/* 5357 Chip specific ChipControl register bits */ 1769#define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */ 1770#define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */ 1771#define CCTRL5357_NFLASH (1<<16) /* Nandflash in ChipControl 1, bit 16 */ 1772 1773/* 43217 Chip specific ChipControl register bits */ 1774#define CCTRL43217_EXTPA_C0 (1<<13) /* core0 extPA in ChipControl 1, bit 13 */ 1775#define CCTRL43217_EXTPA_C1 (1<<8) /* core1 extPA in ChipControl 1, bit 8 */ 1776 1777/* 43228 Chip specific ChipControl register bits */ 1778#define CCTRL43228_EXTPA_C0 (1<<14) /* core1 extPA in ChipControl 1, bit 14 */ 1779#define CCTRL43228_EXTPA_C1 (1<<9) /* core0 extPA in ChipControl 1, bit 1 */ 1780 1781/* 4328 resources */ 1782#define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */ 1783#define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */ 1784#define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */ 1785#define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ 1786#define RES4328_ILP_REQUEST 4 /* 0x00010 */ 1787#define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */ 1788#define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */ 1789#define RES4328_ROM_SWITCH 7 /* 0x00080 */ 1790#define RES4328_PA_REF_LDO 8 /* 0x00100 */ 1791#define RES4328_RADIO_LDO 9 /* 0x00200 */ 1792#define RES4328_AFE_LDO 10 /* 0x00400 */ 1793#define RES4328_PLL_LDO 11 /* 0x00800 */ 1794#define RES4328_BG_FILTBYP 12 /* 0x01000 */ 1795#define RES4328_TX_FILTBYP 13 /* 0x02000 */ 1796#define RES4328_RX_FILTBYP 14 /* 0x04000 */ 1797#define RES4328_XTAL_PU 15 /* 0x08000 */ 1798#define RES4328_XTAL_EN 16 /* 0x10000 */ 1799#define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */ 1800#define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */ 1801#define RES4328_BB_PLL_PU 19 /* 0x80000 */ 1802 1803/* 4325 A0/A1 resources */ 1804#define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */ 1805#define RES4325_CBUCK_BURST 1 /* 0x00000002 */ 1806#define RES4325_CBUCK_PWM 2 /* 0x00000004 */ 1807#define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */ 1808#define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */ 1809#define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */ 1810#define RES4325_ILP_REQUEST 6 /* 0x00000040 */ 1811#define RES4325_ABUCK_BURST 7 /* 0x00000080 */ 1812#define RES4325_ABUCK_PWM 8 /* 0x00000100 */ 1813#define RES4325_LNLDO1_PU 9 /* 0x00000200 */ 1814#define RES4325_OTP_PU 10 /* 0x00000400 */ 1815#define RES4325_LNLDO3_PU 11 /* 0x00000800 */ 1816#define RES4325_LNLDO4_PU 12 /* 0x00001000 */ 1817#define RES4325_XTAL_PU 13 /* 0x00002000 */ 1818#define RES4325_ALP_AVAIL 14 /* 0x00004000 */ 1819#define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */ 1820#define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */ 1821#define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1822#define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1823#define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */ 1824#define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1825#define RES4325_HT_AVAIL 21 /* 0x00200000 */ 1826 1827/* 4325 B0/C0 resources */ 1828#define RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */ 1829#define RES4325B0_CBUCK_BURST 2 /* 0x00000004 */ 1830#define RES4325B0_CBUCK_PWM 3 /* 0x00000008 */ 1831#define RES4325B0_CLDO_PU 4 /* 0x00000010 */ 1832 1833/* 4325 C1 resources */ 1834#define RES4325C1_LNLDO2_PU 12 /* 0x00001000 */ 1835 1836/* 4325 chip-specific ChipStatus register bits */ 1837#define CST4325_SPROM_OTP_SEL_MASK 0x00000003 1838#define CST4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ 1839#define CST4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ 1840#define CST4325_OTP_SEL 2 /* OTP is powered up, no SPROM */ 1841#define CST4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */ 1842#define CST4325_SDIO_USB_MODE_MASK 0x00000004 1843#define CST4325_SDIO_USB_MODE_SHIFT 2 1844#define CST4325_RCAL_VALID_MASK 0x00000008 1845#define CST4325_RCAL_VALID_SHIFT 3 1846#define CST4325_RCAL_VALUE_MASK 0x000001f0 1847#define CST4325_RCAL_VALUE_SHIFT 4 1848#define CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */ 1849#define CST4325_PMUTOP_2B_SHIFT 9 1850 1851#define RES4329_RESERVED0 0 /* 0x00000001 */ 1852#define RES4329_CBUCK_LPOM 1 /* 0x00000002 */ 1853#define RES4329_CBUCK_BURST 2 /* 0x00000004 */ 1854#define RES4329_CBUCK_PWM 3 /* 0x00000008 */ 1855#define RES4329_CLDO_PU 4 /* 0x00000010 */ 1856#define RES4329_PALDO_PU 5 /* 0x00000020 */ 1857#define RES4329_ILP_REQUEST 6 /* 0x00000040 */ 1858#define RES4329_RESERVED7 7 /* 0x00000080 */ 1859#define RES4329_RESERVED8 8 /* 0x00000100 */ 1860#define RES4329_LNLDO1_PU 9 /* 0x00000200 */ 1861#define RES4329_OTP_PU 10 /* 0x00000400 */ 1862#define RES4329_RESERVED11 11 /* 0x00000800 */ 1863#define RES4329_LNLDO2_PU 12 /* 0x00001000 */ 1864#define RES4329_XTAL_PU 13 /* 0x00002000 */ 1865#define RES4329_ALP_AVAIL 14 /* 0x00004000 */ 1866#define RES4329_RX_PWRSW_PU 15 /* 0x00008000 */ 1867#define RES4329_TX_PWRSW_PU 16 /* 0x00010000 */ 1868#define RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1869#define RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1870#define RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */ 1871#define RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1872#define RES4329_HT_AVAIL 21 /* 0x00200000 */ 1873 1874#define CST4329_SPROM_OTP_SEL_MASK 0x00000003 1875#define CST4329_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ 1876#define CST4329_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ 1877#define CST4329_OTP_SEL 2 /* OTP is powered up, no SPROM */ 1878#define CST4329_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */ 1879#define CST4329_SPI_SDIO_MODE_MASK 0x00000004 1880#define CST4329_SPI_SDIO_MODE_SHIFT 2 1881 1882/* 4312 chip-specific ChipStatus register bits */ 1883#define CST4312_SPROM_OTP_SEL_MASK 0x00000003 1884#define CST4312_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ 1885#define CST4312_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ 1886#define CST4312_OTP_SEL 2 /* OTP is powered up, no SPROM */ 1887#define CST4312_OTP_BAD 3 /* OTP is broken, SPROM is present */ 1888 1889/* 4312 resources (all PMU chips with little memory constraint) */ 1890#define RES4312_SWITCHER_BURST 0 /* 0x00000001 */ 1891#define RES4312_SWITCHER_PWM 1 /* 0x00000002 */ 1892#define RES4312_PA_REF_LDO 2 /* 0x00000004 */ 1893#define RES4312_CORE_LDO_BURST 3 /* 0x00000008 */ 1894#define RES4312_CORE_LDO_PWM 4 /* 0x00000010 */ 1895#define RES4312_RADIO_LDO 5 /* 0x00000020 */ 1896#define RES4312_ILP_REQUEST 6 /* 0x00000040 */ 1897#define RES4312_BG_FILTBYP 7 /* 0x00000080 */ 1898#define RES4312_TX_FILTBYP 8 /* 0x00000100 */ 1899#define RES4312_RX_FILTBYP 9 /* 0x00000200 */ 1900#define RES4312_XTAL_PU 10 /* 0x00000400 */ 1901#define RES4312_ALP_AVAIL 11 /* 0x00000800 */ 1902#define RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */ 1903#define RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */ 1904#define RES4312_HT_AVAIL 14 /* 0x00004000 */ 1905 1906/* 4322 resources */ 1907#define RES4322_RF_LDO 0 1908#define RES4322_ILP_REQUEST 1 1909#define RES4322_XTAL_PU 2 1910#define RES4322_ALP_AVAIL 3 1911#define RES4322_SI_PLL_ON 4 1912#define RES4322_HT_SI_AVAIL 5 1913#define RES4322_PHY_PLL_ON 6 1914#define RES4322_HT_PHY_AVAIL 7 1915#define RES4322_OTP_PU 8 1916 1917/* 4322 chip-specific ChipStatus register bits */ 1918#define CST4322_XTAL_FREQ_20_40MHZ 0x00000020 1919#define CST4322_SPROM_OTP_SEL_MASK 0x000000c0 1920#define CST4322_SPROM_OTP_SEL_SHIFT 6 1921#define CST4322_NO_SPROM_OTP 0 /* no OTP, no SPROM */ 1922#define CST4322_SPROM_PRESENT 1 /* SPROM is present */ 1923#define CST4322_OTP_PRESENT 2 /* OTP is present */ 1924#define CST4322_PCI_OR_USB 0x00000100 1925#define CST4322_BOOT_MASK 0x00000600 1926#define CST4322_BOOT_SHIFT 9 1927#define CST4322_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ 1928#define CST4322_BOOT_FROM_ROM 1 /* boot from ROM */ 1929#define CST4322_BOOT_FROM_FLASH 2 /* boot from FLASH */ 1930#define CST4322_BOOT_FROM_INVALID 3 1931#define CST4322_ILP_DIV_EN 0x00000800 1932#define CST4322_FLASH_TYPE_MASK 0x00001000 1933#define CST4322_FLASH_TYPE_SHIFT 12 1934#define CST4322_FLASH_TYPE_SHIFT_ST 0 /* ST serial FLASH */ 1935#define CST4322_FLASH_TYPE_SHIFT_ATMEL 1 /* ATMEL flash */ 1936#define CST4322_ARM_TAP_SEL 0x00002000 1937#define CST4322_RES_INIT_MODE_MASK 0x0000c000 1938#define CST4322_RES_INIT_MODE_SHIFT 14 1939#define CST4322_RES_INIT_MODE_ILPAVAIL 0 /* resinitmode: ILP available */ 1940#define CST4322_RES_INIT_MODE_ILPREQ 1 /* resinitmode: ILP request */ 1941#define CST4322_RES_INIT_MODE_ALPAVAIL 2 /* resinitmode: ALP available */ 1942#define CST4322_RES_INIT_MODE_HTAVAIL 3 /* resinitmode: HT available */ 1943#define CST4322_PCIPLLCLK_GATING 0x00010000 1944#define CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000 1945#define CST4322_PCI_CARDBUS_MODE 0x00040000 1946 1947/* 43224 chip-specific ChipControl register bits */ 1948#define CCTRL43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */ 1949#define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ 1950#define CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ 1951 1952/* 43236 resources */ 1953#define RES43236_REGULATOR 0 1954#define RES43236_ILP_REQUEST 1 1955#define RES43236_XTAL_PU 2 1956#define RES43236_ALP_AVAIL 3 1957#define RES43236_SI_PLL_ON 4 1958#define RES43236_HT_SI_AVAIL 5 1959 1960/* 43236 chip-specific ChipControl register bits */ 1961#define CCTRL43236_BT_COEXIST (1<<0) /* 0 disable */ 1962#define CCTRL43236_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ 1963#define CCTRL43236_EXT_LNA (1<<2) /* 0 disable */ 1964#define CCTRL43236_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */ 1965#define CCTRL43236_GSIO (1<<4) /* 0 disable */ 1966 1967/* 43236 Chip specific ChipStatus register bits */ 1968#define CST43236_SFLASH_MASK 0x00000040 1969#define CST43236_OTP_SEL_MASK 0x00000080 1970#define CST43236_OTP_SEL_SHIFT 7 1971#define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */ 1972#define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */ 1973#define CST43236_BOOT_MASK 0x00001800 1974#define CST43236_BOOT_SHIFT 11 1975#define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ 1976#define CST43236_BOOT_FROM_ROM 1 /* boot from ROM */ 1977#define CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */ 1978#define CST43236_BOOT_FROM_INVALID 3 1979 1980/* 43237 resources */ 1981#define RES43237_REGULATOR 0 1982#define RES43237_ILP_REQUEST 1 1983#define RES43237_XTAL_PU 2 1984#define RES43237_ALP_AVAIL 3 1985#define RES43237_SI_PLL_ON 4 1986#define RES43237_HT_SI_AVAIL 5 1987 1988/* 43237 chip-specific ChipControl register bits */ 1989#define CCTRL43237_BT_COEXIST (1<<0) /* 0 disable */ 1990#define CCTRL43237_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ 1991#define CCTRL43237_EXT_LNA (1<<2) /* 0 disable */ 1992#define CCTRL43237_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */ 1993#define CCTRL43237_GSIO (1<<4) /* 0 disable */ 1994 1995/* 43237 Chip specific ChipStatus register bits */ 1996#define CST43237_SFLASH_MASK 0x00000040 1997#define CST43237_OTP_SEL_MASK 0x00000080 1998#define CST43237_OTP_SEL_SHIFT 7 1999#define CST43237_HSIC_MASK 0x00000100 /* USB/HSIC */ 2000#define CST43237_BP_CLK 0x00000200 /* 120/96Mbps */ 2001#define CST43237_BOOT_MASK 0x00001800 2002#define CST43237_BOOT_SHIFT 11 2003#define CST43237_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ 2004#define CST43237_BOOT_FROM_ROM 1 /* boot from ROM */ 2005#define CST43237_BOOT_FROM_FLASH 2 /* boot from FLASH */ 2006#define CST43237_BOOT_FROM_INVALID 3 2007 2008/* 43239 resources */ 2009#define RES43239_OTP_PU 9 2010#define RES43239_MACPHY_CLKAVAIL 23 2011#define RES43239_HT_AVAIL 24 2012 2013/* 43239 Chip specific ChipStatus register bits */ 2014#define CST43239_SPROM_MASK 0x00000002 2015#define CST43239_SFLASH_MASK 0x00000004 2016#define CST43239_RES_INIT_MODE_SHIFT 7 2017#define CST43239_RES_INIT_MODE_MASK 0x000001f0 2018#define CST43239_CHIPMODE_SDIOD(cs) ((cs) & (1 << 15)) /* SDIO || gSPI */ 2019#define CST43239_CHIPMODE_USB20D(cs) (~(cs) & (1 << 15)) /* USB || USBDA */ 2020#define CST43239_CHIPMODE_SDIO(cs) (((cs) & (1 << 0)) == 0) /* SDIO */ 2021#define CST43239_CHIPMODE_GSPI(cs) (((cs) & (1 << 0)) == (1 << 0)) /* gSPI */ 2022 2023/* 4324 resources */ 2024/* 43242 use same PMU as 4324 */ 2025#define RES4324_LPLDO_PU 0 2026#define RES4324_RESET_PULLDN_DIS 1 2027#define RES4324_PMU_BG_PU 2 2028#define RES4324_HSIC_LDO_PU 3 2029#define RES4324_CBUCK_LPOM_PU 4 2030#define RES4324_CBUCK_PFM_PU 5 2031#define RES4324_CLDO_PU 6 2032#define RES4324_LPLDO2_LVM 7 2033#define RES4324_LNLDO1_PU 8 2034#define RES4324_LNLDO2_PU 9 2035#define RES4324_LDO3P3_PU 10 2036#define RES4324_OTP_PU 11 2037#define RES4324_XTAL_PU 12 2038#define RES4324_BBPLL_PU 13 2039#define RES4324_LQ_AVAIL 14 2040#define RES4324_WL_CORE_READY 17 2041#define RES4324_ILP_REQ 18 2042#define RES4324_ALP_AVAIL 19 2043#define RES4324_PALDO_PU 20 2044#define RES4324_RADIO_PU 21 2045#define RES4324_SR_CLK_STABLE 22 2046#define RES4324_SR_SAVE_RESTORE 23 2047#define RES4324_SR_PHY_PWRSW 24 2048#define RES4324_SR_PHY_PIC 25 2049#define RES4324_SR_SUBCORE_PWRSW 26 2050#define RES4324_SR_SUBCORE_PIC 27 2051#define RES4324_SR_MEM_PM0 28 2052#define RES4324_HT_AVAIL 29 2053#define RES4324_MACPHY_CLKAVAIL 30 2054 2055/* 4324 Chip specific ChipStatus register bits */ 2056#define CST4324_SPROM_MASK 0x00000080 2057#define CST4324_SFLASH_MASK 0x00400000 2058#define CST4324_RES_INIT_MODE_SHIFT 10 2059#define CST4324_RES_INIT_MODE_MASK 0x00000c00 2060#define CST4324_CHIPMODE_MASK 0x7 2061#define CST4324_CHIPMODE_SDIOD(cs) ((~(cs)) & (1 << 2)) /* SDIO || gSPI */ 2062#define CST4324_CHIPMODE_USB20D(cs) (((cs) & CST4324_CHIPMODE_MASK) == 0x6) /* USB || USBDA */ 2063 2064/* 43242 Chip specific ChipStatus register bits */ 2065#define CST43242_SFLASH_MASK 0x00000008 2066#define CST43242_SR_HALT (1<<25) 2067#define CST43242_SR_CHIP_STATUS_2 27 /* bit 27 */ 2068 2069/* 4331 resources */ 2070#define RES4331_REGULATOR 0 2071#define RES4331_ILP_REQUEST 1 2072#define RES4331_XTAL_PU 2 2073#define RES4331_ALP_AVAIL 3 2074#define RES4331_SI_PLL_ON 4 2075#define RES4331_HT_SI_AVAIL 5 2076 2077/* 4331 chip-specific ChipControl register bits */ 2078#define CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */ 2079#define CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ 2080#define CCTRL4331_EXT_LNA_G (1<<2) /* 0 disable */ 2081#define CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */ 2082#define CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */ 2083#define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */ 2084#define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */ 2085#define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */ 2086#define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */ 2087#define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */ 2088#define CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */ 2089#define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */ 2090#define CCTRL4331_EXTPA_EN2 (1<<12) /* 0 ext pa disable, 1 ext pa enabled */ 2091#define CCTRL4331_EXT_LNA_A (1<<13) /* 0 disable */ 2092#define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */ 2093#define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */ 2094#define CCTRL4331_EXTPA_ANA_EN (1<<24) /* 0 ext pa disable, 1 ext pa enabled */ 2095 2096/* 4331 Chip specific ChipStatus register bits */ 2097#define CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */ 2098#define CST4331_SPROM_OTP_SEL_MASK 0x00000006 2099#define CST4331_SPROM_OTP_SEL_SHIFT 1 2100#define CST4331_SPROM_PRESENT 0x00000002 2101#define CST4331_OTP_PRESENT 0x00000004 2102#define CST4331_LDO_RF 0x00000008 2103#define CST4331_LDO_PAR 0x00000010 2104 2105/* 4315 resource */ 2106#define RES4315_CBUCK_LPOM 1 /* 0x00000002 */ 2107#define RES4315_CBUCK_BURST 2 /* 0x00000004 */ 2108#define RES4315_CBUCK_PWM 3 /* 0x00000008 */ 2109#define RES4315_CLDO_PU 4 /* 0x00000010 */ 2110#define RES4315_PALDO_PU 5 /* 0x00000020 */ 2111#define RES4315_ILP_REQUEST 6 /* 0x00000040 */ 2112#define RES4315_LNLDO1_PU 9 /* 0x00000200 */ 2113#define RES4315_OTP_PU 10 /* 0x00000400 */ 2114#define RES4315_LNLDO2_PU 12 /* 0x00001000 */ 2115#define RES4315_XTAL_PU 13 /* 0x00002000 */ 2116#define RES4315_ALP_AVAIL 14 /* 0x00004000 */ 2117#define RES4315_RX_PWRSW_PU 15 /* 0x00008000 */ 2118#define RES4315_TX_PWRSW_PU 16 /* 0x00010000 */ 2119#define RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 2120#define RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 2121#define RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */ 2122#define RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 2123#define RES4315_HT_AVAIL 21 /* 0x00200000 */ 2124 2125/* 4315 chip-specific ChipStatus register bits */ 2126#define CST4315_SPROM_OTP_SEL_MASK 0x00000003 /* gpio [7:6], SDIO CIS selection */ 2127#define CST4315_DEFCIS_SEL 0x00000000 /* use default CIS, OTP is powered up */ 2128#define CST4315_SPROM_SEL 0x00000001 /* use SPROM, OTP is powered up */ 2129#define CST4315_OTP_SEL 0x00000002 /* use OTP, OTP is powered up */ 2130#define CST4315_OTP_PWRDN 0x00000003 /* use SPROM, OTP is powered down */ 2131#define CST4315_SDIO_MODE 0x00000004 /* gpio [8], sdio/usb mode */ 2132#define CST4315_RCAL_VALID 0x00000008 2133#define CST4315_RCAL_VALUE_MASK 0x000001f0 2134#define CST4315_RCAL_VALUE_SHIFT 4 2135#define CST4315_PALDO_EXTPNP 0x00000200 /* PALDO is configured with external PNP */ 2136#define CST4315_CBUCK_MODE_MASK 0x00000c00 2137#define CST4315_CBUCK_MODE_BURST 0x00000400 2138#define CST4315_CBUCK_MODE_LPBURST 0x00000c00 2139 2140/* 4319 resources */ 2141#define RES4319_CBUCK_LPOM 1 /* 0x00000002 */ 2142#define RES4319_CBUCK_BURST 2 /* 0x00000004 */ 2143#define RES4319_CBUCK_PWM 3 /* 0x00000008 */ 2144#define RES4319_CLDO_PU 4 /* 0x00000010 */ 2145#define RES4319_PALDO_PU 5 /* 0x00000020 */ 2146#define RES4319_ILP_REQUEST 6 /* 0x00000040 */ 2147#define RES4319_LNLDO1_PU 9 /* 0x00000200 */ 2148#define RES4319_OTP_PU 10 /* 0x00000400 */ 2149#define RES4319_LNLDO2_PU 12 /* 0x00001000 */ 2150#define RES4319_XTAL_PU 13 /* 0x00002000 */ 2151#define RES4319_ALP_AVAIL 14 /* 0x00004000 */ 2152#define RES4319_RX_PWRSW_PU 15 /* 0x00008000 */ 2153#define RES4319_TX_PWRSW_PU 16 /* 0x00010000 */ 2154#define RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 2155#define RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 2156#define RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */ 2157#define RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 2158#define RES4319_HT_AVAIL 21 /* 0x00200000 */ 2159 2160/* 4319 chip-specific ChipStatus register bits */ 2161#define CST4319_SPI_CPULESSUSB 0x00000001 2162#define CST4319_SPI_CLK_POL 0x00000002 2163#define CST4319_SPI_CLK_PH 0x00000008 2164#define CST4319_SPROM_OTP_SEL_MASK 0x000000c0 /* gpio [7:6], SDIO CIS selection */ 2165#define CST4319_SPROM_OTP_SEL_SHIFT 6 2166#define CST4319_DEFCIS_SEL 0x00000000 /* use default CIS, OTP is powered up */ 2167#define CST4319_SPROM_SEL 0x00000040 /* use SPROM, OTP is powered up */ 2168#define CST4319_OTP_SEL 0x00000080 /* use OTP, OTP is powered up */ 2169#define CST4319_OTP_PWRDN 0x000000c0 /* use SPROM, OTP is powered down */ 2170#define CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */ 2171#define CST4319_REMAP_SEL_MASK 0x00000600 2172#define CST4319_ILPDIV_EN 0x00000800 2173#define CST4319_XTAL_PD_POL 0x00001000 2174#define CST4319_LPO_SEL 0x00002000 2175#define CST4319_RES_INIT_MODE 0x0000c000 2176#define CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */ 2177#define CST4319_CBUCK_MODE_MASK 0x00060000 2178#define CST4319_CBUCK_MODE_BURST 0x00020000 2179#define CST4319_CBUCK_MODE_LPBURST 0x00060000 2180#define CST4319_RCAL_VALID 0x01000000 2181#define CST4319_RCAL_VALUE_MASK 0x3e000000 2182#define CST4319_RCAL_VALUE_SHIFT 25 2183 2184#define PMU1_PLL0_CHIPCTL0 0 2185#define PMU1_PLL0_CHIPCTL1 1 2186#define PMU1_PLL0_CHIPCTL2 2 2187#define CCTL_4319USB_XTAL_SEL_MASK 0x00180000 2188#define CCTL_4319USB_XTAL_SEL_SHIFT 19 2189#define CCTL_4319USB_48MHZ_PLL_SEL 1 2190#define CCTL_4319USB_24MHZ_PLL_SEL 2 2191 2192/* PMU resources for 4336 */ 2193#define RES4336_CBUCK_LPOM 0 2194#define RES4336_CBUCK_BURST 1 2195#define RES4336_CBUCK_LP_PWM 2 2196#define RES4336_CBUCK_PWM 3 2197#define RES4336_CLDO_PU 4 2198#define RES4336_DIS_INT_RESET_PD 5 2199#define RES4336_ILP_REQUEST 6 2200#define RES4336_LNLDO_PU 7 2201#define RES4336_LDO3P3_PU 8 2202#define RES4336_OTP_PU 9 2203#define RES4336_XTAL_PU 10 2204#define RES4336_ALP_AVAIL 11 2205#define RES4336_RADIO_PU 12 2206#define RES4336_BG_PU 13 2207#define RES4336_VREG1p4_PU_PU 14 2208#define RES4336_AFE_PWRSW_PU 15 2209#define RES4336_RX_PWRSW_PU 16 2210#define RES4336_TX_PWRSW_PU 17 2211#define RES4336_BB_PWRSW_PU 18 2212#define RES4336_SYNTH_PWRSW_PU 19 2213#define RES4336_MISC_PWRSW_PU 20 2214#define RES4336_LOGEN_PWRSW_PU 21 2215#define RES4336_BBPLL_PWRSW_PU 22 2216#define RES4336_MACPHY_CLKAVAIL 23 2217#define RES4336_HT_AVAIL 24 2218#define RES4336_RSVD 25 2219 2220/* 4336 chip-specific ChipStatus register bits */ 2221#define CST4336_SPI_MODE_MASK 0x00000001 2222#define CST4336_SPROM_PRESENT 0x00000002 2223#define CST4336_OTP_PRESENT 0x00000004 2224#define CST4336_ARMREMAP_0 0x00000008 2225#define CST4336_ILPDIV_EN_MASK 0x00000010 2226#define CST4336_ILPDIV_EN_SHIFT 4 2227#define CST4336_XTAL_PD_POL_MASK 0x00000020 2228#define CST4336_XTAL_PD_POL_SHIFT 5 2229#define CST4336_LPO_SEL_MASK 0x00000040 2230#define CST4336_LPO_SEL_SHIFT 6 2231#define CST4336_RES_INIT_MODE_MASK 0x00000180 2232#define CST4336_RES_INIT_MODE_SHIFT 7 2233#define CST4336_CBUCK_MODE_MASK 0x00000600 2234#define CST4336_CBUCK_MODE_SHIFT 9 2235 2236/* 4336 Chip specific PMU ChipControl register bits */ 2237#define PCTL_4336_SERIAL_ENAB (1 << 24) 2238 2239/* 4330 resources */ 2240#define RES4330_CBUCK_LPOM 0 2241#define RES4330_CBUCK_BURST 1 2242#define RES4330_CBUCK_LP_PWM 2 2243#define RES4330_CBUCK_PWM 3 2244#define RES4330_CLDO_PU 4 2245#define RES4330_DIS_INT_RESET_PD 5 2246#define RES4330_ILP_REQUEST 6 2247#define RES4330_LNLDO_PU 7 2248#define RES4330_LDO3P3_PU 8 2249#define RES4330_OTP_PU 9 2250#define RES4330_XTAL_PU 10 2251#define RES4330_ALP_AVAIL 11 2252#define RES4330_RADIO_PU 12 2253#define RES4330_BG_PU 13 2254#define RES4330_VREG1p4_PU_PU 14 2255#define RES4330_AFE_PWRSW_PU 15 2256#define RES4330_RX_PWRSW_PU 16 2257#define RES4330_TX_PWRSW_PU 17 2258#define RES4330_BB_PWRSW_PU 18 2259#define RES4330_SYNTH_PWRSW_PU 19 2260#define RES4330_MISC_PWRSW_PU 20 2261#define RES4330_LOGEN_PWRSW_PU 21 2262#define RES4330_BBPLL_PWRSW_PU 22 2263#define RES4330_MACPHY_CLKAVAIL 23 2264#define RES4330_HT_AVAIL 24 2265#define RES4330_5gRX_PWRSW_PU 25 2266#define RES4330_5gTX_PWRSW_PU 26 2267#define RES4330_5g_LOGEN_PWRSW_PU 27 2268 2269/* 4330 chip-specific ChipStatus register bits */ 2270#define CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */ 2271#define CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */ 2272#define CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */ 2273#define CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */ 2274#define CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */ 2275#define CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */ 2276#define CST4330_OTP_PRESENT 0x00000010 2277#define CST4330_LPO_AUTODET_EN 0x00000020 2278#define CST4330_ARMREMAP_0 0x00000040 2279#define CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */ 2280#define CST4330_ILPDIV_EN 0x00000100 2281#define CST4330_LPO_SEL 0x00000200 2282#define CST4330_RES_INIT_MODE_SHIFT 10 2283#define CST4330_RES_INIT_MODE_MASK 0x00000c00 2284#define CST4330_CBUCK_MODE_SHIFT 12 2285#define CST4330_CBUCK_MODE_MASK 0x00003000 2286#define CST4330_CBUCK_POWER_OK 0x00004000 2287#define CST4330_BB_PLL_LOCKED 0x00008000 2288#define SOCDEVRAM_BP_ADDR 0x1E000000 2289#define SOCDEVRAM_ARM_ADDR 0x00800000 2290 2291/* 4330 Chip specific PMU ChipControl register bits */ 2292#define PCTL_4330_SERIAL_ENAB (1 << 24) 2293 2294/* 4330 Chip specific ChipControl register bits */ 2295#define CCTRL_4330_GPIO_SEL 0x00000001 /* 1=select GPIOs to be muxed out */ 2296#define CCTRL_4330_ERCX_SEL 0x00000002 /* 1=select ERCX BT coex to be muxed out */ 2297#define CCTRL_4330_SDIO_HOST_WAKE 0x00000004 /* SDIO: 1=configure GPIO0 for host wake */ 2298#define CCTRL_4330_JTAG_DISABLE 0x00000008 /* 1=disable JTAG interface on mux'd pins */ 2299 2300#define PMU_VREG0_ADDR 0 2301#define PMU_VREG0_DISABLE_PULLD_BT_SHIFT 2 2302#define PMU_VREG0_DISABLE_PULLD_WL_SHIFT 3 2303 2304#define PMU_VREG4_ADDR 4 2305 2306#define PMU_VREG4_CLDO_PWM_SHIFT 4 2307#define PMU_VREG4_CLDO_PWM_MASK 0x7 2308 2309#define PMU_VREG4_LPLDO1_SHIFT 15 2310#define PMU_VREG4_LPLDO1_MASK 0x7 2311#define PMU_VREG4_LPLDO1_1p20V 0 2312#define PMU_VREG4_LPLDO1_1p15V 1 2313#define PMU_VREG4_LPLDO1_1p10V 2 2314#define PMU_VREG4_LPLDO1_1p25V 3 2315#define PMU_VREG4_LPLDO1_1p05V 4 2316#define PMU_VREG4_LPLDO1_1p00V 5 2317#define PMU_VREG4_LPLDO1_0p95V 6 2318#define PMU_VREG4_LPLDO1_0p90V 7 2319 2320/* 4350/4345 VREG4 settings */ 2321#define PMU4350_VREG4_LPLDO1_1p10V 0 2322#define PMU4350_VREG4_LPLDO1_1p15V 1 2323#define PMU4350_VREG4_LPLDO1_1p21V 2 2324#define PMU4350_VREG4_LPLDO1_1p24V 3 2325#define PMU4350_VREG4_LPLDO1_0p90V 4 2326#define PMU4350_VREG4_LPLDO1_0p96V 5 2327#define PMU4350_VREG4_LPLDO1_1p01V 6 2328#define PMU4350_VREG4_LPLDO1_1p04V 7 2329 2330#define PMU_VREG4_LPLDO2_LVM_SHIFT 18 2331#define PMU_VREG4_LPLDO2_LVM_MASK 0x7 2332#define PMU_VREG4_LPLDO2_HVM_SHIFT 21 2333#define PMU_VREG4_LPLDO2_HVM_MASK 0x7 2334#define PMU_VREG4_LPLDO2_LVM_HVM_MASK 0x3f 2335#define PMU_VREG4_LPLDO2_1p00V 0 2336#define PMU_VREG4_LPLDO2_1p15V 1 2337#define PMU_VREG4_LPLDO2_1p20V 2 2338#define PMU_VREG4_LPLDO2_1p10V 3 2339#define PMU_VREG4_LPLDO2_0p90V 4 /* 4 - 7 is 0.90V */ 2340 2341#define PMU_VREG4_HSICLDO_BYPASS_SHIFT 27 2342#define PMU_VREG4_HSICLDO_BYPASS_MASK 0x1 2343 2344#define PMU_VREG5_ADDR 5 2345#define PMU_VREG5_HSICAVDD_PD_SHIFT 6 2346#define PMU_VREG5_HSICAVDD_PD_MASK 0x1 2347#define PMU_VREG5_HSICDVDD_PD_SHIFT 11 2348#define PMU_VREG5_HSICDVDD_PD_MASK 0x1 2349 2350/* 4334 resources */ 2351#define RES4334_LPLDO_PU 0 2352#define RES4334_RESET_PULLDN_DIS 1 2353#define RES4334_PMU_BG_PU 2 2354#define RES4334_HSIC_LDO_PU 3 2355#define RES4334_CBUCK_LPOM_PU 4 2356#define RES4334_CBUCK_PFM_PU 5 2357#define RES4334_CLDO_PU 6 2358#define RES4334_LPLDO2_LVM 7 2359#define RES4334_LNLDO_PU 8 2360#define RES4334_LDO3P3_PU 9 2361#define RES4334_OTP_PU 10 2362#define RES4334_XTAL_PU 11 2363#define RES4334_WL_PWRSW_PU 12 2364#define RES4334_LQ_AVAIL 13 2365#define RES4334_LOGIC_RET 14 2366#define RES4334_MEM_SLEEP 15 2367#define RES4334_MACPHY_RET 16 2368#define RES4334_WL_CORE_READY 17 2369#define RES4334_ILP_REQ 18 2370#define RES4334_ALP_AVAIL 19 2371#define RES4334_MISC_PWRSW_PU 20 2372#define RES4334_SYNTH_PWRSW_PU 21 2373#define RES4334_RX_PWRSW_PU 22 2374#define RES4334_RADIO_PU 23 2375#define RES4334_WL_PMU_PU 24 2376#define RES4334_VCO_LDO_PU 25 2377#define RES4334_AFE_LDO_PU 26 2378#define RES4334_RX_LDO_PU 27 2379#define RES4334_TX_LDO_PU 28 2380#define RES4334_HT_AVAIL 29 2381#define RES4334_MACPHY_CLK_AVAIL 30 2382 2383/* 4334 chip-specific ChipStatus register bits */ 2384#define CST4334_CHIPMODE_MASK 7 2385#define CST4334_SDIO_MODE 0x00000000 2386#define CST4334_SPI_MODE 0x00000004 2387#define CST4334_HSIC_MODE 0x00000006 2388#define CST4334_BLUSB_MODE 0x00000007 2389#define CST4334_CHIPMODE_HSIC(cs) (((cs) & CST4334_CHIPMODE_MASK) == CST4334_HSIC_MODE) 2390#define CST4334_OTP_PRESENT 0x00000010 2391#define CST4334_LPO_AUTODET_EN 0x00000020 2392#define CST4334_ARMREMAP_0 0x00000040 2393#define CST4334_SPROM_PRESENT 0x00000080 2394#define CST4334_ILPDIV_EN_MASK 0x00000100 2395#define CST4334_ILPDIV_EN_SHIFT 8 2396#define CST4334_LPO_SEL_MASK 0x00000200 2397#define CST4334_LPO_SEL_SHIFT 9 2398#define CST4334_RES_INIT_MODE_MASK 0x00000C00 2399#define CST4334_RES_INIT_MODE_SHIFT 10 2400 2401/* 4334 Chip specific PMU ChipControl register bits */ 2402#define PCTL_4334_GPIO3_ENAB (1 << 3) 2403 2404/* 4334 Chip control */ 2405#define CCTRL4334_PMU_WAKEUP_GPIO1 (1 << 0) 2406#define CCTRL4334_PMU_WAKEUP_HSIC (1 << 1) 2407#define CCTRL4334_PMU_WAKEUP_AOS (1 << 2) 2408#define CCTRL4334_HSIC_WAKE_MODE (1 << 3) 2409#define CCTRL4334_HSIC_INBAND_GPIO1 (1 << 4) 2410#define CCTRL4334_HSIC_LDO_PU (1 << 23) 2411 2412/* 4334 Chip control 3 */ 2413#define CCTRL4334_BLOCK_EXTRNL_WAKE (1 << 4) 2414#define CCTRL4334_SAVERESTORE_FIX (1 << 5) 2415 2416/* 43341 Chip control 3 */ 2417#define CCTRL43341_BLOCK_EXTRNL_WAKE (1 << 13) 2418#define CCTRL43341_SAVERESTORE_FIX (1 << 14) 2419#define CCTRL43341_BT_ISO_SEL (1 << 16) 2420 2421/* 4334 Chip specific ChipControl1 register bits */ 2422#define CCTRL1_4334_GPIO_SEL (1 << 0) /* 1=select GPIOs to be muxed out */ 2423#define CCTRL1_4334_ERCX_SEL (1 << 1) /* 1=select ERCX BT coex to be muxed out */ 2424#define CCTRL1_4334_SDIO_HOST_WAKE (1 << 2) /* SDIO: 1=configure GPIO0 for host wake */ 2425#define CCTRL1_4334_JTAG_DISABLE (1 << 3) /* 1=disable JTAG interface on mux'd pins */ 2426#define CCTRL1_4334_UART_ON_4_5 (1 << 28) /* 1=UART_TX/UART_RX muxed on GPIO_4/5 (4334B0/1) */ 2427 2428/* 4324 Chip specific ChipControl1 register bits */ 2429#define CCTRL1_4324_GPIO_SEL (1 << 0) /* 1=select GPIOs to be muxed out */ 2430#define CCTRL1_4324_SDIO_HOST_WAKE (1 << 2) /* SDIO: 1=configure GPIO0 for host wake */ 2431 2432/* 43143 chip-specific ChipStatus register bits based on Confluence documentation */ 2433/* register contains strap values sampled during POR */ 2434#define CST43143_REMAP_TO_ROM (3 << 0) /* 00=Boot SRAM, 01=Boot ROM, 10=Boot SFLASH */ 2435#define CST43143_SDIO_EN (1 << 2) /* 0 = USB Enab, SDIO pins are GPIO or I2S */ 2436#define CST43143_SDIO_ISO (1 << 3) /* 1 = SDIO isolated */ 2437#define CST43143_USB_CPU_LESS (1 << 4) /* 1 = CPULess mode Enabled */ 2438#define CST43143_CBUCK_MODE (3 << 6) /* Indicates what controller mode CBUCK is in */ 2439#define CST43143_POK_CBUCK (1 << 8) /* 1 = 1.2V CBUCK voltage ready */ 2440#define CST43143_PMU_OVRSPIKE (1 << 9) 2441#define CST43143_PMU_OVRTEMP (0xF << 10) 2442#define CST43143_SR_FLL_CAL_DONE (1 << 14) 2443#define CST43143_USB_PLL_LOCKDET (1 << 15) 2444#define CST43143_PMU_PLL_LOCKDET (1 << 16) 2445#define CST43143_CHIPMODE_SDIOD(cs) (((cs) & CST43143_SDIO_EN) != 0) /* SDIO */ 2446 2447/* 43143 Chip specific ChipControl register bits */ 2448/* 00: SECI is disabled (JATG functional), 01: 2 wire, 10: 4 wire */ 2449#define CCTRL_43143_SECI (1<<0) 2450#define CCTRL_43143_BT_LEGACY (1<<1) 2451#define CCTRL_43143_I2S_MODE (1<<2) /* 0: SDIO enabled */ 2452#define CCTRL_43143_I2S_MASTER (1<<3) /* 0: I2S MCLK input disabled */ 2453#define CCTRL_43143_I2S_FULL (1<<4) /* 0: I2S SDIN and SPDIF_TX inputs disabled */ 2454#define CCTRL_43143_GSIO (1<<5) /* 0: sFlash enabled */ 2455#define CCTRL_43143_RF_SWCTRL_MASK (7<<6) /* 0: disabled */ 2456#define CCTRL_43143_RF_SWCTRL_0 (1<<6) 2457#define CCTRL_43143_RF_SWCTRL_1 (2<<6) 2458#define CCTRL_43143_RF_SWCTRL_2 (4<<6) 2459#define CCTRL_43143_RF_XSWCTRL (1<<9) /* 0: UART enabled */ 2460#define CCTRL_43143_HOST_WAKE0 (1<<11) /* 1: SDIO separate interrupt output from GPIO4 */ 2461#define CCTRL_43143_HOST_WAKE1 (1<<12) /* 1: SDIO separate interrupt output from GPIO16 */ 2462 2463/* 43143 resources, based on pmu_params.xls V1.19 */ 2464#define RES43143_EXT_SWITCHER_PWM 0 /* 0x00001 */ 2465#define RES43143_XTAL_PU 1 /* 0x00002 */ 2466#define RES43143_ILP_REQUEST 2 /* 0x00004 */ 2467#define RES43143_ALP_AVAIL 3 /* 0x00008 */ 2468#define RES43143_WL_CORE_READY 4 /* 0x00010 */ 2469#define RES43143_BBPLL_PWRSW_PU 5 /* 0x00020 */ 2470#define RES43143_HT_AVAIL 6 /* 0x00040 */ 2471#define RES43143_RADIO_PU 7 /* 0x00080 */ 2472#define RES43143_MACPHY_CLK_AVAIL 8 /* 0x00100 */ 2473#define RES43143_OTP_PU 9 /* 0x00200 */ 2474#define RES43143_LQ_AVAIL 10 /* 0x00400 */ 2475 2476#define PMU43143_XTAL_CORE_SIZE_MASK 0x3F 2477 2478/* 4313 resources */ 2479#define RES4313_BB_PU_RSRC 0 2480#define RES4313_ILP_REQ_RSRC 1 2481#define RES4313_XTAL_PU_RSRC 2 2482#define RES4313_ALP_AVAIL_RSRC 3 2483#define RES4313_RADIO_PU_RSRC 4 2484#define RES4313_BG_PU_RSRC 5 2485#define RES4313_VREG1P4_PU_RSRC 6 2486#define RES4313_AFE_PWRSW_RSRC 7 2487#define RES4313_RX_PWRSW_RSRC 8 2488#define RES4313_TX_PWRSW_RSRC 9 2489#define RES4313_BB_PWRSW_RSRC 10 2490#define RES4313_SYNTH_PWRSW_RSRC 11 2491#define RES4313_MISC_PWRSW_RSRC 12 2492#define RES4313_BB_PLL_PWRSW_RSRC 13 2493#define RES4313_HT_AVAIL_RSRC 14 2494#define RES4313_MACPHY_CLK_AVAIL_RSRC 15 2495 2496/* 4313 chip-specific ChipStatus register bits */ 2497#define CST4313_SPROM_PRESENT 1 2498#define CST4313_OTP_PRESENT 2 2499#define CST4313_SPROM_OTP_SEL_MASK 0x00000002 2500#define CST4313_SPROM_OTP_SEL_SHIFT 0 2501 2502/* 4313 Chip specific ChipControl register bits */ 2503#define CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ 2504 2505/* PMU respources for 4314 */ 2506#define RES4314_LPLDO_PU 0 2507#define RES4314_PMU_SLEEP_DIS 1 2508#define RES4314_PMU_BG_PU 2 2509#define RES4314_CBUCK_LPOM_PU 3 2510#define RES4314_CBUCK_PFM_PU 4 2511#define RES4314_CLDO_PU 5 2512#define RES4314_LPLDO2_LVM 6 2513#define RES4314_WL_PMU_PU 7 2514#define RES4314_LNLDO_PU 8 2515#define RES4314_LDO3P3_PU 9 2516#define RES4314_OTP_PU 10 2517#define RES4314_XTAL_PU 11 2518#define RES4314_WL_PWRSW_PU 12 2519#define RES4314_LQ_AVAIL 13 2520#define RES4314_LOGIC_RET 14 2521#define RES4314_MEM_SLEEP 15 2522#define RES4314_MACPHY_RET 16 2523#define RES4314_WL_CORE_READY 17 2524#define RES4314_ILP_REQ 18 2525#define RES4314_ALP_AVAIL 19 2526#define RES4314_MISC_PWRSW_PU 20 2527#define RES4314_SYNTH_PWRSW_PU 21 2528#define RES4314_RX_PWRSW_PU 22 2529#define RES4314_RADIO_PU 23 2530#define RES4314_VCO_LDO_PU 24 2531#define RES4314_AFE_LDO_PU 25 2532#define RES4314_RX_LDO_PU 26 2533#define RES4314_TX_LDO_PU 27 2534#define RES4314_HT_AVAIL 28 2535#define RES4314_MACPHY_CLK_AVAIL 29 2536 2537/* 4314 chip-specific ChipStatus register bits */ 2538#define CST4314_OTP_ENABLED 0x00200000 2539 2540/* 43228 resources */ 2541#define RES43228_NOT_USED 0 2542#define RES43228_ILP_REQUEST 1 2543#define RES43228_XTAL_PU 2 2544#define RES43228_ALP_AVAIL 3 2545#define RES43228_PLL_EN 4 2546#define RES43228_HT_PHY_AVAIL 5 2547 2548/* 43228 chipstatus reg bits */ 2549#define CST43228_ILP_DIV_EN 0x1 2550#define CST43228_OTP_PRESENT 0x2 2551#define CST43228_SERDES_REFCLK_PADSEL 0x4 2552#define CST43228_SDIO_MODE 0x8 2553#define CST43228_SDIO_OTP_PRESENT 0x10 2554#define CST43228_SDIO_RESET 0x20 2555 2556/* 4706 chipstatus reg bits */ 2557#define CST4706_PKG_OPTION (1<<0) /* 0: full-featured package 1: low-cost package */ 2558#define CST4706_SFLASH_PRESENT (1<<1) /* 0: parallel, 1: serial flash is present */ 2559#define CST4706_SFLASH_TYPE (1<<2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */ 2560#define CST4706_MIPS_BENDIAN (1<<3) /* 0: little, 1: big endian */ 2561#define CST4706_PCIE1_DISABLE (1<<5) /* PCIE1 enable strap pin */ 2562 2563/* 4706 flashstrconfig reg bits */ 2564#define FLSTRCF4706_MASK 0x000000ff 2565#define FLSTRCF4706_SF1 0x00000001 /* 2nd serial flash present */ 2566#define FLSTRCF4706_PF1 0x00000002 /* 2nd parallel flash present */ 2567#define FLSTRCF4706_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */ 2568#define FLSTRCF4706_NF1 0x00000008 /* 2nd NAND flash present */ 2569#define FLSTRCF4706_1ST_MADDR_SEG_MASK 0x000000f0 /* Valid value mask */ 2570#define FLSTRCF4706_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */ 2571#define FLSTRCF4706_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */ 2572#define FLSTRCF4706_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */ 2573#define FLSTRCF4706_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */ 2574#define FLSTRCF4706_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */ 2575#define FLSTRCF4706_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */ 2576#define FLSTRCF4706_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */ 2577 2578/* 4360 Chip specific ChipControl register bits */ 2579#define CCTRL4360_I2C_MODE (1 << 0) 2580#define CCTRL4360_UART_MODE (1 << 1) 2581#define CCTRL4360_SECI_MODE (1 << 2) 2582#define CCTRL4360_BTSWCTRL_MODE (1 << 3) 2583#define CCTRL4360_DISCRETE_FEMCTRL_MODE (1 << 4) 2584#define CCTRL4360_DIGITAL_PACTRL_MODE (1 << 5) 2585#define CCTRL4360_BTSWCTRL_AND_DIGPA_PRESENT (1 << 6) 2586#define CCTRL4360_EXTRA_GPIO_MODE (1 << 7) 2587#define CCTRL4360_EXTRA_FEMCTRL_MODE (1 << 8) 2588#define CCTRL4360_BT_LGCY_MODE (1 << 9) 2589#define CCTRL4360_CORE2FEMCTRL4_ON (1 << 21) 2590#define CCTRL4360_SECI_ON_GPIO01 (1 << 24) 2591 2592/* 4360 Chip specific Regulator Control register bits */ 2593#define RCTRL4360_RFLDO_PWR_DOWN (1 << 1) 2594 2595/* 4360 PMU resources and chip status bits */ 2596#define RES4360_REGULATOR 0 2597#define RES4360_ILP_AVAIL 1 2598#define RES4360_ILP_REQ 2 2599#define RES4360_XTAL_LDO_PU 3 2600#define RES4360_XTAL_PU 4 2601#define RES4360_ALP_AVAIL 5 2602#define RES4360_BBPLLPWRSW_PU 6 2603#define RES4360_HT_AVAIL 7 2604#define RES4360_OTP_PU 8 2605 2606#define CST4360_XTAL_40MZ 0x00000001 2607#define CST4360_SFLASH 0x00000002 2608#define CST4360_SPROM_PRESENT 0x00000004 2609#define CST4360_SFLASH_TYPE 0x00000004 2610#define CST4360_OTP_ENABLED 0x00000008 2611#define CST4360_REMAP_ROM 0x00000010 2612#define CST4360_RSRC_INIT_MODE_MASK 0x00000060 2613#define CST4360_RSRC_INIT_MODE_SHIFT 5 2614#define CST4360_ILP_DIVEN 0x00000080 2615#define CST4360_MODE_USB 0x00000100 2616#define CST4360_SPROM_SIZE_MASK 0x00000600 2617#define CST4360_SPROM_SIZE_SHIFT 9 2618#define CST4360_BBPLL_LOCK 0x00000800 2619#define CST4360_AVBBPLL_LOCK 0x00001000 2620#define CST4360_USBBBPLL_LOCK 0x00002000 2621#define CST4360_RSRC_INIT_MODE(cs) ((cs & CST4360_RSRC_INIT_MODE_MASK) >> \ 2622 CST4360_RSRC_INIT_MODE_SHIFT) 2623 2624#define CCTRL_4360_UART_SEL 0x2 2625#define CST4360_RSRC_INIT_MODE(cs) ((cs & CST4360_RSRC_INIT_MODE_MASK) >> \ 2626 CST4360_RSRC_INIT_MODE_SHIFT) 2627 2628 2629/* 43602 PMU resources based on pmu_params.xls version v0.95 */ 2630#define RES43602_LPLDO_PU 0 2631#define RES43602_REGULATOR 1 2632#define RES43602_PMU_SLEEP 2 2633#define RES43602_RSVD_3 3 2634#define RES43602_XTALLDO_PU 4 2635#define RES43602_SERDES_PU 5 2636#define RES43602_BBPLL_PWRSW_PU 6 2637#define RES43602_SR_CLK_START 7 2638#define RES43602_SR_PHY_PWRSW 8 2639#define RES43602_SR_SUBCORE_PWRSW 9 2640#define RES43602_XTAL_PU 10 2641#define RES43602_PERST_OVR 11 2642#define RES43602_SR_CLK_STABLE 12 2643#define RES43602_SR_SAVE_RESTORE 13 2644#define RES43602_SR_SLEEP 14 2645#define RES43602_LQ_START 15 2646#define RES43602_LQ_AVAIL 16 2647#define RES43602_WL_CORE_RDY 17 2648#define RES43602_ILP_REQ 18 2649#define RES43602_ALP_AVAIL 19 2650#define RES43602_RADIO_PU 20 2651#define RES43602_RFLDO_PU 21 2652#define RES43602_HT_START 22 2653#define RES43602_HT_AVAIL 23 2654#define RES43602_MACPHY_CLKAVAIL 24 2655#define RES43602_PARLDO_PU 25 2656#define RES43602_RSVD_26 26 2657 2658/* 43602 chip status bits */ 2659#define CST43602_SPROM_PRESENT (1<<1) 2660#define CST43602_SPROM_SIZE (1<<10) /* 0 = 16K, 1 = 4K */ 2661#define CST43602_BBPLL_LOCK (1<<11) 2662#define CST43602_RF_LDO_OUT_OK (1<<15) /* RF LDO output OK */ 2663 2664#define PMU43602_CC2_PCIE_CLKREQ_L_WAKE_EN (1<<1) /* creates gated_pcie_wake, pmu_wakeup logic */ 2665#define PMU43602_CC2_PCIE_PERST_L_WAKE_EN (1<<2) /* creates gated_pcie_wake, pmu_wakeup logic */ 2666#define PMU43602_CC2_ENABLE_L2REFCLKPAD_PWRDWN (1<<3) 2667#define PMU43602_CC2_PMU_WAKE_ALP_AVAIL_EN (1<<5) /* enable pmu_wakeup to request for ALP_AVAIL */ 2668#define PMU43602_CC2_PERST_L_EXTEND_EN (1<<9) /* extend perst_l until rsc PERST_OVR comes up */ 2669#define PMU43602_CC2_FORCE_EXT_LPO (1<<19) /* 1=ext LPO clock is the final LPO clock */ 2670#define PMU43602_CC2_XTAL32_SEL (1<<30) /* 0=ext_clock, 1=xtal */ 2671 2672#define CC_SR1_43602_SR_ASM_ADDR (0x0) 2673 2674/* PLL CTL register values for open loop, used during S/R operation */ 2675#define PMU43602_PLL_CTL6_VAL 0x68000528 2676#define PMU43602_PLL_CTL7_VAL 0x6 2677 2678#define PMU43602_CC3_ARMCR4_DBG_CLK (1 << 29) 2679 2680 2681 2682/* defines to detect active host interface in use */ 2683#define CHIP_HOSTIF_PCIEMODE 0x1 2684#define CHIP_HOSTIF_USBMODE 0x2 2685#define CHIP_HOSTIF_SDIOMODE 0x4 2686#define CHIP_HOSTIF_PCIE(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_PCIEMODE) 2687#define CHIP_HOSTIF_USB(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_USBMODE) 2688#define CHIP_HOSTIF_SDIO(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_SDIOMODE) 2689 2690/* 4335 resources */ 2691#define RES4335_LPLDO_PO 0 2692#define RES4335_PMU_BG_PU 1 2693#define RES4335_PMU_SLEEP 2 2694#define RES4335_RSVD_3 3 2695#define RES4335_CBUCK_LPOM_PU 4 2696#define RES4335_CBUCK_PFM_PU 5 2697#define RES4335_RSVD_6 6 2698#define RES4335_RSVD_7 7 2699#define RES4335_LNLDO_PU 8 2700#define RES4335_XTALLDO_PU 9 2701#define RES4335_LDO3P3_PU 10 2702#define RES4335_OTP_PU 11 2703#define RES4335_XTAL_PU 12 2704#define RES4335_SR_CLK_START 13 2705#define RES4335_LQ_AVAIL 14 2706#define RES4335_LQ_START 15 2707#define RES4335_RSVD_16 16 2708#define RES4335_WL_CORE_RDY 17 2709#define RES4335_ILP_REQ 18 2710#define RES4335_ALP_AVAIL 19 2711#define RES4335_MINI_PMU 20 2712#define RES4335_RADIO_PU 21 2713#define RES4335_SR_CLK_STABLE 22 2714#define RES4335_SR_SAVE_RESTORE 23 2715#define RES4335_SR_PHY_PWRSW 24 2716#define RES4335_SR_VDDM_PWRSW 25 2717#define RES4335_SR_SUBCORE_PWRSW 26 2718#define RES4335_SR_SLEEP 27 2719#define RES4335_HT_START 28 2720#define RES4335_HT_AVAIL 29 2721#define RES4335_MACPHY_CLKAVAIL 30 2722 2723/* 4335 Chip specific ChipStatus register bits */ 2724#define CST4335_SPROM_MASK 0x00000020 2725#define CST4335_SFLASH_MASK 0x00000040 2726#define CST4335_RES_INIT_MODE_SHIFT 7 2727#define CST4335_RES_INIT_MODE_MASK 0x00000180 2728#define CST4335_CHIPMODE_MASK 0xF 2729#define CST4335_CHIPMODE_SDIOD(cs) (((cs) & (1 << 0)) != 0) /* SDIO */ 2730#define CST4335_CHIPMODE_GSPI(cs) (((cs) & (1 << 1)) != 0) /* gSPI */ 2731#define CST4335_CHIPMODE_USB20D(cs) (((cs) & (1 << 2)) != 0) /* HSIC || USBDA */ 2732#define CST4335_CHIPMODE_PCIE(cs) (((cs) & (1 << 3)) != 0) /* PCIE */ 2733 2734/* 4335 Chip specific ChipControl1 register bits */ 2735#define CCTRL1_4335_GPIO_SEL (1 << 0) /* 1=select GPIOs to be muxed out */ 2736#define CCTRL1_4335_SDIO_HOST_WAKE (1 << 2) /* SDIO: 1=configure GPIO0 for host wake */ 2737 2738#define CCTRL2_4335_AOSBLOCK (1 << 30) 2739#define CCTRL2_4335_PMUWAKE (1 << 31) 2740 2741#define PATCHTBL_SIZE (0x800) 2742#define CR4_4335_RAM_BASE (0x180000) 2743#define CR4_4345_RAM_BASE (0x1b0000) 2744#define CR4_4349_RAM_BASE (0x180000) 2745#define CR4_4350_RAM_BASE (0x180000) 2746#define CR4_4360_RAM_BASE (0x0) 2747#define CR4_43602_RAM_BASE (0x180000) 2748 2749/* 4335 chip OTP present & OTP select bits. */ 2750#define SPROM4335_OTP_SELECT 0x00000010 2751#define SPROM4335_OTP_PRESENT 0x00000020 2752 2753/* 4335 GCI specific bits. */ 2754#define CC4335_GCI_STRAP_OVERRIDE_SFLASH_PRESENT (1 << 24) 2755#define CC4335_GCI_STRAP_OVERRIDE_SFLASH_TYPE 25 2756#define CC4335_GCI_FUNC_SEL_PAD_SDIO 0x00707770 2757 2758/* SFLASH clkdev specific bits. */ 2759#define CC4335_SFLASH_CLKDIV_MASK 0x1F000000 2760#define CC4335_SFLASH_CLKDIV_SHIFT 25 2761 2762/* 4335 OTP bits for SFLASH. */ 2763#define CC4335_SROM_OTP_SFLASH 40 2764#define CC4335_SROM_OTP_SFLASH_PRESENT 0x1 2765#define CC4335_SROM_OTP_SFLASH_TYPE 0x2 2766#define CC4335_SROM_OTP_SFLASH_CLKDIV_MASK 0x003C 2767#define CC4335_SROM_OTP_SFLASH_CLKDIV_SHIFT 2 2768 2769 2770/* 4335 chip OTP present & OTP select bits. */ 2771#define SPROM4335_OTP_SELECT 0x00000010 2772#define SPROM4335_OTP_PRESENT 0x00000020 2773 2774/* 4335 GCI specific bits. */ 2775#define CC4335_GCI_STRAP_OVERRIDE_SFLASH_PRESENT (1 << 24) 2776#define CC4335_GCI_STRAP_OVERRIDE_SFLASH_TYPE 25 2777#define CC4335_GCI_FUNC_SEL_PAD_SDIO 0x00707770 2778 2779/* SFLASH clkdev specific bits. */ 2780#define CC4335_SFLASH_CLKDIV_MASK 0x1F000000 2781#define CC4335_SFLASH_CLKDIV_SHIFT 25 2782 2783/* 4335 OTP bits for SFLASH. */ 2784#define CC4335_SROM_OTP_SFLASH 40 2785#define CC4335_SROM_OTP_SFLASH_PRESENT 0x1 2786#define CC4335_SROM_OTP_SFLASH_TYPE 0x2 2787#define CC4335_SROM_OTP_SFLASH_CLKDIV_MASK 0x003C 2788#define CC4335_SROM_OTP_SFLASH_CLKDIV_SHIFT 2 2789 2790/* 4335 resources--END */ 2791 2792/* 4345 Chip specific ChipStatus register bits */ 2793#define CST4345_SPROM_MASK 0x00000020 2794#define CST4345_SFLASH_MASK 0x00000040 2795#define CST4345_RES_INIT_MODE_SHIFT 7 2796#define CST4345_RES_INIT_MODE_MASK 0x00000180 2797#define CST4345_CHIPMODE_MASK 0x4000F 2798#define CST4345_CHIPMODE_SDIOD(cs) (((cs) & (1 << 0)) != 0) /* SDIO */ 2799#define CST4345_CHIPMODE_GSPI(cs) (((cs) & (1 << 1)) != 0) /* gSPI */ 2800#define CST4345_CHIPMODE_HSIC(cs) (((cs) & (1 << 2)) != 0) /* HSIC */ 2801#define CST4345_CHIPMODE_PCIE(cs) (((cs) & (1 << 3)) != 0) /* PCIE */ 2802#define CST4345_CHIPMODE_USB20D(cs) (((cs) & (1 << 18)) != 0) /* USBDA */ 2803 2804/* 4350 Chipcommon ChipStatus bits */ 2805#define CST4350_SDIO_MODE 0x00000001 2806#define CST4350_HSIC20D_MODE 0x00000002 2807#define CST4350_BP_ON_HSIC_CLK 0x00000004 2808#define CST4350_PCIE_MODE 0x00000008 2809#define CST4350_USB20D_MODE 0x00000010 2810#define CST4350_USB30D_MODE 0x00000020 2811#define CST4350_SPROM_PRESENT 0x00000040 2812#define CST4350_RSRC_INIT_MODE_0 0x00000080 2813#define CST4350_RSRC_INIT_MODE_1 0x00000100 2814#define CST4350_SEL0_SDIO 0x00000200 2815#define CST4350_SEL1_SDIO 0x00000400 2816#define CST4350_SDIO_PAD_MODE 0x00000800 2817#define CST4350_BBPLL_LOCKED 0x00001000 2818#define CST4350_USBPLL_LOCKED 0x00002000 2819#define CST4350_LINE_STATE 0x0000C000 2820#define CST4350_SERDES_PIPE_PLLLOCK 0x00010000 2821#define CST4350_BT_READY 0x00020000 2822#define CST4350_SFLASH_PRESENT 0x00040000 2823#define CST4350_CPULESS_ENABLE 0x00080000 2824#define CST4350_STRAP_HOST_IFC_1 0x00100000 2825#define CST4350_STRAP_HOST_IFC_2 0x00200000 2826#define CST4350_STRAP_HOST_IFC_3 0x00400000 2827#define CST4350_RAW_SPROM_PRESENT 0x00800000 2828#define CST4350_APP_CLK_SWITCH_SEL_RDBACK 0x01000000 2829#define CST4350_RAW_RSRC_INIT_MODE_0 0x02000000 2830#define CST4350_SDIO_PAD_VDDIO 0x04000000 2831#define CST4350_GSPI_MODE 0x08000000 2832#define CST4350_PACKAGE_OPTION 0xF0000000 2833#define CST4350_PACKAGE_SHIFT 28 2834 2835/* package option for 4350 */ 2836#define CST4350_PACKAGE_WLCSP 0x0 2837#define CST4350_PACKAGE_PCIE 0x1 2838#define CST4350_PACKAGE_WLBGA 0x2 2839#define CST4350_PACKAGE_DBG 0x3 2840#define CST4350_PACKAGE_USB 0x4 2841#define CST4350_PACKAGE_USB_HSIC 0x4 2842 2843#define CST4350_PKG_MODE(cs) ((cs & CST4350_PACKAGE_OPTION) >> CST4350_PACKAGE_SHIFT) 2844 2845#define CST4350_PKG_WLCSP(cs) (CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_WLCSP)) 2846#define CST4350_PKG_PCIE(cs) (CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_PCIE)) 2847#define CST4350_PKG_WLBGA(cs) (CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_WLBGA)) 2848#define CST4350_PKG_USB(cs) (CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_USB)) 2849#define CST4350_PKG_USB_HSIC(cs) (CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_USB_HSIC)) 2850 2851/* 4350C0 USB PACKAGE using raw_sprom_present to indicate 40mHz xtal */ 2852#define CST4350_PKG_USB_40M(cs) (cs & CST4350_RAW_SPROM_PRESENT) 2853 2854#define CST4350_CHIPMODE_SDIOD(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_SDIOD)) 2855#define CST4350_CHIPMODE_USB20D(cs) ((CST4350_IFC_MODE(cs)) == (CST4350_IFC_MODE_USB20D)) 2856#define CST4350_CHIPMODE_HSIC20D(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_HSIC20D)) 2857#define CST4350_CHIPMODE_HSIC30D(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_HSIC30D)) 2858#define CST4350_CHIPMODE_USB30D(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_USB30D)) 2859#define CST4350_CHIPMODE_USB30D_WL(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_USB30D_WL)) 2860#define CST4350_CHIPMODE_PCIE(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_PCIE)) 2861 2862/* strap_host_ifc strap value */ 2863#define CST4350_HOST_IFC_MASK 0x00700000 2864#define CST4350_HOST_IFC_SHIFT 20 2865 2866/* host_ifc raw mode */ 2867#define CST4350_IFC_MODE_SDIOD 0x0 2868#define CST4350_IFC_MODE_HSIC20D 0x1 2869#define CST4350_IFC_MODE_HSIC30D 0x2 2870#define CST4350_IFC_MODE_PCIE 0x3 2871#define CST4350_IFC_MODE_USB20D 0x4 2872#define CST4350_IFC_MODE_USB30D 0x5 2873#define CST4350_IFC_MODE_USB30D_WL 0x6 2874#define CST4350_IFC_MODE_USB30D_BT 0x7 2875 2876#define CST4350_IFC_MODE(cs) ((cs & CST4350_HOST_IFC_MASK) >> CST4350_HOST_IFC_SHIFT) 2877 2878/* 4350 PMU resources */ 2879#define RES4350_LPLDO_PU 0 2880#define RES4350_PMU_BG_PU 1 2881#define RES4350_PMU_SLEEP 2 2882#define RES4350_RSVD_3 3 2883#define RES4350_CBUCK_LPOM_PU 4 2884#define RES4350_CBUCK_PFM_PU 5 2885#define RES4350_COLD_START_WAIT 6 2886#define RES4350_RSVD_7 7 2887#define RES4350_LNLDO_PU 8 2888#define RES4350_XTALLDO_PU 9 2889#define RES4350_LDO3P3_PU 10 2890#define RES4350_OTP_PU 11 2891#define RES4350_XTAL_PU 12 2892#define RES4350_SR_CLK_START 13 2893#define RES4350_LQ_AVAIL 14 2894#define RES4350_LQ_START 15 2895#define RES4350_PERST_OVR 16 2896#define RES4350_WL_CORE_RDY 17 2897#define RES4350_ILP_REQ 18 2898#define RES4350_ALP_AVAIL 19 2899#define RES4350_MINI_PMU 20 2900#define RES4350_RADIO_PU 21 2901#define RES4350_SR_CLK_STABLE 22 2902#define RES4350_SR_SAVE_RESTORE 23 2903#define RES4350_SR_PHY_PWRSW 24 2904#define RES4350_SR_VDDM_PWRSW 25 2905#define RES4350_SR_SUBCORE_PWRSW 26 2906#define RES4350_SR_SLEEP 27 2907#define RES4350_HT_START 28 2908#define RES4350_HT_AVAIL 29 2909#define RES4350_MACPHY_CLKAVAIL 30 2910 2911#define MUXENAB4350_UART_MASK (0x0000000f) 2912#define MUXENAB4350_UART_SHIFT 0 2913#define MUXENAB4350_HOSTWAKE_MASK (0x000000f0) /* configure GPIO for SDIO host_wake */ 2914#define MUXENAB4350_HOSTWAKE_SHIFT 4 2915 2916 2917/* 4350 GCI function sel values */ 2918#define CC4350_FNSEL_HWDEF (0) 2919#define CC4350_FNSEL_SAMEASPIN (1) 2920#define CC4350_FNSEL_UART (2) 2921#define CC4350_FNSEL_SFLASH (3) 2922#define CC4350_FNSEL_SPROM (4) 2923#define CC4350_FNSEL_I2C (5) 2924#define CC4350_FNSEL_MISC0 (6) 2925#define CC4350_FNSEL_GCI (7) 2926#define CC4350_FNSEL_MISC1 (8) 2927#define CC4350_FNSEL_MISC2 (9) 2928#define CC4350_FNSEL_PWDOG (10) 2929#define CC4350_FNSEL_IND (12) 2930#define CC4350_FNSEL_PDN (13) 2931#define CC4350_FNSEL_PUP (14) 2932#define CC4350_FNSEL_TRISTATE (15) 2933#define CC4350C_FNSEL_UART (3) 2934 2935 2936/* 4350 GPIO */ 2937#define CC4350_PIN_GPIO_00 (0) 2938#define CC4350_PIN_GPIO_01 (1) 2939#define CC4350_PIN_GPIO_02 (2) 2940#define CC4350_PIN_GPIO_03 (3) 2941#define CC4350_PIN_GPIO_04 (4) 2942#define CC4350_PIN_GPIO_05 (5) 2943#define CC4350_PIN_GPIO_06 (6) 2944#define CC4350_PIN_GPIO_07 (7) 2945#define CC4350_PIN_GPIO_08 (8) 2946#define CC4350_PIN_GPIO_09 (9) 2947#define CC4350_PIN_GPIO_10 (10) 2948#define CC4350_PIN_GPIO_11 (11) 2949#define CC4350_PIN_GPIO_12 (12) 2950#define CC4350_PIN_GPIO_13 (13) 2951#define CC4350_PIN_GPIO_14 (14) 2952#define CC4350_PIN_GPIO_15 (15) 2953 2954#define CC4350_RSVD_16_SHIFT 16 2955 2956#define CC2_4350_PHY_PWRSW_UPTIME_MASK (0xf << 0) 2957#define CC2_4350_PHY_PWRSW_UPTIME_SHIFT (0) 2958#define CC2_4350_VDDM_PWRSW_UPDELAY_MASK (0xf << 4) 2959#define CC2_4350_VDDM_PWRSW_UPDELAY_SHIFT (4) 2960#define CC2_4350_VDDM_PWRSW_UPTIME_MASK (0xf << 8) 2961#define CC2_4350_VDDM_PWRSW_UPTIME_SHIFT (8) 2962#define CC2_4350_SBC_PWRSW_DNDELAY_MASK (0x3 << 12) 2963#define CC2_4350_SBC_PWRSW_DNDELAY_SHIFT (12) 2964#define CC2_4350_PHY_PWRSW_DNDELAY_MASK (0x3 << 14) 2965#define CC2_4350_PHY_PWRSW_DNDELAY_SHIFT (14) 2966#define CC2_4350_VDDM_PWRSW_DNDELAY_MASK (0x3 << 16) 2967#define CC2_4350_VDDM_PWRSW_DNDELAY_SHIFT (16) 2968#define CC2_4350_VDDM_PWRSW_EN_MASK (1 << 20) 2969#define CC2_4350_VDDM_PWRSW_EN_SHIFT (20) 2970#define CC2_4350_MEMLPLDO_PWRSW_EN_MASK (1 << 21) 2971#define CC2_4350_MEMLPLDO_PWRSW_EN_SHIFT (21) 2972#define CC2_4350_SDIO_AOS_WAKEUP_MASK (1 << 24) 2973#define CC2_4350_SDIO_AOS_WAKEUP_SHIFT (24) 2974 2975/* Applies to 4335/4350/4345 */ 2976#define CC3_SR_CLK_SR_MEM_MASK (1 << 0) 2977#define CC3_SR_CLK_SR_MEM_SHIFT (0) 2978#define CC3_SR_BIT1_TBD_MASK (1 << 1) 2979#define CC3_SR_BIT1_TBD_SHIFT (1) 2980#define CC3_SR_ENGINE_ENABLE_MASK (1 << 2) 2981#define CC3_SR_ENGINE_ENABLE_SHIFT (2) 2982#define CC3_SR_BIT3_TBD_MASK (1 << 3) 2983#define CC3_SR_BIT3_TBD_SHIFT (3) 2984#define CC3_SR_MINDIV_FAST_CLK_MASK (0xF << 4) 2985#define CC3_SR_MINDIV_FAST_CLK_SHIFT (4) 2986#define CC3_SR_R23_SR2_RISE_EDGE_TRIG_MASK (1 << 8) 2987#define CC3_SR_R23_SR2_RISE_EDGE_TRIG_SHIFT (8) 2988#define CC3_SR_R23_SR2_FALL_EDGE_TRIG_MASK (1 << 9) 2989#define CC3_SR_R23_SR2_FALL_EDGE_TRIG_SHIFT (9) 2990#define CC3_SR_R23_SR_RISE_EDGE_TRIG_MASK (1 << 10) 2991#define CC3_SR_R23_SR_RISE_EDGE_TRIG_SHIFT (10) 2992#define CC3_SR_R23_SR_FALL_EDGE_TRIG_MASK (1 << 11) 2993#define CC3_SR_R23_SR_FALL_EDGE_TRIG_SHIFT (11) 2994#define CC3_SR_NUM_CLK_HIGH_MASK (0x7 << 12) 2995#define CC3_SR_NUM_CLK_HIGH_SHIFT (12) 2996#define CC3_SR_BIT15_TBD_MASK (1 << 15) 2997#define CC3_SR_BIT15_TBD_SHIFT (15) 2998#define CC3_SR_PHY_FUNC_PIC_MASK (1 << 16) 2999#define CC3_SR_PHY_FUNC_PIC_SHIFT (16) 3000#define CC3_SR_BIT17_19_TBD_MASK (0x7 << 17) 3001#define CC3_SR_BIT17_19_TBD_SHIFT (17) 3002#define CC3_SR_CHIP_TRIGGER_1_MASK (1 << 20) 3003#define CC3_SR_CHIP_TRIGGER_1_SHIFT (20) 3004#define CC3_SR_CHIP_TRIGGER_2_MASK (1 << 21) 3005#define CC3_SR_CHIP_TRIGGER_2_SHIFT (21) 3006#define CC3_SR_CHIP_TRIGGER_3_MASK (1 << 22) 3007#define CC3_SR_CHIP_TRIGGER_3_SHIFT (22) 3008#define CC3_SR_CHIP_TRIGGER_4_MASK (1 << 23) 3009#define CC3_SR_CHIP_TRIGGER_4_SHIFT (23) 3010#define CC3_SR_ALLOW_SBC_FUNC_PIC_MASK (1 << 24) 3011#define CC3_SR_ALLOW_SBC_FUNC_PIC_SHIFT (24) 3012#define CC3_SR_BIT25_26_TBD_MASK (0x3 << 25) 3013#define CC3_SR_BIT25_26_TBD_SHIFT (25) 3014#define CC3_SR_ALLOW_SBC_STBY_MASK (1 << 27) 3015#define CC3_SR_ALLOW_SBC_STBY_SHIFT (27) 3016#define CC3_SR_GPIO_MUX_MASK (0xF << 28) 3017#define CC3_SR_GPIO_MUX_SHIFT (28) 3018 3019/* Applies to 4335/4350/4345 */ 3020#define CC4_SR_INIT_ADDR_MASK (0x3FF0000) 3021#define CC4_4350_SR_ASM_ADDR (0x30) 3022#define CC4_4350_C0_SR_ASM_ADDR (0x0) 3023#define CC4_4335_SR_ASM_ADDR (0x48) 3024#define CC4_4345_SR_ASM_ADDR (0x48) 3025#define CC4_SR_INIT_ADDR_SHIFT (16) 3026 3027#define CC4_4350_EN_SR_CLK_ALP_MASK (1 << 30) 3028#define CC4_4350_EN_SR_CLK_ALP_SHIFT (30) 3029#define CC4_4350_EN_SR_CLK_HT_MASK (1 << 31) 3030#define CC4_4350_EN_SR_CLK_HT_SHIFT (31) 3031 3032#define VREG4_4350_MEMLPDO_PU_MASK (1 << 31) 3033#define VREG4_4350_MEMLPDO_PU_SHIFT 31 3034 3035#define VREG6_4350_SR_EXT_CLKDIR_MASK (1 << 20) 3036#define VREG6_4350_SR_EXT_CLKDIR_SHIFT 20 3037#define VREG6_4350_SR_EXT_CLKDIV_MASK (0x3 << 21) 3038#define VREG6_4350_SR_EXT_CLKDIV_SHIFT 21 3039#define VREG6_4350_SR_EXT_CLKEN_MASK (1 << 23) 3040#define VREG6_4350_SR_EXT_CLKEN_SHIFT 23 3041 3042#define CC5_4350_PMU_EN_ASSERT_MASK (1 << 13) 3043#define CC5_4350_PMU_EN_ASSERT_SHIFT (13) 3044 3045#define CC6_4350_PCIE_CLKREQ_WAKEUP_MASK (1 << 4) 3046#define CC6_4350_PCIE_CLKREQ_WAKEUP_SHIFT (4) 3047#define CC6_4350_PMU_WAKEUP_ALPAVAIL_MASK (1 << 6) 3048#define CC6_4350_PMU_WAKEUP_ALPAVAIL_SHIFT (6) 3049#define CC6_4350_PMU_EN_EXT_PERST_MASK (1 << 17) 3050#define CC6_4350_PMU_EN_EXT_PERST_SHIFT (17) 3051#define CC6_4350_PMU_EN_WAKEUP_MASK (1 << 18) 3052#define CC6_4350_PMU_EN_WAKEUP_SHIFT (18) 3053 3054#define CC7_4350_PMU_EN_ASSERT_L2_MASK (1 << 26) 3055#define CC7_4350_PMU_EN_ASSERT_L2_SHIFT (26) 3056#define CC7_4350_PMU_EN_MDIO_MASK (1 << 27) 3057#define CC7_4350_PMU_EN_MDIO_SHIFT (27) 3058 3059#define CC6_4345_PMU_EN_PERST_DEASSERT_MASK (1 << 13) 3060#define CC6_4345_PMU_EN_PERST_DEASSERT_SHIF (13) 3061#define CC6_4345_PMU_EN_L2_DEASSERT_MASK (1 << 14) 3062#define CC6_4345_PMU_EN_L2_DEASSERT_SHIF (14) 3063#define CC6_4345_PMU_EN_ASSERT_L2_MASK (1 << 15) 3064#define CC6_4345_PMU_EN_ASSERT_L2_SHIFT (15) 3065#define CC6_4345_PMU_EN_MDIO_MASK (1 << 24) 3066#define CC6_4345_PMU_EN_MDIO_SHIFT (24) 3067 3068/* GCI chipcontrol register indices */ 3069#define CC_GCI_CHIPCTRL_00 (0) 3070#define CC_GCI_CHIPCTRL_01 (1) 3071#define CC_GCI_CHIPCTRL_02 (2) 3072#define CC_GCI_CHIPCTRL_03 (3) 3073#define CC_GCI_CHIPCTRL_04 (4) 3074#define CC_GCI_CHIPCTRL_05 (5) 3075#define CC_GCI_CHIPCTRL_06 (6) 3076#define CC_GCI_CHIPCTRL_07 (7) 3077#define CC_GCI_CHIPCTRL_08 (8) 3078#define CC_GCI_XTAL_BUFSTRG_NFC (0xff << 12) 3079 3080#define CC_GCI_06_JTAG_SEL_SHIFT 4 3081#define CC_GCI_06_JTAG_SEL_MASK (1 << 4) 3082 3083#define CC_GCI_NUMCHIPCTRLREGS(cap1) ((cap1 & 0xF00) >> 8) 3084 3085/* 4345 PMU resources */ 3086#define RES4345_LPLDO_PU 0 3087#define RES4345_PMU_BG_PU 1 3088#define RES4345_PMU_SLEEP 2 3089#define RES4345_HSICLDO_PU 3 3090#define RES4345_CBUCK_LPOM_PU 4 3091#define RES4345_CBUCK_PFM_PU 5 3092#define RES4345_COLD_START_WAIT 6 3093#define RES4345_RSVD_7 7 3094#define RES4345_LNLDO_PU 8 3095#define RES4345_XTALLDO_PU 9 3096#define RES4345_LDO3P3_PU 10 3097#define RES4345_OTP_PU 11 3098#define RES4345_XTAL_PU 12 3099#define RES4345_SR_CLK_START 13 3100#define RES4345_LQ_AVAIL 14 3101#define RES4345_LQ_START 15 3102#define RES4345_PERST_OVR 16 3103#define RES4345_WL_CORE_RDY 17 3104#define RES4345_ILP_REQ 18 3105#define RES4345_ALP_AVAIL 19 3106#define RES4345_MINI_PMU 20 3107#define RES4345_RADIO_PU 21 3108#define RES4345_SR_CLK_STABLE 22 3109#define RES4345_SR_SAVE_RESTORE 23 3110#define RES4345_SR_PHY_PWRSW 24 3111#define RES4345_SR_VDDM_PWRSW 25 3112#define RES4345_SR_SUBCORE_PWRSW 26 3113#define RES4345_SR_SLEEP 27 3114#define RES4345_HT_START 28 3115#define RES4345_HT_AVAIL 29 3116#define RES4345_MACPHY_CLKAVAIL 30 3117 3118/* 4335 pins 3119* note: only the values set as default/used are added here. 3120*/ 3121#define CC4335_PIN_GPIO_00 (0) 3122#define CC4335_PIN_GPIO_01 (1) 3123#define CC4335_PIN_GPIO_02 (2) 3124#define CC4335_PIN_GPIO_03 (3) 3125#define CC4335_PIN_GPIO_04 (4) 3126#define CC4335_PIN_GPIO_05 (5) 3127#define CC4335_PIN_GPIO_06 (6) 3128#define CC4335_PIN_GPIO_07 (7) 3129#define CC4335_PIN_GPIO_08 (8) 3130#define CC4335_PIN_GPIO_09 (9) 3131#define CC4335_PIN_GPIO_10 (10) 3132#define CC4335_PIN_GPIO_11 (11) 3133#define CC4335_PIN_GPIO_12 (12) 3134#define CC4335_PIN_GPIO_13 (13) 3135#define CC4335_PIN_GPIO_14 (14) 3136#define CC4335_PIN_GPIO_15 (15) 3137#define CC4335_PIN_SDIO_CLK (16) 3138#define CC4335_PIN_SDIO_CMD (17) 3139#define CC4335_PIN_SDIO_DATA0 (18) 3140#define CC4335_PIN_SDIO_DATA1 (19) 3141#define CC4335_PIN_SDIO_DATA2 (20) 3142#define CC4335_PIN_SDIO_DATA3 (21) 3143#define CC4335_PIN_RF_SW_CTRL_0 (22) 3144#define CC4335_PIN_RF_SW_CTRL_1 (23) 3145#define CC4335_PIN_RF_SW_CTRL_2 (24) 3146#define CC4335_PIN_RF_SW_CTRL_3 (25) 3147#define CC4335_PIN_RF_SW_CTRL_4 (26) 3148#define CC4335_PIN_RF_SW_CTRL_5 (27) 3149#define CC4335_PIN_RF_SW_CTRL_6 (28) 3150#define CC4335_PIN_RF_SW_CTRL_7 (29) 3151#define CC4335_PIN_RF_SW_CTRL_8 (30) 3152#define CC4335_PIN_RF_SW_CTRL_9 (31) 3153/* Last GPIO Pad */ 3154#define CC4335_PIN_GPIO_LAST (31) 3155 3156/* 4335 GCI function sel values 3157*/ 3158#define CC4335_FNSEL_HWDEF (0) 3159#define CC4335_FNSEL_SAMEASPIN (1) 3160#define CC4335_FNSEL_GPIO0 (2) 3161#define CC4335_FNSEL_GPIO1 (3) 3162#define CC4335_FNSEL_GCI0 (4) 3163#define CC4335_FNSEL_GCI1 (5) 3164#define CC4335_FNSEL_UART (6) 3165#define CC4335_FNSEL_SFLASH (7) 3166#define CC4335_FNSEL_SPROM (8) 3167#define CC4335_FNSEL_MISC0 (9) 3168#define CC4335_FNSEL_MISC1 (10) 3169#define CC4335_FNSEL_MISC2 (11) 3170#define CC4335_FNSEL_IND (12) 3171#define CC4335_FNSEL_PDN (13) 3172#define CC4335_FNSEL_PUP (14) 3173#define CC4335_FNSEL_TRI (15) 3174 3175/* GCI Core Control Reg */ 3176#define GCI_CORECTRL_SR_MASK (1 << 0) /* SECI block Reset */ 3177#define GCI_CORECTRL_RSL_MASK (1 << 1) /* ResetSECILogic */ 3178#define GCI_CORECTRL_ES_MASK (1 << 2) /* EnableSECI */ 3179#define GCI_CORECTRL_FSL_MASK (1 << 3) /* Force SECI Out Low */ 3180#define GCI_CORECTRL_SOM_MASK (7 << 4) /* SECI Op Mode */ 3181#define GCI_CORECTRL_US_MASK (1 << 7) /* Update SECI */ 3182#define GCI_CORECTRL_BOS_MASK (1 << 8) /* Break On Sleep */ 3183 3184/* 4345 pins 3185* note: only the values set as default/used are added here. 3186*/ 3187#define CC4345_PIN_GPIO_00 (0) 3188#define CC4345_PIN_GPIO_01 (1) 3189#define CC4345_PIN_GPIO_02 (2) 3190#define CC4345_PIN_GPIO_03 (3) 3191#define CC4345_PIN_GPIO_04 (4) 3192#define CC4345_PIN_GPIO_05 (5) 3193#define CC4345_PIN_GPIO_06 (6) 3194#define CC4345_PIN_GPIO_07 (7) 3195#define CC4345_PIN_GPIO_08 (8) 3196#define CC4345_PIN_GPIO_09 (9) 3197#define CC4345_PIN_GPIO_10 (10) 3198#define CC4345_PIN_GPIO_11 (11) 3199#define CC4345_PIN_GPIO_12 (12) 3200#define CC4345_PIN_GPIO_13 (13) 3201#define CC4345_PIN_GPIO_14 (14) 3202#define CC4345_PIN_GPIO_15 (15) 3203#define CC4345_PIN_GPIO_16 (16) 3204#define CC4345_PIN_SDIO_CLK (17) 3205#define CC4345_PIN_SDIO_CMD (18) 3206#define CC4345_PIN_SDIO_DATA0 (19) 3207#define CC4345_PIN_SDIO_DATA1 (20) 3208#define CC4345_PIN_SDIO_DATA2 (21) 3209#define CC4345_PIN_SDIO_DATA3 (22) 3210#define CC4345_PIN_RF_SW_CTRL_0 (23) 3211#define CC4345_PIN_RF_SW_CTRL_1 (24) 3212#define CC4345_PIN_RF_SW_CTRL_2 (25) 3213#define CC4345_PIN_RF_SW_CTRL_3 (26) 3214#define CC4345_PIN_RF_SW_CTRL_4 (27) 3215#define CC4345_PIN_RF_SW_CTRL_5 (28) 3216#define CC4345_PIN_RF_SW_CTRL_6 (29) 3217#define CC4345_PIN_RF_SW_CTRL_7 (30) 3218#define CC4345_PIN_RF_SW_CTRL_8 (31) 3219#define CC4345_PIN_RF_SW_CTRL_9 (32) 3220 3221/* 4345 GCI function sel values 3222*/ 3223#define CC4345_FNSEL_HWDEF (0) 3224#define CC4345_FNSEL_SAMEASPIN (1) 3225#define CC4345_FNSEL_GPIO0 (2) 3226#define CC4345_FNSEL_GPIO1 (3) 3227#define CC4345_FNSEL_GCI0 (4) 3228#define CC4345_FNSEL_GCI1 (5) 3229#define CC4345_FNSEL_UART (6) 3230#define CC4345_FNSEL_SFLASH (7) 3231#define CC4345_FNSEL_SPROM (8) 3232#define CC4345_FNSEL_MISC0 (9) 3233#define CC4345_FNSEL_MISC1 (10) 3234#define CC4345_FNSEL_MISC2 (11) 3235#define CC4345_FNSEL_IND (12) 3236#define CC4345_FNSEL_PDN (13) 3237#define CC4345_FNSEL_PUP (14) 3238#define CC4345_FNSEL_TRI (15) 3239 3240#define MUXENAB4345_UART_MASK (0x0000000f) 3241#define MUXENAB4345_UART_SHIFT 0 3242#define MUXENAB4345_HOSTWAKE_MASK (0x000000f0) 3243#define MUXENAB4345_HOSTWAKE_SHIFT 4 3244 3245/* 4345 GCI AVS function sel values */ 3246#define CC4345_GCI_AVS_CTRL_MASK (0xfc) 3247#define CC4345_GCI_AVS_CTRL_SHIFT (2) 3248#define CC4345_GCI_AVS_CTRL_ENAB (1 << 5) 3249 3250/* GCI GPIO for function sel GCI-0/GCI-1 */ 3251#define CC_GCI_GPIO_0 (0) 3252#define CC_GCI_GPIO_1 (1) 3253#define CC_GCI_GPIO_2 (2) 3254#define CC_GCI_GPIO_3 (3) 3255#define CC_GCI_GPIO_4 (4) 3256#define CC_GCI_GPIO_5 (5) 3257#define CC_GCI_GPIO_6 (6) 3258#define CC_GCI_GPIO_7 (7) 3259#define CC_GCI_GPIO_8 (8) 3260#define CC_GCI_GPIO_9 (9) 3261#define CC_GCI_GPIO_10 (10) 3262#define CC_GCI_GPIO_11 (11) 3263#define CC_GCI_GPIO_12 (12) 3264#define CC_GCI_GPIO_13 (13) 3265#define CC_GCI_GPIO_14 (14) 3266#define CC_GCI_GPIO_15 (15) 3267 3268 3269/* indicates Invalid GPIO, e.g. when PAD GPIO doesn't map to GCI GPIO */ 3270#define CC_GCI_GPIO_INVALID 0xFF 3271 3272/* find the 4 bit mask given the bit position */ 3273#define GCIMASK(pos) (((uint32)0xF) << pos) 3274/* get the value which can be used to directly OR with chipcontrol reg */ 3275#define GCIPOSVAL(val, pos) ((((uint32)val) << pos) & GCIMASK(pos)) 3276/* Extract nibble from a given position */ 3277#define GCIGETNBL(val, pos) ((val >> pos) & 0xF) 3278 3279 3280/* find the 8 bit mask given the bit position */ 3281#define GCIMASK_8B(pos) (((uint32)0xFF) << pos) 3282/* get the value which can be used to directly OR with chipcontrol reg */ 3283#define GCIPOSVAL_8B(val, pos) ((((uint32)val) << pos) & GCIMASK_8B(pos)) 3284/* Extract nibble from a given position */ 3285#define GCIGETNBL_8B(val, pos) ((val >> pos) & 0xFF) 3286 3287/* find the 4 bit mask given the bit position */ 3288#define GCIMASK_4B(pos) (((uint32)0xF) << pos) 3289/* get the value which can be used to directly OR with chipcontrol reg */ 3290#define GCIPOSVAL_4B(val, pos) ((((uint32)val) << pos) & GCIMASK_4B(pos)) 3291/* Extract nibble from a given position */ 3292#define GCIGETNBL_4B(val, pos) ((val >> pos) & 0xF) 3293 3294 3295/* 4335 GCI Intstatus(Mask)/WakeMask Register bits. */ 3296#define GCI_INTSTATUS_RBI (1 << 0) /* Rx Break Interrupt */ 3297#define GCI_INTSTATUS_UB (1 << 1) /* UART Break Interrupt */ 3298#define GCI_INTSTATUS_SPE (1 << 2) /* SECI Parity Error Interrupt */ 3299#define GCI_INTSTATUS_SFE (1 << 3) /* SECI Framing Error Interrupt */ 3300#define GCI_INTSTATUS_SRITI (1 << 9) /* SECI Rx Idle Timer Interrupt */ 3301#define GCI_INTSTATUS_STFF (1 << 10) /* SECI Tx FIFO Full Interrupt */ 3302#define GCI_INTSTATUS_STFAE (1 << 11) /* SECI Tx FIFO Almost Empty Intr */ 3303#define GCI_INTSTATUS_SRFAF (1 << 12) /* SECI Rx FIFO Almost Full */ 3304#define GCI_INTSTATUS_SRFNE (1 << 14) /* SECI Rx FIFO Not Empty */ 3305#define GCI_INTSTATUS_SRFOF (1 << 15) /* SECI Rx FIFO Not Empty Timeout */ 3306#define GCI_INTSTATUS_GPIOINT (1 << 25) /* GCIGpioInt */ 3307#define GCI_INTSTATUS_GPIOWAKE (1 << 26) /* GCIGpioWake */ 3308 3309/* 4335 GCI IntMask Register bits. */ 3310#define GCI_INTMASK_RBI (1 << 0) /* Rx Break Interrupt */ 3311#define GCI_INTMASK_UB (1 << 1) /* UART Break Interrupt */ 3312#define GCI_INTMASK_SPE (1 << 2) /* SECI Parity Error Interrupt */ 3313#define GCI_INTMASK_SFE (1 << 3) /* SECI Framing Error Interrupt */ 3314#define GCI_INTMASK_SRITI (1 << 9) /* SECI Rx Idle Timer Interrupt */ 3315#define GCI_INTMASK_STFF (1 << 10) /* SECI Tx FIFO Full Interrupt */ 3316#define GCI_INTMASK_STFAE (1 << 11) /* SECI Tx FIFO Almost Empty Intr */ 3317#define GCI_INTMASK_SRFAF (1 << 12) /* SECI Rx FIFO Almost Full */ 3318#define GCI_INTMASK_SRFNE (1 << 14) /* SECI Rx FIFO Not Empty */ 3319#define GCI_INTMASK_SRFOF (1 << 15) /* SECI Rx FIFO Not Empty Timeout */ 3320#define GCI_INTMASK_GPIOINT (1 << 25) /* GCIGpioInt */ 3321#define GCI_INTMASK_GPIOWAKE (1 << 26) /* GCIGpioWake */ 3322 3323/* 4335 GCI WakeMask Register bits. */ 3324#define GCI_WAKEMASK_RBI (1 << 0) /* Rx Break Interrupt */ 3325#define GCI_WAKEMASK_UB (1 << 1) /* UART Break Interrupt */ 3326#define GCI_WAKEMASK_SPE (1 << 2) /* SECI Parity Error Interrupt */ 3327#define GCI_WAKEMASK_SFE (1 << 3) /* SECI Framing Error Interrupt */ 3328#define GCI_WAKE_SRITI (1 << 9) /* SECI Rx Idle Timer Interrupt */ 3329#define GCI_WAKEMASK_STFF (1 << 10) /* SECI Tx FIFO Full Interrupt */ 3330#define GCI_WAKEMASK_STFAE (1 << 11) /* SECI Tx FIFO Almost Empty Intr */ 3331#define GCI_WAKEMASK_SRFAF (1 << 12) /* SECI Rx FIFO Almost Full */ 3332#define GCI_WAKEMASK_SRFNE (1 << 14) /* SECI Rx FIFO Not Empty */ 3333#define GCI_WAKEMASK_SRFOF (1 << 15) /* SECI Rx FIFO Not Empty Timeout */ 3334#define GCI_WAKEMASK_GPIOINT (1 << 25) /* GCIGpioInt */ 3335#define GCI_WAKEMASK_GPIOWAKE (1 << 26) /* GCIGpioWake */ 3336 3337#define GCI_WAKE_ON_GCI_GPIO1 1 3338#define GCI_WAKE_ON_GCI_GPIO2 2 3339#define GCI_WAKE_ON_GCI_GPIO3 3 3340#define GCI_WAKE_ON_GCI_GPIO4 4 3341#define GCI_WAKE_ON_GCI_GPIO5 5 3342#define GCI_WAKE_ON_GCI_GPIO6 6 3343#define GCI_WAKE_ON_GCI_GPIO7 7 3344#define GCI_WAKE_ON_GCI_GPIO8 8 3345#define GCI_WAKE_ON_GCI_SECI_IN 9 3346 3347/* 4335 MUX options. each nibble belongs to a setting. Non-zero value specifies a logic 3348* for now only UART for bootloader. 3349*/ 3350#define MUXENAB4335_UART_MASK (0x0000000f) 3351 3352#define MUXENAB4335_UART_SHIFT 0 3353#define MUXENAB4335_HOSTWAKE_MASK (0x000000f0) /* configure GPIO for SDIO host_wake */ 3354#define MUXENAB4335_HOSTWAKE_SHIFT 4 3355#define MUXENAB4335_GETIX(val, name) \ 3356 ((((val) & MUXENAB4335_ ## name ## _MASK) >> MUXENAB4335_ ## name ## _SHIFT) - 1) 3357 3358/* 3359* Maximum delay for the PMU state transition in us. 3360* This is an upper bound intended for spinwaits etc. 3361*/ 3362#define PMU_MAX_TRANSITION_DLY 15000 3363 3364/* PMU resource up transition time in ILP cycles */ 3365#define PMURES_UP_TRANSITION 2 3366 3367/* 3368* Information from BT to WLAN over eci_inputlo, eci_inputmi & 3369* eci_inputhi register. Rev >=21 3370*/ 3371/* Fields in eci_inputlo register - [0:31] */ 3372#define ECI_INLO_TASKTYPE_MASK 0x0000000f /* [3:0] - 4 bits */ 3373#define ECI_INLO_TASKTYPE_SHIFT 0 3374#define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */ 3375#define ECI_INLO_PKTDUR_SHIFT 4 3376#define ECI_INLO_ROLE_MASK 0x00000100 /* [8] - 1 bits */ 3377#define ECI_INLO_ROLE_SHIFT 8 3378#define ECI_INLO_MLP_MASK 0x00000e00 /* [11:9] - 3 bits */ 3379#define ECI_INLO_MLP_SHIFT 9 3380#define ECI_INLO_TXPWR_MASK 0x000ff000 /* [19:12] - 8 bits */ 3381#define ECI_INLO_TXPWR_SHIFT 12 3382#define ECI_INLO_RSSI_MASK 0x0ff00000 /* [27:20] - 8 bits */ 3383#define ECI_INLO_RSSI_SHIFT 20 3384#define ECI_INLO_VAD_MASK 0x10000000 /* [28] - 1 bits */ 3385#define ECI_INLO_VAD_SHIFT 28 3386 3387/* 3388* Register eci_inputlo bitfield values. 3389* - BT packet type information bits [7:0] 3390*/ 3391/* [3:0] - Task (link) type */ 3392#define BT_ACL 0x00 3393#define BT_SCO 0x01 3394#define BT_eSCO 0x02 3395#define BT_A2DP 0x03 3396#define BT_SNIFF 0x04 3397#define BT_PAGE_SCAN 0x05 3398#define BT_INQUIRY_SCAN 0x06 3399#define BT_PAGE 0x07 3400#define BT_INQUIRY 0x08 3401#define BT_MSS 0x09 3402#define BT_PARK 0x0a 3403#define BT_RSSISCAN 0x0b 3404#define BT_MD_ACL 0x0c 3405#define BT_MD_eSCO 0x0d 3406#define BT_SCAN_WITH_SCO_LINK 0x0e 3407#define BT_SCAN_WITHOUT_SCO_LINK 0x0f 3408/* [7:4] = packet duration code */ 3409/* [8] - Master / Slave */ 3410#define BT_MASTER 0 3411#define BT_SLAVE 1 3412/* [11:9] - multi-level priority */ 3413#define BT_LOWEST_PRIO 0x0 3414#define BT_HIGHEST_PRIO 0x3 3415/* [19:12] - BT transmit power */ 3416/* [27:20] - BT RSSI */ 3417/* [28] - VAD silence */ 3418/* [31:29] - Undefined */ 3419/* Register eci_inputmi values - [32:63] - none defined */ 3420/* [63:32] - Undefined */ 3421 3422/* Information from WLAN to BT over eci_output register. */ 3423/* Fields in eci_output register - [0:31] */ 3424#define ECI48_OUT_MASKMAGIC_HIWORD 0x55550000 3425#define ECI_OUT_CHANNEL_MASK(ccrev) ((ccrev) < 35 ? 0xf : (ECI48_OUT_MASKMAGIC_HIWORD | 0xf000)) 3426#define ECI_OUT_CHANNEL_SHIFT(ccrev) ((ccrev) < 35 ? 0 : 12) 3427#define ECI_OUT_BW_MASK(ccrev) ((ccrev) < 35 ? 0x70 : (ECI48_OUT_MASKMAGIC_HIWORD | 0xe00)) 3428#define ECI_OUT_BW_SHIFT(ccrev) ((ccrev) < 35 ? 4 : 9) 3429#define ECI_OUT_ANTENNA_MASK(ccrev) ((ccrev) < 35 ? 0x80 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x100)) 3430#define ECI_OUT_ANTENNA_SHIFT(ccrev) ((ccrev) < 35 ? 7 : 8) 3431#define ECI_OUT_SIMUL_TXRX_MASK(ccrev) \ 3432 ((ccrev) < 35 ? 0x10000 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x80)) 3433#define ECI_OUT_SIMUL_TXRX_SHIFT(ccrev) ((ccrev) < 35 ? 16 : 7) 3434#define ECI_OUT_FM_DISABLE_MASK(ccrev) \ 3435 ((ccrev) < 35 ? 0x40000 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x40)) 3436#define ECI_OUT_FM_DISABLE_SHIFT(ccrev) ((ccrev) < 35 ? 18 : 6) 3437 3438/* Indicate control of ECI bits between s/w and dot11mac. 3439 * 0 => FW control, 1=> MAC/ucode control 3440 3441 * Current assignment (ccrev >= 35): 3442 * 0 - TxConf (ucode) 3443 * 38 - FM disable (wl) 3444 * 39 - Allow sim rx (ucode) 3445 * 40 - Num antennas (wl) 3446 * 43:41 - WLAN channel exclusion BW (wl) 3447 * 47:44 - WLAN channel (wl) 3448 * 3449 * (ccrev < 35) 3450 * 15:0 - wl 3451 * 16 - 3452 * 18 - FM disable 3453 * 30 - wl interrupt 3454 * 31 - ucode interrupt 3455 * others - unassigned (presumed to be with dot11mac/ucode) 3456 */ 3457#define ECI_MACCTRL_BITS 0xbffb0000 3458#define ECI_MACCTRLLO_BITS 0x1 3459#define ECI_MACCTRLHI_BITS 0xFF 3460 3461/* SECI configuration */ 3462#define SECI_MODE_UART 0x0 3463#define SECI_MODE_SECI 0x1 3464#define SECI_MODE_LEGACY_3WIRE_BT 0x2 3465#define SECI_MODE_LEGACY_3WIRE_WLAN 0x3 3466#define SECI_MODE_HALF_SECI 0x4 3467 3468#define SECI_RESET (1 << 0) 3469#define SECI_RESET_BAR_UART (1 << 1) 3470#define SECI_ENAB_SECI_ECI (1 << 2) 3471#define SECI_ENAB_SECIOUT_DIS (1 << 3) 3472#define SECI_MODE_MASK 0x7 3473#define SECI_MODE_SHIFT 4 /* (bits 5, 6, 7) */ 3474#define SECI_UPD_SECI (1 << 7) 3475 3476#define SECI_SLIP_ESC_CHAR 0xDB 3477#define SECI_SIGNOFF_0 SECI_SLIP_ESC_CHAR 3478#define SECI_SIGNOFF_1 0 3479#define SECI_REFRESH_REQ 0xDA 3480 3481/* seci clk_ctl_st bits */ 3482#define CLKCTL_STS_SECI_CLK_REQ (1 << 8) 3483#define CLKCTL_STS_SECI_CLK_AVAIL (1 << 24) 3484 3485#define SECI_UART_MSR_CTS_STATE (1 << 0) 3486#define SECI_UART_MSR_RTS_STATE (1 << 1) 3487#define SECI_UART_SECI_IN_STATE (1 << 2) 3488#define SECI_UART_SECI_IN2_STATE (1 << 3) 3489 3490/* GCI RX FIFO Control Register */ 3491#define GCI_RXF_LVL_MASK (0xFF << 0) 3492#define GCI_RXF_TIMEOUT_MASK (0xFF << 8) 3493 3494/* GCI UART Registers' Bit definitions */ 3495/* Seci Fifo Level Register */ 3496#define SECI_TXF_LVL_MASK (0x3F << 8) 3497#define TXF_AE_LVL_DEFAULT 0x4 3498#define SECI_RXF_LVL_FC_MASK (0x3F << 16) 3499 3500/* SeciUARTFCR Bit definitions */ 3501#define SECI_UART_FCR_RFR (1 << 0) 3502#define SECI_UART_FCR_TFR (1 << 1) 3503#define SECI_UART_FCR_SR (1 << 2) 3504#define SECI_UART_FCR_THP (1 << 3) 3505#define SECI_UART_FCR_AB (1 << 4) 3506#define SECI_UART_FCR_ATOE (1 << 5) 3507#define SECI_UART_FCR_ARTSOE (1 << 6) 3508#define SECI_UART_FCR_ABV (1 << 7) 3509#define SECI_UART_FCR_ALM (1 << 8) 3510 3511/* SECI UART LCR register bits */ 3512#define SECI_UART_LCR_STOP_BITS (1 << 0) /* 0 - 1bit, 1 - 2bits */ 3513#define SECI_UART_LCR_PARITY_EN (1 << 1) 3514#define SECI_UART_LCR_PARITY (1 << 2) /* 0 - odd, 1 - even */ 3515#define SECI_UART_LCR_RX_EN (1 << 3) 3516#define SECI_UART_LCR_LBRK_CTRL (1 << 4) /* 1 => SECI_OUT held low */ 3517#define SECI_UART_LCR_TXO_EN (1 << 5) 3518#define SECI_UART_LCR_RTSO_EN (1 << 6) 3519#define SECI_UART_LCR_SLIPMODE_EN (1 << 7) 3520#define SECI_UART_LCR_RXCRC_CHK (1 << 8) 3521#define SECI_UART_LCR_TXCRC_INV (1 << 9) 3522#define SECI_UART_LCR_TXCRC_LSBF (1 << 10) 3523#define SECI_UART_LCR_TXCRC_EN (1 << 11) 3524#define SECI_UART_LCR_RXSYNC_EN (1 << 12) 3525 3526#define SECI_UART_MCR_TX_EN (1 << 0) 3527#define SECI_UART_MCR_PRTS (1 << 1) 3528#define SECI_UART_MCR_SWFLCTRL_EN (1 << 2) 3529#define SECI_UART_MCR_HIGHRATE_EN (1 << 3) 3530#define SECI_UART_MCR_LOOPBK_EN (1 << 4) 3531#define SECI_UART_MCR_AUTO_RTS (1 << 5) 3532#define SECI_UART_MCR_AUTO_TX_DIS (1 << 6) 3533#define SECI_UART_MCR_BAUD_ADJ_EN (1 << 7) 3534#define SECI_UART_MCR_XONOFF_RPT (1 << 9) 3535 3536/* SeciUARTLSR Bit Mask */ 3537#define SECI_UART_LSR_RXOVR_MASK (1 << 0) 3538#define SECI_UART_LSR_RFF_MASK (1 << 1) 3539#define SECI_UART_LSR_TFNE_MASK (1 << 2) 3540#define SECI_UART_LSR_TI_MASK (1 << 3) 3541#define SECI_UART_LSR_TPR_MASK (1 << 4) 3542#define SECI_UART_LSR_TXHALT_MASK (1 << 5) 3543 3544/* SeciUARTMSR Bit Mask */ 3545#define SECI_UART_MSR_CTSS_MASK (1 << 0) 3546#define SECI_UART_MSR_RTSS_MASK (1 << 1) 3547#define SECI_UART_MSR_SIS_MASK (1 << 2) 3548#define SECI_UART_MSR_SIS2_MASK (1 << 3) 3549 3550/* SeciUARTData Bits */ 3551#define SECI_UART_DATA_RF_NOT_EMPTY_BIT (1 << 12) 3552#define SECI_UART_DATA_RF_FULL_BIT (1 << 13) 3553#define SECI_UART_DATA_RF_OVRFLOW_BIT (1 << 14) 3554#define SECI_UART_DATA_FIFO_PTR_MASK 0xFF 3555#define SECI_UART_DATA_RF_RD_PTR_SHIFT 16 3556#define SECI_UART_DATA_RF_WR_PTR_SHIFT 24 3557 3558/* LTECX: ltecxmux mask */ 3559#define LTECX_MUX_MODE_SHIFT 0 3560#define LTECX_MUX_MODE_MASK ((0xF) << LTECX_MUX_MODE_SHIFT) 3561#define LTECX_MUX_GPIOCFG_SHIFT 4 3562#define LTECX_MUX_GPIOCFG_MASK ((0xF) << LTECX_MUX_GPIOCFG_SHIFT) 3563#define LTECX_MUX_FSYNC_SHIFT 8 3564#define LTECX_MUX_FSYNC_MASK ((0xF) << LTECX_MUX_FSYNC_SHIFT) 3565#define LTECX_MUX_LTERX_SHIFT 12 3566#define LTECX_MUX_LTERX_MASK ((0xF) << LTECX_MUX_LTERX_SHIFT) 3567#define LTECX_MUX_LTETX_SHIFT 16 3568#define LTECX_MUX_LTETX_MASK ((0xF) << LTECX_MUX_LTETX_SHIFT) 3569#define LTECX_MUX_WLPRIO_SHIFT 20 3570#define LTECX_MUX_WLPRIO_MASK ((0xF) << LTECX_MUX_WLPRIO_SHIFT) 3571/* LTECX: ltecxmux MODE */ 3572#define LTECX_MUX_MODE_WCI2 0x0 3573#define LTECX_MUX_MODE_GPIO 0x1 3574#define LTECX_MUX_MODE_NOLTECX 0xF 3575 3576/* LTECX: ltecxmux GPIO config */ 3577#define LTECX_MUX_CONFIG_GPIO2345 0x0 3578#define LTECX_MUX_CONFIG_GPIO89AB 0x1 3579#define LTECX_MUX_GPIOMASK_SHIFT 16 3580/* LTECX: ltecxmux SECI GPIO config */ 3581#define LTECX_MUX_WCI2_UARTI_SHIFT 4 3582#define LTECX_MUX_WCI2_UARTI_MASK ((0xF) << LTECX_MUX_WCI2_UARTI_SHIFT) 3583#define LTECX_MUX_WCI2_UARTO_SHIFT 8 3584#define LTECX_MUX_WCI2_UARTO_MASK ((0xF) << LTECX_MUX_WCI2_UARTO_SHIFT) 3585#define LTECX_MUX_WCI2_FNSELI_SHIFT 12 3586#define LTECX_MUX_WCI2_FNSELI_MASK ((0xF) << LTECX_MUX_WCI2_FNSELI_SHIFT) 3587#define LTECX_MUX_WCI2_FNSELO_SHIFT 16 3588#define LTECX_MUX_WCI2_FNSELO_MASK ((0xF) << LTECX_MUX_WCI2_FNSELO_SHIFT) 3589 3590/* WLAN channel numbers - used from wifi.h */ 3591 3592/* WLAN BW */ 3593#define ECI_BW_20 0x0 3594#define ECI_BW_25 0x1 3595#define ECI_BW_30 0x2 3596#define ECI_BW_35 0x3 3597#define ECI_BW_40 0x4 3598#define ECI_BW_45 0x5 3599#define ECI_BW_50 0x6 3600#define ECI_BW_ALL 0x7 3601 3602/* WLAN - number of antenna */ 3603#define WLAN_NUM_ANT1 TXANT_0 3604#define WLAN_NUM_ANT2 TXANT_1 3605 3606/* otpctrl1 0xF4 */ 3607#define OTPC_FORCE_PWR_OFF 0x02000000 3608 3609/* chipcommon s/r registers introduced with cc rev >= 48 */ 3610#define CC_SR_CTL0_ENABLE_MASK 0x1 3611#define CC_SR_CTL0_ENABLE_SHIFT 0 3612#define CC_SR_CTL0_EN_SR_ENG_CLK_SHIFT 1 /* sr_clk to sr_memory enable */ 3613#define CC_SR_CTL0_RSRC_TRIGGER_SHIFT 2 /* Rising edge resource trigger 0 to sr_engine */ 3614#define CC_SR_CTL0_MIN_DIV_SHIFT 6 /* Min division value for fast clk in sr_engine */ 3615#define CC_SR_CTL0_EN_SBC_STBY_SHIFT 16 /* Allow Subcore mem StandBy? */ 3616#define CC_SR_CTL0_EN_SR_ALP_CLK_MASK_SHIFT 18 3617#define CC_SR_CTL0_EN_SR_HT_CLK_SHIFT 19 3618#define CC_SR_CTL0_ALLOW_PIC_SHIFT 20 /* Allow pic to separate power domains */ 3619#define CC_SR_CTL0_MAX_SR_LQ_CLK_CNT_SHIFT 25 3620#define CC_SR_CTL0_EN_MEM_DISABLE_FOR_SLEEP 30 3621 3622#define CC_SR_CTL1_SR_INIT_MASK 0x3FF 3623#define CC_SR_CTL1_SR_INIT_SHIFT 0 3624 3625#define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */ 3626#define ECI_INLO_PKTDUR_SHIFT 4 3627 3628/* gci chip control bits */ 3629#define GCI_GPIO_CHIPCTRL_ENAB_IN_BIT 0 3630#define GCI_GPIO_CHIPCTRL_ENAB_OP_BIT 1 3631#define GCI_GPIO_CHIPCTRL_INVERT_BIT 2 3632#define GCI_GPIO_CHIPCTRL_PULLUP_BIT 3 3633#define GCI_GPIO_CHIPCTRL_PULLDN_BIT 4 3634#define GCI_GPIO_CHIPCTRL_ENAB_BTSIG_BIT 5 3635#define GCI_GPIO_CHIPCTRL_ENAB_OD_OP_BIT 6 3636#define GCI_GPIO_CHIPCTRL_ENAB_EXT_GPIO_BIT 7 3637 3638/* gci GPIO input status bits */ 3639#define GCI_GPIO_STS_VALUE_BIT 0 3640#define GCI_GPIO_STS_POS_EDGE_BIT 1 3641#define GCI_GPIO_STS_NEG_EDGE_BIT 2 3642#define GCI_GPIO_STS_FAST_EDGE_BIT 3 3643#define GCI_GPIO_STS_CLEAR 0xF 3644 3645#define GCI_GPIO_STS_VALUE (1 << GCI_GPIO_STS_VALUE_BIT) 3646 3647#endif /* _SBCHIPC_H */ 3648