1/* 2 * Broadcom HND chip & on-chip-interconnect-related definitions. 3 * 4 * Copyright (C) 2015, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id: hndsoc.h 458249 2014-02-26 06:31:34Z $ 19 */ 20 21#ifndef _HNDSOC_H 22#define _HNDSOC_H 23 24/* Include the soci specific files */ 25#include <sbconfig.h> 26#include <aidmp.h> 27 28/* 29 * SOC Interconnect Address Map. 30 * All regions may not exist on all chips. 31 */ 32#define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */ 33#define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */ 34#define SI_PCI_MEM_SZ (64 * 1024 * 1024) 35#define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */ 36#define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ 37#define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */ 38 39#ifdef SI_ENUM_BASE_VARIABLE 40#define SI_ENUM_BASE (sii->pub.si_enum_base) 41#else 42#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */ 43#endif /* SI_ENUM_BASE_VARIABLE */ 44 45#define SI_WRAP_BASE 0x18100000 /* Wrapper space base */ 46#define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ 47 48#define SI_MAXCORES 32 /* NorthStar has more cores */ 49 50#define SI_MAXBR 4 /* Max bridges (this is arbitrary, for software 51 * convenience and could be changed if we 52 * make any larger chips 53 */ 54 55#define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */ 56#define SI_FASTRAM_SWAPPED 0x19800000 57 58#define SI_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ 59#define SI_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ 60#define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */ 61#define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ 62#define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ 63#define SI_FLASH_WINDOW 0x01000000 /* Flash XIP Window */ 64 65#define SI_NS_NANDFLASH 0x1c000000 /* NorthStar NAND flash base */ 66#define SI_NS_NORFLASH 0x1e000000 /* NorthStar NOR flash base */ 67#define SI_NS_ROM 0xfffd0000 /* NorthStar ROM */ 68#define SI_NS_FLASH_WINDOW 0x02000000 /* Flash XIP Window */ 69 70#define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */ 71#define SI_ARMCR4_ROM 0x000f0000 /* ARM Cortex-R4 ROM */ 72#define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */ 73#define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */ 74#define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */ 75#define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */ 76 77#define SI_SFLASH 0x14000000 78#define SI_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */ 79#define SI_PCI_DMA2 0x80000000 /* Client Mode sb2pcitranslation2 (1 GB) */ 80#define SI_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */ 81#define SI_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 82 * (2 ZettaBytes), low 32 bits 83 */ 84#define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 85 * (2 ZettaBytes), high 32 bits 86 */ 87 88/* APB bridge code */ 89#define APB_BRIDGE_ID 0x135 /* APB Bridge 0, 1, etc. */ 90 91/* core codes */ 92#define NODEV_CORE_ID 0x700 /* Invalid coreid */ 93#define CC_CORE_ID 0x800 /* chipcommon core */ 94#define ILINE20_CORE_ID 0x801 /* iline20 core */ 95#define SRAM_CORE_ID 0x802 /* sram core */ 96#define SDRAM_CORE_ID 0x803 /* sdram core */ 97#define PCI_CORE_ID 0x804 /* pci core */ 98#define MIPS_CORE_ID 0x805 /* mips core */ 99#define ENET_CORE_ID 0x806 /* enet mac core */ 100#define CODEC_CORE_ID 0x807 /* v90 codec core */ 101#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */ 102#define ADSL_CORE_ID 0x809 /* ADSL core */ 103#define ILINE100_CORE_ID 0x80a /* iline100 core */ 104#define IPSEC_CORE_ID 0x80b /* ipsec core */ 105#define UTOPIA_CORE_ID 0x80c /* utopia core */ 106#define PCMCIA_CORE_ID 0x80d /* pcmcia core */ 107#define SOCRAM_CORE_ID 0x80e /* internal memory core */ 108#define MEMC_CORE_ID 0x80f /* memc sdram core */ 109#define OFDM_CORE_ID 0x810 /* OFDM phy core */ 110#define EXTIF_CORE_ID 0x811 /* external interface core */ 111#define D11_CORE_ID 0x812 /* 802.11 MAC core */ 112#define APHY_CORE_ID 0x813 /* 802.11a phy core */ 113#define BPHY_CORE_ID 0x814 /* 802.11b phy core */ 114#define GPHY_CORE_ID 0x815 /* 802.11g phy core */ 115#define MIPS33_CORE_ID 0x816 /* mips3302 core */ 116#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */ 117#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */ 118#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */ 119#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */ 120#define SDIOH_CORE_ID 0x81b /* sdio host core */ 121#define ROBO_CORE_ID 0x81c /* roboswitch core */ 122#define ATA100_CORE_ID 0x81d /* parallel ATA core */ 123#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */ 124#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */ 125#define PCIE_CORE_ID 0x820 /* pci express core */ 126#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */ 127#define SRAMC_CORE_ID 0x822 /* SRAM controller core */ 128#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */ 129#define ARM11_CORE_ID 0x824 /* ARM 1176 core */ 130#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */ 131#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */ 132#define PMU_CORE_ID 0x827 /* PMU core */ 133#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */ 134#define SDIOD_CORE_ID 0x829 /* SDIO device core */ 135#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */ 136#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */ 137#define MIPS74K_CORE_ID 0x82c /* mips 74k core */ 138#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */ 139#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */ 140#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */ 141#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */ 142#define SC_CORE_ID 0x831 /* shared common core */ 143#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */ 144#define SPIH_CORE_ID 0x833 /* SPI host core */ 145#define I2S_CORE_ID 0x834 /* I2S core */ 146#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */ 147#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */ 148 149#define ACPHY_CORE_ID 0x83b /* Dot11 ACPHY */ 150#define PCIE2_CORE_ID 0x83c /* pci express Gen2 core */ 151#define USB30D_CORE_ID 0x83d /* usb 3.0 device core */ 152#define ARMCR4_CORE_ID 0x83e /* ARM CR4 CPU */ 153#define M2MDMA_CORE_ID 0x844 /* memory to memory dma */ 154#define APB_BRIDGE_CORE_ID 0x135 /* APB bridge core ID */ 155#define AXI_CORE_ID 0x301 /* AXI/GPV core ID */ 156#define EROM_CORE_ID 0x366 /* EROM core ID */ 157#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */ 158#define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all 159 * unused address ranges 160 */ 161 162#define CC_4706_CORE_ID 0x500 /* chipcommon core */ 163#define NS_PCIEG2_CORE_ID 0x501 /* PCIE Gen 2 core */ 164#define NS_DMA_CORE_ID 0x502 /* DMA core */ 165#define NS_SDIO3_CORE_ID 0x503 /* SDIO3 core */ 166#define NS_USB20_CORE_ID 0x504 /* USB2.0 core */ 167#define NS_USB30_CORE_ID 0x505 /* USB3.0 core */ 168#define NS_A9JTAG_CORE_ID 0x506 /* ARM Cortex A9 JTAG core */ 169#define NS_DDR23_CORE_ID 0x507 /* Denali DDR2/DDR3 memory controller */ 170#define NS_ROM_CORE_ID 0x508 /* ROM core */ 171#define NS_NAND_CORE_ID 0x509 /* NAND flash controller core */ 172#define NS_QSPI_CORE_ID 0x50a /* SPI flash controller core */ 173#define NS_CCB_CORE_ID 0x50b /* ChipcommonB core */ 174#define SOCRAM_4706_CORE_ID 0x50e /* internal memory core */ 175#define NS_SOCRAM_CORE_ID SOCRAM_4706_CORE_ID 176#define ARMCA9_CORE_ID 0x510 /* ARM Cortex A9 core (ihost) */ 177#define NS_IHOST_CORE_ID ARMCA9_CORE_ID /* ARM Cortex A9 core (ihost) */ 178#define GMAC_COMMON_4706_CORE_ID 0x5dc /* Gigabit MAC core */ 179#define GMAC_4706_CORE_ID 0x52d /* Gigabit MAC core */ 180#define AMEMC_CORE_ID 0x52e /* DDR1/2 memory controller core */ 181#define ALTA_CORE_ID 0x534 /* I2S core */ 182#define DDR23_PHY_CORE_ID 0x5dd 183 184#define SI_PCI1_MEM 0x40000000 /* Host Mode sb2pcitranslation0 (64 MB) */ 185#define SI_PCI1_CFG 0x44000000 /* Host Mode sb2pcitranslation1 (64 MB) */ 186#define SI_PCIE1_DMA_H32 0xc0000000 /* PCIE Client Mode sb2pcitranslation2 187 * (2 ZettaBytes), high 32 bits 188 */ 189#define CC_4706B0_CORE_REV 0x8000001f /* chipcommon core */ 190#define SOCRAM_4706B0_CORE_REV 0x80000005 /* internal memory core */ 191#define GMAC_4706B0_CORE_REV 0x80000000 /* Gigabit MAC core */ 192#define NS_PCIEG2_CORE_REV_B0 0x7 /* NS-B0 PCIE Gen 2 core rev */ 193 194/* There are TWO constants on all HND chips: SI_ENUM_BASE above, 195 * and chipcommon being the first core: 196 */ 197#define SI_CC_IDX 0 198 199/* SOC Interconnect types (aka chip types) */ 200#define SOCI_SB 0 201#define SOCI_AI 1 202#define SOCI_UBUS 2 203#define SOCI_NAI 3 204 205/* Common core control flags */ 206#define SICF_BIST_EN 0x8000 207#define SICF_PME_EN 0x4000 208#define SICF_CORE_BITS 0x3ffc 209#define SICF_FGC 0x0002 210#define SICF_CLOCK_EN 0x0001 211 212/* Common core status flags */ 213#define SISF_BIST_DONE 0x8000 214#define SISF_BIST_ERROR 0x4000 215#define SISF_GATED_CLK 0x2000 216#define SISF_DMA64 0x1000 217#define SISF_CORE_BITS 0x0fff 218 219/* Norstar core status flags */ 220#define SISF_NS_BOOTDEV_MASK 0x0003 /* ROM core */ 221#define SISF_NS_BOOTDEV_NOR 0x0000 /* ROM core */ 222#define SISF_NS_BOOTDEV_NAND 0x0001 /* ROM core */ 223#define SISF_NS_BOOTDEV_ROM 0x0002 /* ROM core */ 224#define SISF_NS_BOOTDEV_OFFLOAD 0x0003 /* ROM core */ 225#define SISF_NS_SKUVEC_MASK 0x000c /* ROM core */ 226 227/* A register that is common to all cores to 228 * communicate w/PMU regarding clock control. 229 */ 230#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */ 231#define SI_PWR_CTL_ST 0x1e8 /* For memory clock gating */ 232 233/* clk_ctl_st register */ 234#define CCS_FORCEALP 0x00000001 /* force ALP request */ 235#define CCS_FORCEHT 0x00000002 /* force HT request */ 236#define CCS_FORCEILP 0x00000004 /* force ILP request */ 237#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */ 238#define CCS_HTAREQ 0x00000010 /* HT Avail Request */ 239#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */ 240#define CCS_HQCLKREQ 0x00000040 /* HQ Clock Required */ 241#define CCS_USBCLKREQ 0x00000100 /* USB Clock Req */ 242#define CCS_SECICLKREQ 0x00000100 /* SECI Clock Req */ 243#define CCS_ARMFASTCLOCKREQ 0x00000100 /* ARM CR4 fast clock request */ 244#define CCS_AVBCLKREQ 0x00000400 /* AVB Clock enable request */ 245#define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */ 246#define CCS_ERSRC_REQ_SHIFT 8 247#define CCS_ALPAVAIL 0x00010000 /* ALP is available */ 248#define CCS_HTAVAIL 0x00020000 /* HT is available */ 249#define CCS_BP_ON_APL 0x00040000 /* RO: Backplane is running on ALP clock */ 250#define CCS_BP_ON_HT 0x00080000 /* RO: Backplane is running on HT clock */ 251#define CCS_ARMFASTCLOCKSTATUS 0x01000000 /* Fast CPU clock is running */ 252#define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */ 253#define CCS_ERSRC_STS_SHIFT 24 254 255#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */ 256#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */ 257 258/* Not really related to SOC Interconnect, but a couple of software 259 * conventions for the use the flash space: 260 */ 261 262/* Minumum amount of flash we support */ 263#define FLASH_MIN 0x00020000 /* Minimum flash size */ 264 265/* A boot/binary may have an embedded block that describes its size */ 266#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */ 267#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */ 268#define BISZ_MAGIC_IDX 0 /* Word 0: magic */ 269#define BISZ_TXTST_IDX 1 /* 1: text start */ 270#define BISZ_TXTEND_IDX 2 /* 2: text end */ 271#define BISZ_DATAST_IDX 3 /* 3: data start */ 272#define BISZ_DATAEND_IDX 4 /* 4: data end */ 273#define BISZ_BSSST_IDX 5 /* 5: bss start */ 274#define BISZ_BSSEND_IDX 6 /* 6: bss end */ 275#define BISZ_SIZE 7 /* descriptor size in 32-bit integers */ 276 277/* Boot/Kernel related defintion and functions */ 278#define SOC_BOOTDEV_ROM 0x00000001 279#define SOC_BOOTDEV_PFLASH 0x00000002 280#define SOC_BOOTDEV_SFLASH 0x00000004 281#define SOC_BOOTDEV_NANDFLASH 0x00000008 282 283#define SOC_KNLDEV_NORFLASH 0x00000002 284#define SOC_KNLDEV_NANDFLASH 0x00000004 285 286#if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) 287int soc_boot_dev(void *sih); 288int soc_knl_dev(void *sih); 289#endif /* !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) */ 290 291#endif /* _HNDSOC_H */ 292