1/* 2 * Definitiosn for Jtag taps in HND chips. 3 * 4 * $Id: hndjtagdefs.h 400891 2013-05-07 23:25:36Z $ 5 * 6 * Copyright (C) 2015, Broadcom Corporation. All Rights Reserved. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 15 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 17 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 18 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#ifndef _HNDJTAGDEFS_H 22#define _HNDJTAGDEFS_H 23 24/* Jtag access regs are all 32 bits */ 25#define JRBITS 32 26 27/* MIPS mode defines: */ 28 29#define MIPS_IR_SIZE 5 30#define MIPS_DR_SIZE 32 31 32#define MIPS_IDCODE 1 33#define MIPS_BYPASS 0x1f 34 35/* Register addresses */ 36#define MIPS_ADDR 0x08 37#define MIPS_DATA 0x09 38#define MIPS_CTRL 0x0a 39 40/* Bits in the Control register */ 41#define DMA_SZ1 0x00000000 42#define DMA_SZ2 0x00000080 43#define DMA_SZ4 0x00000100 44#define DMA_SZ3 0x00000180 45#define DMA_READ 0x00000200 46#define DMA_ERROR 0x00000400 47#define DMA_START 0x00000800 48#define EJ_BREAK 0x00001000 49#define EJ_PREN 0x00008000 50#define DMA_ACC 0x00020000 51#define EJ_PRACC 0x00040000 52 53/* CC mode defines: */ 54 55#define CCJT_IR_SIZE 8 56#define CCJT_DR_SIZE 32 57 58#define CCJT_USER_BASE 0x20 59 60#define CCJT_IDCODE 1 61#define CCJT_BYPASS 0xff 62 63/* Register addresses */ 64#define CHIPC_ADDR 0x30 65#define CHIPC_DATA 0x32 66#define CHIPC_CTRL 0x34 67 68#define CHIPC_RO 1 /* Or in this to get the read-only address */ 69 70/* Control register bits */ 71#define CCC_BE0 0x00000001 72#define CCC_BE1 0x00000002 73#define CCC_BE2 0x00000004 74#define CCC_BE3 0x00000008 75#define CCC_SZ1 (CCC_BE0) 76#define CCC_SZ2 (CCC_BE1 | CCC_BE0) 77#define CCC_SZ4 (CCC_BE3 | CCC_BE2 | CCC_BE1 | CCC_BE0) 78#define CCC_READ 0x00000010 79#define CCC_START 0x00000020 80#define CCC_ERROR 0x00000040 81 82/* Bits written into the control register need to be shifted */ 83#define CCC_WR_SHIFT 25 84 85/* LV mode defines: */ 86 87#define LV_IR_SIZE 32 88#define LV_DR_SIZE 32 89 90#define LV_BASE 0xfe03ff3a 91#define LV_REG_MASK 0x01f00000 92#define LV_REG_SHIFT 20 93#define LV_RO 0x00080000 94#define LV_USER_BASE 0x10 95 96/* 38 bits IR, Reg address is in bits 31:27, WriteEnable is in bit 26 */ 97#define LV_38_BASE 0x03efff3a 98#define LV_38_REG_MASK 0xf8000000 99#define LV_38_REG_SHIFT 27 100#define LV_38_RO 0x04000000 101 102/* Keystone base */ 103#define LV_BASE_KY 0xfe07ff3a 104 105/* Register addresses */ 106#define LV_CAP 0 107#define LV_CHAIN_CTL 1 108#define LV_ADDR 2 109#define LV_ADDRH 3 110#define LV_DATA 4 111#define LV_CTRL 5 112#define LV_OTP_CTL 6 113#define LV_OTP_STAT 7 114#define LV_ATEWRITE 8 115#define LV_ATEREAD 9 116#define LV_ATEREADDATA 10 117#define LV_ATEWRITENEXT 11 118 119#define LV_REG_IR(reg) (LV_BASE | (((reg) << LV_REG_SHIFT) & LV_REG_MASK)) 120#define LV_REG_ROIR(reg) (LV_BASE | LV_RO | (((reg) << LV_REG_SHIFT) & LV_REG_MASK)) 121#define LV_UREG_IR(reg) (LV_BASE | ((((reg) + LV_USER_BASE) << LV_REG_SHIFT) & LV_REG_MASK)) 122#define LV_UREG_ROIR(reg) \ 123 (LV_BASE | LV_RO | ((((reg) + LV_USER_BASE) << LV_REG_SHIFT) & LV_REG_MASK)) 124 125#define LV_REG_IR_KY(reg) (LV_BASE_KY | (((reg) << LV_REG_SHIFT) & LV_REG_MASK)) 126 127#define LV_IDCODE 0xfffffffe 128#define LV_BYPASS 0xffffffff 129 130/* Northstar mode */ 131 132#define NS_BASE 0xe06ff33a 133#define NS_REG_MASK 0x1f000000 134#define NS_REG_SHIFT 24 135#define NS_RO 0x00800000 136 137/* Northstar-Lite */ 138#define NSL_BASE 0xe81bf33a 139#define NSL_REG_MASK 0x07C00000 140#define NSL_REG_SHIFT 22 141#define NSL_RO 0x00200000 142 143#define NS_REG_IR(reg) (NS_BASE | (((reg) << NS_REG_SHIFT) & NS_REG_MASK)) 144#define NS_DEVID 0x002BE17F 145#define NS_DEVID11 0x002BF17F 146#define NS_DEVID12 0x002C017F 147#define NS_DEVID13 0x0031E17F 148#define NS_DEVID47082 0x0032D17F 149 150#define IDC_MFG_MASK 0x00000fff 151#define IDC_PART_MASK 0x0ffff000 152#define IDC_PART_SHIFT 12 153#define IDC_REV_MASK 0xf0000000 154#define IDC_REV_SHIFT 28 155 156#define ATE_BUSY 1 157#define ATE_RERROR 2 158#define ATE_REJECT 0x10 159#define ATE_WERROR 0x20 160 161#define JEDEC_BRCM 0x17f 162 163#endif /* _HNDJTAGDEFS_H */ 164