1/* 2 * BCM5301X Denali DDR2/DDR3 memory controlers. 3 * 4 * Copyright (C) 2015, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id$ 19 */ 20 21#ifndef _DDRC_H 22#define _DDRC_H 23 24#ifndef PAD 25#define _PADLINE(line) pad ## line 26#define _XSTR(line) _PADLINE(line) 27#define PAD _XSTR(__LINE__) 28#endif /* PAD */ 29 30#ifdef _LANGUAGE_ASSEMBLY 31 32#define DDRC_CONTROL00 0x000 33#define DDRC_CONTROL01 0x004 34#define DDRC_CONTROL02 0x008 35#define DDRC_CONTROL03 0x00c 36#define DDRC_CONTROL04 0x010 37#define DDRC_CONTROL05 0x014 38#define DDRC_CONTROL06 0x018 39#define DDRC_CONTROL07 0x01c 40#define DDRC_CONTROL08 0x020 41#define DDRC_CONTROL09 0x024 42#define DDRC_CONTROL10 0x028 43#define DDRC_CONTROL11 0x02c 44#define DDRC_CONTROL12 0x030 45#define DDRC_CONTROL13 0x034 46#define DDRC_CONTROL14 0x038 47#define DDRC_CONTROL15 0x03c 48#define DDRC_CONTROL16 0x040 49#define DDRC_CONTROL17 0x044 50#define DDRC_CONTROL18 0x048 51#define DDRC_CONTROL19 0x04c 52#define DDRC_CONTROL20 0x050 53#define DDRC_CONTROL21 0x054 54#define DDRC_CONTROL22 0x058 55#define DDRC_CONTROL23 0x05c 56#define DDRC_CONTROL24 0x060 57#define DDRC_CONTROL25 0x064 58#define DDRC_CONTROL26 0x068 59#define DDRC_CONTROL27 0x06c 60#define DDRC_CONTROL28 0x070 61#define DDRC_CONTROL29 0x074 62#define DDRC_CONTROL30 0x078 63#define DDRC_CONTROL31 0x07c 64#define DDRC_CONTROL32 0x080 65#define DDRC_CONTROL33 0x084 66#define DDRC_CONTROL34 0x088 67#define DDRC_CONTROL35 0x08c 68#define DDRC_CONTROL36 0x090 69#define DDRC_CONTROL37 0x094 70#define DDRC_CONTROL38 0x098 71#define DDRC_CONTROL39 0x09c 72#define DDRC_CONTROL40 0x0a0 73#define DDRC_CONTROL41 0x0a4 74#define DDRC_CONTROL42 0x0a8 75#define DDRC_CONTROL43 0x0ac 76#define DDRC_CONTROL44 0x0b0 77#define DDRC_CONTROL45 0x0b4 78#define DDRC_CONTROL46 0x0b8 79#define DDRC_CONTROL47 0x0bc 80#define DDRC_CONTROL48 0x0c0 81#define DDRC_CONTROL49 0x0c4 82#define DDRC_CONTROL50 0x0c8 83#define DDRC_CONTROL51 0x0cc 84#define DDRC_CONTROL52 0x0d0 85#define DDRC_CONTROL53 0x0d4 86#define DDRC_CONTROL54 0x0d8 87#define DDRC_CONTROL55 0x0dc 88#define DDRC_CONTROL56 0x0e0 89#define DDRC_CONTROL57 0x0e4 90#define DDRC_CONTROL58 0x0e8 91#define DDRC_CONTROL59 0x0ec 92#define DDRC_CONTROL60 0x0f0 93#define DDRC_CONTROL61 0x0f4 94#define DDRC_CONTROL62 0x0f8 95#define DDRC_CONTROL63 0x0fc 96#define DDRC_CONTROL64 0x100 97#define DDRC_CONTROL65 0x104 98#define DDRC_CONTROL66 0x108 99#define DDRC_CONTROL67 0x10c 100#define DDRC_CONTROL68 0x110 101#define DDRC_CONTROL69 0x114 102#define DDRC_CONTROL70 0x118 103#define DDRC_CONTROL71 0x11c 104#define DDRC_CONTROL72 0x120 105#define DDRC_CONTROL73 0x124 106#define DDRC_CONTROL74 0x128 107#define DDRC_CONTROL75 0x12c 108#define DDRC_CONTROL76 0x130 109#define DDRC_CONTROL77 0x134 110#define DDRC_CONTROL78 0x138 111#define DDRC_CONTROL79 0x13c 112#define DDRC_CONTROL80 0x140 113#define DDRC_CONTROL81 0x144 114#define DDRC_CONTROL82 0x148 115#define DDRC_CONTROL83 0x14c 116#define DDRC_CONTROL84 0x150 117#define DDRC_CONTROL85 0x154 118#define DDRC_CONTROL86 0x158 119#define DDRC_CONTROL87 0x15c 120#define DDRC_CONTROL88 0x160 121#define DDRC_CONTROL89 0x164 122#define DDRC_CONTROL90 0x168 123#define DDRC_CONTROL91 0x16c 124#define DDRC_CONTROL92 0x170 125#define DDRC_CONTROL93 0x174 126#define DDRC_CONTROL94 0x178 127#define DDRC_CONTROL95 0x17c 128#define DDRC_CONTROL96 0x180 129#define DDRC_CONTROL97 0x184 130#define DDRC_CONTROL98 0x188 131#define DDRC_CONTROL99 0x18c 132#define DDRC_CONTROL100 0x190 133#define DDRC_CONTROL101 0x194 134#define DDRC_CONTROL102 0x198 135#define DDRC_CONTROL103 0x19c 136#define DDRC_CONTROL104 0x1a0 137#define DDRC_CONTROL105 0x1a4 138#define DDRC_CONTROL106 0x1a8 139#define DDRC_CONTROL107 0x1ac 140#define DDRC_CONTROL108 0x1b0 141#define DDRC_CONTROL109 0x1b4 142#define DDRC_CONTROL110 0x1b8 143#define DDRC_CONTROL111 0x1bc 144#define DDRC_CONTROL112 0x1c0 145#define DDRC_CONTROL113 0x1c4 146#define DDRC_CONTROL114 0x1c8 147#define DDRC_CONTROL115 0x1cc 148#define DDRC_CONTROL116 0x1d0 149#define DDRC_CONTROL117 0x1d4 150#define DDRC_CONTROL118 0x1d8 151#define DDRC_CONTROL119 0x1dc 152#define DDRC_CONTROL120 0x1e0 153#define DDRC_CONTROL121 0x1e4 154#define DDRC_CONTROL122 0x1e8 155#define DDRC_CONTROL123 0x1ec 156#define DDRC_CONTROL124 0x1f0 157#define DDRC_CONTROL125 0x1f4 158#define DDRC_CONTROL126 0x1f8 159#define DDRC_CONTROL127 0x1fc 160#define DDRC_CONTROL128 0x200 161#define DDRC_CONTROL129 0x204 162#define DDRC_CONTROL130 0x208 163#define DDRC_CONTROL131 0x20c 164#define DDRC_CONTROL132 0x210 165#define DDRC_CONTROL133 0x214 166#define DDRC_CONTROL134 0x218 167#define DDRC_CONTROL135 0x21c 168#define DDRC_CONTROL136 0x220 169#define DDRC_CONTROL137 0x224 170#define DDRC_CONTROL138 0x228 171#define DDRC_CONTROL139 0x22c 172#define DDRC_CONTROL140 0x230 173#define DDRC_CONTROL141 0x234 174#define DDRC_CONTROL142 0x238 175#define DDRC_CONTROL143 0x23c 176#define DDRC_CONTROL144 0x240 177#define DDRC_CONTROL145 0x244 178#define DDRC_CONTROL146 0x248 179#define DDRC_CONTROL147 0x24c 180#define DDRC_CONTROL148 0x250 181#define DDRC_CONTROL149 0x254 182#define DDRC_CONTROL150 0x258 183#define DDRC_CONTROL151 0x25c 184#define DDRC_CONTROL152 0x260 185#define DDRC_CONTROL153 0x264 186#define DDRC_CONTROL154 0x268 187#define DDRC_CONTROL155 0x26c 188#define DDRC_CONTROL156 0x270 189#define DDRC_CONTROL157 0x274 190#define DDRC_CONTROL158 0x278 191#define DDRC_CONTROL159 0x27c 192#define DDRC_CONTROL160 0x280 193#define DDRC_CONTROL161 0x284 194#define DDRC_CONTROL162 0x288 195#define DDRC_CONTROL163 0x28c 196#define DDRC_CONTROL164 0x290 197#define DDRC_CONTROL165 0x294 198#define DDRC_CONTROL166 0x298 199#define DDRC_CONTROL167 0x29c 200#define DDRC_CONTROL168 0x2a0 201#define DDRC_CONTROL169 0x2a4 202#define DDRC_CONTROL170 0x2a8 203#define DDRC_CONTROL171 0x2ac 204#define DDRC_CONTROL172 0x2b0 205#define DDRC_CONTROL173 0x2b4 206#define DDRC_CONTROL174 0x2b8 207#define DDRC_CONTROL175 0x2bc 208#define DDRC_CONTROL176 0x2c0 209#define DDRC_CONTROL177 0x2c4 210#define DDRC_CONTROL178 0x2c8 211#define DDRC_CONTROL179 0x2cc 212#define DDRC_CONTROL180 0x2d0 213#define DDRC_CONTROL181 0x2d4 214#define DDRC_CONTROL182 0x2d8 215#define DDRC_CONTROL183 0x2dc 216#define DDRC_CONTROL184 0x2e0 217#define DDRC_CONTROL185 0x2e4 218#define DDRC_CONTROL186 0x2e8 219#define DDRC_CONTROL187 0x2ec 220#define DDRC_CONTROL188 0x2f0 221#define DDRC_CONTROL189 0x2f4 222#define DDRC_CONTROL190 0x2f8 223#define DDRC_CONTROL191 0x2fc 224#define DDRC_CONTROL192 0x300 225#define DDRC_CONTROL193 0x304 226#define DDRC_CONTROL194 0x308 227#define DDRC_CONTROL195 0x30c 228#define DDRC_CONTROL196 0x310 229#define DDRC_CONTROL197 0x314 230#define DDRC_CONTROL198 0x318 231#define DDRC_CONTROL199 0x31c 232#define DDRC_CONTROL200 0x320 233#define DDRC_CONTROL201 0x324 234#define DDRC_CONTROL202 0x328 235#define DDRC_CONTROL203 0x32c 236#define DDRC_CONTROL204 0x330 237#define DDRC_CONTROL205 0x334 238#define DDRC_CONTROL206 0x338 239#define DDRC_CONTROL207 0x33c 240#define DDRC_CONTROL208 0x340 241 242#define DDRC_PHY_CONFIG 0x400 243#define DDRC_PCONTROL_REV 0x800 244#define DDRC_PCONTROL_PM_CONTROL 0x804 245#define DDRC_PCONTROL_PLL_STATUS 0x810 246#define DDRC_PCONTROL_PLL_CONFIG 0x814 247#define DDRC_PCONTROL_PLL_CONTROL 0x818 248#define DDRC_PCONTROL_PLL_DIVIDERS 0x81c 249#define DDRC_PCONTROL_AUX_CONTROL 0x820 250 251#define DDRC_PCONTROL_ZQ_PVT_COMPCTL 0x83c 252#define DDRC_PCONTROL_VDL_CALIBRATE 0x848 253#define DDRC_PHY_STRP_STAT 0x8b8 254#define DDRC_PHY_LN0_WR_PREMB_MODE 0xbac 255 256#else /* !_LANGUAGE_ASSEMBLY */ 257 258#define DDRC_MAXREG 209 259 260typedef struct ddrcregs { 261 uint32 control[DDRC_MAXREG]; /* 0x000 -- 0x340 */ 262 uint32 PAD[47]; 263 uint32 phy_config; /* 0x400 */ 264 uint32 PAD[255]; 265 uint32 phy_control_rev; /* 0x800 */ 266 uint32 phy_control_pmcontrol; /* 0x804 */ 267 uint32 PAD[2]; 268 uint32 phy_control_pllstatus; /* 0x810 */ 269 uint32 phy_control_pllconfig; /* 0x814 */ 270 uint32 phy_control_pllcontrol; /* 0x818 */ 271 uint32 phy_control_plldividers; /* 0x81c */ 272 uint32 phy_control_auxcontrol; /* 0x820 */ 273 uint32 PAD[4]; 274 uint32 phy_control_vdl_ovride_bitctl; /* 0x834 */ 275 uint32 PAD[1]; 276 uint32 phy_control_zq_pvt_compctl; /* 0x83c */ 277 uint32 PAD[2]; 278 uint32 phy_control_vdl_calibrate; /* 0x848 */ 279 uint32 phy_control_vdl_calibsts; /* 0x84c */ 280 uint32 PAD[26]; 281 uint32 phy_strp_stat; /* 0x8b8 */ 282 uint32 PAD[81]; 283 uint32 phy_ln0_vdl_ovride_byte_rd_en; /* 0xa00 */ 284 uint32 phy_ln0_vdl_ovride_byte0_w; /* 0xa04 */ 285 uint32 phy_ln0_vdl_ovride_byte0_r_p; /* 0xa08 */ 286 uint32 phy_ln0_vdl_ovride_byte0_r_n; /* 0xa0c */ 287 uint32 phy_ln0_vdl_ovride_byte0_bit0_w; /* 0xa10 */ 288 uint32 phy_ln0_vdl_ovride_byte0_bit1_w; /* 0xa14 */ 289 uint32 phy_ln0_vdl_ovride_byte0_bit2_w; /* 0xa18 */ 290 uint32 phy_ln0_vdl_ovride_byte0_bit3_w; /* 0xa1c */ 291 uint32 phy_ln0_vdl_ovride_byte0_bit4_w; /* 0xa20 */ 292 uint32 phy_ln0_vdl_ovride_byte0_bit5_w; /* 0xa24 */ 293 uint32 phy_ln0_vdl_ovride_byte0_bit6_w; /* 0xa28 */ 294 uint32 phy_ln0_vdl_ovride_byte0_bit7_w; /* 0xa2c */ 295 uint32 phy_ln0_vdl_ovride_byte0_dm_w; /* 0xa30 */ 296 uint32 PAD[16]; 297 uint32 phy_ln0_vdl_ovride_byte0_bit_rd_en; /* 0xa74 */ 298 uint32 PAD[11]; 299 uint32 phy_ln0_vdl_ovride_byte1_w; /* 0xaa4 */ 300 uint32 phy_ln0_vdl_ovride_byte1_r_p; /* 0xaa8 */ 301 uint32 phy_ln0_vdl_ovride_byte1_r_n; /* 0xaac */ 302 uint32 phy_ln0_vdl_ovride_byte1_bit0_w; /* 0xab0 */ 303 uint32 phy_ln0_vdl_ovride_byte1_bit1_w; /* 0xab4 */ 304 uint32 phy_ln0_vdl_ovride_byte1_bit2_w; /* 0xab8 */ 305 uint32 phy_ln0_vdl_ovride_byte1_bit3_w; /* 0xabc */ 306 uint32 phy_ln0_vdl_ovride_byte1_bit4_w; /* 0xac0 */ 307 uint32 phy_ln0_vdl_ovride_byte1_bit5_w; /* 0xac4 */ 308 uint32 phy_ln0_vdl_ovride_byte1_bit6_w; /* 0xac8 */ 309 uint32 phy_ln0_vdl_ovride_byte1_bit7_w; /* 0xacc */ 310 uint32 phy_ln0_vdl_ovride_byte1_dm_w; /* 0xad0 */ 311 uint32 PAD[16]; 312 uint32 phy_ln0_vdl_ovride_byte1_bit_rd_en; /* 0xb14 */ 313 uint32 PAD[18]; 314 uint32 phy_ln0_rddata_dly; /* 0xb60 */ 315 uint32 PAD[18]; 316 uint32 phy_ln0_wr_premb_mode; /* 0xbac */ 317} _ddrcregs_t; 318 319typedef volatile _ddrcregs_t ddrcregs_t; 320 321#endif /* _LANGUAGE_ASSEMBLY */ 322 323#define DDR_TABLE_END 0xffffffff 324 325#define DDRC00_START 0x00000001 326#define DDR_INT_INIT_DONE 0x200 327 328#define DDR_PHY_DMP_OFFSET 0x00001000 329 330#define DDR_TYPE_MASK (0x1 << 0) 331#define DDR_STAT_DDR3 0x00000001 /* bit 0 of iostatus */ 332 333#define DDR_PHY_CONTROL_REGS_REVISION 0x18010800 334#define DDR_S1_IDM_RESET_CONTROL 0x18108800 335#define DDR_S1_IDM_IO_CONTROL_DIRECT 0x18108408 336#define DDR_S2_IDM_RESET_CONTROL 0x18109800 337 338#endif /* _DDRC_H */ 339