1/* 2 * BCM947xx ChipcommonB Definitions. 3 * 4 * $Id$ 5 * 6 * Copyright (C) 2015, Broadcom Corporation. All Rights Reserved. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 15 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 17 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 18 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#ifndef _CHIPCOMMONB_H 22#define _CHIPCOMMONB_H 23 24#ifndef _LANGUAGE_ASSEMBLY 25 26/* cpp contortions to concatenate w/arg prescan */ 27#ifndef PAD 28#define _PADLINE(line) pad ## line 29#define _XSTR(line) _PADLINE(line) 30#define PAD _XSTR(__LINE__) 31#endif /* PAD */ 32 33typedef volatile struct { 34 uint32 PAD[1024]; /* 0x1000 */ 35 uint32 PAD[1024]; 36 uint32 PAD[1024]; 37 uint32 PAD[1024]; 38 uint32 PAD[1024]; 39 uint32 PAD[1024]; 40 uint32 PAD[1024]; /* 0x7000 */ 41 uint32 PAD[1024]; /* 0x8000 */ 42 uint32 PAD[1024]; 43 uint32 PAD[1024]; 44 uint32 cru_control; /* 0xb000 */ 45 uint32 PAD[1023]; 46 uint32 pcu_mdio_mgt; /* 0xc000 */ 47 uint32 pcu_mdio_cmd; /* 0xc004 */ 48 uint32 PAD[6]; 49 uint32 pcu_aopc_control; /* 0xc020 */ 50 uint32 pcu_status; /* 0xc024 */ 51 uint32 pcu_1v8_vregcntl; /* 0xc028 */ 52 uint32 pcu_1v8_1v5_vregcntl; /* 0xc02c */ 53 uint32 PAD[52]; 54 uint32 cru_lcpll_control0; /* 0xc100 */ 55 uint32 cru_lcpll_control1; 56 uint32 cru_lcpll_control2; 57 uint32 cru_lcpll_control3; 58 uint32 cru_lcpll_status; 59 uint32 PAD[11]; 60 uint32 cru_genpll_control0; /* 0xc140 */ 61 uint32 cru_genpll_control1; 62 uint32 cru_genpll_control2; 63 uint32 cru_genpll_control3; 64 uint32 cru_genpll_control4; 65 uint32 cru_genpll_control5; 66 uint32 cru_genpll_control6; 67 uint32 cru_genpll_control7; 68 uint32 cru_genpll_status; 69 uint32 PAD[7]; 70 uint32 cru_clkset_key; /* 0xc180 */ 71 uint32 cru_reset; 72 uint32 cru_period_sample; 73 uint32 cru_interrupt; 74 uint32 cru_mdio_control; /* 0xc190 */ 75 uint32 PAD[11]; 76 uint32 cru_gpio_control0; /* 0xc1c0 */ 77 uint32 cru_gpio_control1; 78 uint32 cru_gpio_control2; 79 uint32 cru_gpio_control3; 80 uint32 cru_gpio_control4; 81 uint32 cru_gpio_control5; 82 uint32 cru_gpio_control6; 83 uint32 cru_gpio_control7; 84 uint32 cru_gpio_control8; 85 86} chipcommonbregs_t; 87 88#endif /* _LANGUAGE_ASSEMBLY */ 89 90/* PCU_AOPC_CONTROL */ 91#define PCU_AOPC_PWRDIS_SEL (1 << 31) 92#define PCU_AOPC_PWRDIS_MASK (0xf << 1) 93#define PCU_AOPC_PWRDIS_WIFI (1 << 1) 94#define PCU_AOPC_PWRDIS_DDR (1 << 2) 95#define PCU_AOPC_PWRDIS_SDIO (1 << 3) 96#define PCU_AOPC_PWRDIS_RGMII (1 << 4) 97#define PCU_AOPC_PWRDIS_LATCHEN (1 << 0) 98 99/* PCU_STATUS */ 100#define PCU_PWR_EN_STRAPS_MASK (0xf << 0) 101#define PCU_PWR_EN_STRAPS_WIF1_EN (1 << 0) 102#define PCU_PWR_EN_STRAPS_DDR_EN (1 << 1) 103#define PCU_PWR_EN_STRAPS_SDIO_EN (1 << 2) 104#define PCU_PWR_EN_STRAPS_RGMII_EN (1 << 3) 105 106 107/* PCU_1V8_1V5_VREGCNTL */ 108#define PCU_VOLTAGE_SELECT_MASK (1 << 9) 109#define PCU_VOLTAGE_SELECT_1V8 (0 << 9) 110#define PCU_VOLTAGE_SELECT_1V5 (1 << 9) 111 112/* DMU tunings for DDR clocks */ 113#define CRU_CLKSET_KEY 0x1800c180 114#define LCPLL_NDIV_INT 0x1800c104 115#define LCPLL_CHX_MDIV 0x1800c108 116#define LCPLL_LOAD_EN_CH 0x1800c100 117 118/* SRAB registers */ 119#define CHIPCB_SRAB_BASE 0x18007000 120#define CHIPCB_SRAB_CMDSTAT_OFFSET 0x0000002c 121#define CHIPCB_SRAB_RDL_OFFSET 0x0000003c 122 123#define CHIPCB_DMU_BASE 0x1800c000 124#define CHIPCB_CRU_STRAPS_CTRL_OFFSET 0x2a0 125#define CHIPCB_CRU_STRAPS_4BYTE (1 << 15) 126 127#endif /* _CHIPCOMMONB_H */ 128