1/*
2 *  Copyright (C) 2001  MandrakeSoft S.A.
3 *  Copyright 2010 Red Hat, Inc. and/or its affiliates.
4 *
5 *    MandrakeSoft S.A.
6 *    43, rue d'Aboukir
7 *    75002 Paris - France
8 *    http://www.linux-mandrake.com/
9 *    http://www.mandrakesoft.com/
10 *
11 *  This library is free software; you can redistribute it and/or
12 *  modify it under the terms of the GNU Lesser General Public
13 *  License as published by the Free Software Foundation; either
14 *  version 2 of the License, or (at your option) any later version.
15 *
16 *  This library is distributed in the hope that it will be useful,
17 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19 *  Lesser General Public License for more details.
20 *
21 *  You should have received a copy of the GNU Lesser General Public
22 *  License along with this library; if not, write to the Free Software
23 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
24 *
25 *  Yunhong Jiang <yunhong.jiang@intel.com>
26 *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
27 *  Based on Xen 3.1 code.
28 */
29
30#include <linux/kvm_host.h>
31#include <linux/kvm.h>
32#include <linux/mm.h>
33#include <linux/highmem.h>
34#include <linux/smp.h>
35#include <linux/hrtimer.h>
36#include <linux/io.h>
37#include <linux/slab.h>
38#include <asm/processor.h>
39#include <asm/page.h>
40#include <asm/current.h>
41#include <trace/events/kvm.h>
42
43#include "ioapic.h"
44#include "lapic.h"
45#include "irq.h"
46
47#define ioapic_debug(fmt, arg...)
48static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
49
50static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
51					  unsigned long addr,
52					  unsigned long length)
53{
54	unsigned long result = 0;
55
56	switch (ioapic->ioregsel) {
57	case IOAPIC_REG_VERSION:
58		result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
59			  | (IOAPIC_VERSION_ID & 0xff));
60		break;
61
62	case IOAPIC_REG_APIC_ID:
63	case IOAPIC_REG_ARB_ID:
64		result = ((ioapic->id & 0xf) << 24);
65		break;
66
67	default:
68		{
69			u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
70			u64 redir_content;
71
72			ASSERT(redir_index < IOAPIC_NUM_PINS);
73
74			redir_content = ioapic->redirtbl[redir_index].bits;
75			result = (ioapic->ioregsel & 0x1) ?
76			    (redir_content >> 32) & 0xffffffff :
77			    redir_content & 0xffffffff;
78			break;
79		}
80	}
81
82	return result;
83}
84
85static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
86{
87	union kvm_ioapic_redirect_entry *pent;
88	int injected = -1;
89
90	pent = &ioapic->redirtbl[idx];
91
92	if (!pent->fields.mask) {
93		injected = ioapic_deliver(ioapic, idx);
94		if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
95			pent->fields.remote_irr = 1;
96	}
97
98	return injected;
99}
100
101static void update_handled_vectors(struct kvm_ioapic *ioapic)
102{
103	DECLARE_BITMAP(handled_vectors, 256);
104	int i;
105
106	memset(handled_vectors, 0, sizeof(handled_vectors));
107	for (i = 0; i < IOAPIC_NUM_PINS; ++i)
108		__set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
109	memcpy(ioapic->handled_vectors, handled_vectors,
110	       sizeof(handled_vectors));
111	smp_wmb();
112}
113
114static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
115{
116	unsigned index;
117	bool mask_before, mask_after;
118	union kvm_ioapic_redirect_entry *e;
119
120	switch (ioapic->ioregsel) {
121	case IOAPIC_REG_VERSION:
122		/* Writes are ignored. */
123		break;
124
125	case IOAPIC_REG_APIC_ID:
126		ioapic->id = (val >> 24) & 0xf;
127		break;
128
129	case IOAPIC_REG_ARB_ID:
130		break;
131
132	default:
133		index = (ioapic->ioregsel - 0x10) >> 1;
134
135		ioapic_debug("change redir index %x val %x\n", index, val);
136		if (index >= IOAPIC_NUM_PINS)
137			return;
138		e = &ioapic->redirtbl[index];
139		mask_before = e->fields.mask;
140		if (ioapic->ioregsel & 1) {
141			e->bits &= 0xffffffff;
142			e->bits |= (u64) val << 32;
143		} else {
144			e->bits &= ~0xffffffffULL;
145			e->bits |= (u32) val;
146			e->fields.remote_irr = 0;
147		}
148		update_handled_vectors(ioapic);
149		mask_after = e->fields.mask;
150		if (mask_before != mask_after)
151			kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
152		if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
153		    && ioapic->irr & (1 << index))
154			ioapic_service(ioapic, index);
155		break;
156	}
157}
158
159static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
160{
161	union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
162	struct kvm_lapic_irq irqe;
163
164	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
165		     "vector=%x trig_mode=%x\n",
166		     entry->fields.dest, entry->fields.dest_mode,
167		     entry->fields.delivery_mode, entry->fields.vector,
168		     entry->fields.trig_mode);
169
170	irqe.dest_id = entry->fields.dest_id;
171	irqe.vector = entry->fields.vector;
172	irqe.dest_mode = entry->fields.dest_mode;
173	irqe.trig_mode = entry->fields.trig_mode;
174	irqe.delivery_mode = entry->fields.delivery_mode << 8;
175	irqe.level = 1;
176	irqe.shorthand = 0;
177
178#ifdef CONFIG_X86
179	/* Always delivery PIT interrupt to vcpu 0 */
180	if (irq == 0) {
181		irqe.dest_mode = 0; /* Physical mode. */
182		/* need to read apic_id from apic regiest since
183		 * it can be rewritten */
184		irqe.dest_id = ioapic->kvm->bsp_vcpu->vcpu_id;
185	}
186#endif
187	return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
188}
189
190int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
191{
192	u32 old_irr;
193	u32 mask = 1 << irq;
194	union kvm_ioapic_redirect_entry entry;
195	int ret = 1;
196
197	spin_lock(&ioapic->lock);
198	old_irr = ioapic->irr;
199	if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
200		entry = ioapic->redirtbl[irq];
201		level ^= entry.fields.polarity;
202		if (!level)
203			ioapic->irr &= ~mask;
204		else {
205			int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
206			ioapic->irr |= mask;
207			if ((edge && old_irr != ioapic->irr) ||
208			    (!edge && !entry.fields.remote_irr))
209				ret = ioapic_service(ioapic, irq);
210			else
211				ret = 0; /* report coalesced interrupt */
212		}
213		trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
214	}
215	spin_unlock(&ioapic->lock);
216
217	return ret;
218}
219
220static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
221				     int trigger_mode)
222{
223	int i;
224
225	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
226		union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
227
228		if (ent->fields.vector != vector)
229			continue;
230
231		/*
232		 * We are dropping lock while calling ack notifiers because ack
233		 * notifier callbacks for assigned devices call into IOAPIC
234		 * recursively. Since remote_irr is cleared only after call
235		 * to notifiers if the same vector will be delivered while lock
236		 * is dropped it will be put into irr and will be delivered
237		 * after ack notifier returns.
238		 */
239		spin_unlock(&ioapic->lock);
240		kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
241		spin_lock(&ioapic->lock);
242
243		if (trigger_mode != IOAPIC_LEVEL_TRIG)
244			continue;
245
246		ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
247		ent->fields.remote_irr = 0;
248		if (!ent->fields.mask && (ioapic->irr & (1 << i)))
249			ioapic_service(ioapic, i);
250	}
251}
252
253void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
254{
255	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
256
257	smp_rmb();
258	if (!test_bit(vector, ioapic->handled_vectors))
259		return;
260	spin_lock(&ioapic->lock);
261	__kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
262	spin_unlock(&ioapic->lock);
263}
264
265static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
266{
267	return container_of(dev, struct kvm_ioapic, dev);
268}
269
270static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
271{
272	return ((addr >= ioapic->base_address &&
273		 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
274}
275
276static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
277			    void *val)
278{
279	struct kvm_ioapic *ioapic = to_ioapic(this);
280	u32 result;
281	if (!ioapic_in_range(ioapic, addr))
282		return -EOPNOTSUPP;
283
284	ioapic_debug("addr %lx\n", (unsigned long)addr);
285	ASSERT(!(addr & 0xf));	/* check alignment */
286
287	addr &= 0xff;
288	spin_lock(&ioapic->lock);
289	switch (addr) {
290	case IOAPIC_REG_SELECT:
291		result = ioapic->ioregsel;
292		break;
293
294	case IOAPIC_REG_WINDOW:
295		result = ioapic_read_indirect(ioapic, addr, len);
296		break;
297
298	default:
299		result = 0;
300		break;
301	}
302	spin_unlock(&ioapic->lock);
303
304	switch (len) {
305	case 8:
306		*(u64 *) val = result;
307		break;
308	case 1:
309	case 2:
310	case 4:
311		memcpy(val, (char *)&result, len);
312		break;
313	default:
314		printk(KERN_WARNING "ioapic: wrong length %d\n", len);
315	}
316	return 0;
317}
318
319static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
320			     const void *val)
321{
322	struct kvm_ioapic *ioapic = to_ioapic(this);
323	u32 data;
324	if (!ioapic_in_range(ioapic, addr))
325		return -EOPNOTSUPP;
326
327	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
328		     (void*)addr, len, val);
329	ASSERT(!(addr & 0xf));	/* check alignment */
330
331	if (len == 4 || len == 8)
332		data = *(u32 *) val;
333	else {
334		printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
335		return 0;
336	}
337
338	addr &= 0xff;
339	spin_lock(&ioapic->lock);
340	switch (addr) {
341	case IOAPIC_REG_SELECT:
342		ioapic->ioregsel = data;
343		break;
344
345	case IOAPIC_REG_WINDOW:
346		ioapic_write_indirect(ioapic, data);
347		break;
348#ifdef	CONFIG_IA64
349	case IOAPIC_REG_EOI:
350		__kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
351		break;
352#endif
353
354	default:
355		break;
356	}
357	spin_unlock(&ioapic->lock);
358	return 0;
359}
360
361void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
362{
363	int i;
364
365	for (i = 0; i < IOAPIC_NUM_PINS; i++)
366		ioapic->redirtbl[i].fields.mask = 1;
367	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
368	ioapic->ioregsel = 0;
369	ioapic->irr = 0;
370	ioapic->id = 0;
371	update_handled_vectors(ioapic);
372}
373
374static const struct kvm_io_device_ops ioapic_mmio_ops = {
375	.read     = ioapic_mmio_read,
376	.write    = ioapic_mmio_write,
377};
378
379int kvm_ioapic_init(struct kvm *kvm)
380{
381	struct kvm_ioapic *ioapic;
382	int ret;
383
384	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
385	if (!ioapic)
386		return -ENOMEM;
387	spin_lock_init(&ioapic->lock);
388	kvm->arch.vioapic = ioapic;
389	kvm_ioapic_reset(ioapic);
390	kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
391	ioapic->kvm = kvm;
392	mutex_lock(&kvm->slots_lock);
393	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
394	mutex_unlock(&kvm->slots_lock);
395	if (ret < 0) {
396		kvm->arch.vioapic = NULL;
397		kfree(ioapic);
398	}
399
400	return ret;
401}
402
403void kvm_ioapic_destroy(struct kvm *kvm)
404{
405	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
406
407	if (ioapic) {
408		kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
409		kvm->arch.vioapic = NULL;
410		kfree(ioapic);
411	}
412}
413
414int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
415{
416	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
417	if (!ioapic)
418		return -EINVAL;
419
420	spin_lock(&ioapic->lock);
421	memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
422	spin_unlock(&ioapic->lock);
423	return 0;
424}
425
426int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
427{
428	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
429	if (!ioapic)
430		return -EINVAL;
431
432	spin_lock(&ioapic->lock);
433	memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
434	update_handled_vectors(ioapic);
435	spin_unlock(&ioapic->lock);
436	return 0;
437}
438