1/* 2 * Driver for DBRI sound chip found on Sparcs. 3 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net) 4 * 5 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl) 6 * 7 * Based entirely upon drivers/sbus/audio/dbri.c which is: 8 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de) 9 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org) 10 * 11 * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO 12 * on Sun SPARCStation 10, 20, LX and Voyager models. 13 * 14 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel 15 * data time multiplexer with ISDN support (aka T7259) 16 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel. 17 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?). 18 * Documentation: 19 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from 20 * Sparc Technology Business (courtesy of Sun Support) 21 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent 22 * available from the Lucent (formerly AT&T microelectronics) home 23 * page. 24 * - http://www.freesoft.org/Linux/DBRI/ 25 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec 26 * Interfaces: CHI, Audio In & Out, 2 bits parallel 27 * Documentation: from the Crystal Semiconductor home page. 28 * 29 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between 30 * memory and a serial device (long pipes, no. 0-15) or between two serial 31 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial 32 * device (short pipes). 33 * A timeslot defines the bit-offset and no. of bits read from a serial device. 34 * The timeslots are linked to 6 circular lists, one for each direction for 35 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes 36 * (the second one is a monitor/tee pipe, valid only for serial input). 37 * 38 * The mmcodec is connected via the CHI bus and needs the data & some 39 * parameters (volume, output selection) time multiplexed in 8 byte 40 * chunks. It also has a control mode, which serves for audio format setting. 41 * 42 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on 43 * the same CHI bus, so I thought perhaps it is possible to use the on-board 44 * & the speakerbox codec simultaneously, giving 2 (not very independent :-) 45 * audio devices. But the SUN HW group decided against it, at least on my 46 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly 47 * connected. 48 * 49 * I've tried to stick to the following function naming conventions: 50 * snd_* ALSA stuff 51 * cs4215_* CS4215 codec specific stuff 52 * dbri_* DBRI high-level stuff 53 * other DBRI low-level stuff 54 */ 55 56#include <linux/interrupt.h> 57#include <linux/delay.h> 58#include <linux/irq.h> 59#include <linux/io.h> 60#include <linux/dma-mapping.h> 61#include <linux/gfp.h> 62 63#include <sound/core.h> 64#include <sound/pcm.h> 65#include <sound/pcm_params.h> 66#include <sound/info.h> 67#include <sound/control.h> 68#include <sound/initval.h> 69 70#include <linux/of.h> 71#include <linux/of_device.h> 72#include <asm/atomic.h> 73 74MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets"); 75MODULE_DESCRIPTION("Sun DBRI"); 76MODULE_LICENSE("GPL"); 77MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}"); 78 79static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 80static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 81/* Enable this card */ 82static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 83 84module_param_array(index, int, NULL, 0444); 85MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard."); 86module_param_array(id, charp, NULL, 0444); 87MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard."); 88module_param_array(enable, bool, NULL, 0444); 89MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard."); 90 91#undef DBRI_DEBUG 92 93#define D_INT (1<<0) 94#define D_GEN (1<<1) 95#define D_CMD (1<<2) 96#define D_MM (1<<3) 97#define D_USR (1<<4) 98#define D_DESC (1<<5) 99 100static int dbri_debug; 101module_param(dbri_debug, int, 0644); 102MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard."); 103 104#ifdef DBRI_DEBUG 105static char *cmds[] = { 106 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS", 107 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV" 108}; 109 110#define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x) 111 112#else 113#define dprintk(a, x...) do { } while (0) 114 115#endif /* DBRI_DEBUG */ 116 117#define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \ 118 (intr << 27) | \ 119 value) 120 121/*************************************************************************** 122 CS4215 specific definitions and structures 123****************************************************************************/ 124 125struct cs4215 { 126 __u8 data[4]; /* Data mode: Time slots 5-8 */ 127 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */ 128 __u8 onboard; 129 __u8 offset; /* Bit offset from frame sync to time slot 1 */ 130 volatile __u32 status; 131 volatile __u32 version; 132 __u8 precision; /* In bits, either 8 or 16 */ 133 __u8 channels; /* 1 or 2 */ 134}; 135 136/* 137 * Control mode first 138 */ 139 140/* Time Slot 1, Status register */ 141#define CS4215_CLB (1<<2) /* Control Latch Bit */ 142#define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */ 143 /* 0: line: 2.8V, speaker 8V */ 144#define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */ 145#define CS4215_RSRVD_1 (1<<5) 146 147/* Time Slot 2, Data Format Register */ 148#define CS4215_DFR_LINEAR16 0 149#define CS4215_DFR_ULAW 1 150#define CS4215_DFR_ALAW 2 151#define CS4215_DFR_LINEAR8 3 152#define CS4215_DFR_STEREO (1<<2) 153static struct { 154 unsigned short freq; 155 unsigned char xtal; 156 unsigned char csval; 157} CS4215_FREQ[] = { 158 { 8000, (1 << 4), (0 << 3) }, 159 { 16000, (1 << 4), (1 << 3) }, 160 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */ 161 { 32000, (1 << 4), (3 << 3) }, 162 /* { NA, (1 << 4), (4 << 3) }, */ 163 /* { NA, (1 << 4), (5 << 3) }, */ 164 { 48000, (1 << 4), (6 << 3) }, 165 { 9600, (1 << 4), (7 << 3) }, 166 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */ 167 { 11025, (2 << 4), (1 << 3) }, 168 { 18900, (2 << 4), (2 << 3) }, 169 { 22050, (2 << 4), (3 << 3) }, 170 { 37800, (2 << 4), (4 << 3) }, 171 { 44100, (2 << 4), (5 << 3) }, 172 { 33075, (2 << 4), (6 << 3) }, 173 { 6615, (2 << 4), (7 << 3) }, 174 { 0, 0, 0} 175}; 176 177#define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */ 178 179#define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */ 180 181/* Time Slot 3, Serial Port Control register */ 182#define CS4215_XEN (1<<0) /* 0: Enable serial output */ 183#define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */ 184#define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */ 185#define CS4215_BSEL_128 (1<<2) 186#define CS4215_BSEL_256 (2<<2) 187#define CS4215_MCK_MAST (0<<4) /* Master clock */ 188#define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */ 189#define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */ 190#define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */ 191#define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */ 192 193/* Time Slot 4, Test Register */ 194#define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */ 195#define CS4215_ENL (1<<1) /* Enable Loopback Testing */ 196 197/* Time Slot 5, Parallel Port Register */ 198/* Read only here and the same as the in data mode */ 199 200/* Time Slot 6, Reserved */ 201 202/* Time Slot 7, Version Register */ 203#define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */ 204 205/* Time Slot 8, Reserved */ 206 207/* 208 * Data mode 209 */ 210/* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */ 211 212/* Time Slot 5, Output Setting */ 213#define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */ 214#define CS4215_LE (1<<6) /* Line Out Enable */ 215#define CS4215_HE (1<<7) /* Headphone Enable */ 216 217/* Time Slot 6, Output Setting */ 218#define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */ 219#define CS4215_SE (1<<6) /* Speaker Enable */ 220#define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */ 221 222/* Time Slot 7, Input Setting */ 223#define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */ 224#define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */ 225#define CS4215_OVR (1<<5) /* 1: Over range condition occurred */ 226#define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */ 227#define CS4215_PIO1 (1<<7) 228 229/* Time Slot 8, Input Setting */ 230#define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */ 231#define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */ 232 233/*************************************************************************** 234 DBRI specific definitions and structures 235****************************************************************************/ 236 237/* DBRI main registers */ 238#define REG0 0x00 /* Status and Control */ 239#define REG1 0x04 /* Mode and Interrupt */ 240#define REG2 0x08 /* Parallel IO */ 241#define REG3 0x0c /* Test */ 242#define REG8 0x20 /* Command Queue Pointer */ 243#define REG9 0x24 /* Interrupt Queue Pointer */ 244 245#define DBRI_NO_CMDS 64 246#define DBRI_INT_BLK 64 247#define DBRI_NO_DESCS 64 248#define DBRI_NO_PIPES 32 249#define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1) 250 251#define DBRI_REC 0 252#define DBRI_PLAY 1 253#define DBRI_NO_STREAMS 2 254 255/* One transmit/receive descriptor */ 256/* When ba != 0 descriptor is used */ 257struct dbri_mem { 258 volatile __u32 word1; 259 __u32 ba; /* Transmit/Receive Buffer Address */ 260 __u32 nda; /* Next Descriptor Address */ 261 volatile __u32 word4; 262}; 263 264/* This structure is in a DMA region where it can accessed by both 265 * the CPU and the DBRI 266 */ 267struct dbri_dma { 268 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */ 269 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */ 270 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */ 271}; 272 273#define dbri_dma_off(member, elem) \ 274 ((u32)(unsigned long) \ 275 (&(((struct dbri_dma *)0)->member[elem]))) 276 277enum in_or_out { PIPEinput, PIPEoutput }; 278 279struct dbri_pipe { 280 u32 sdp; /* SDP command word */ 281 int nextpipe; /* Next pipe in linked list */ 282 int length; /* Length of timeslot (bits) */ 283 int first_desc; /* Index of first descriptor */ 284 int desc; /* Index of active descriptor */ 285 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */ 286}; 287 288/* Per stream (playback or record) information */ 289struct dbri_streaminfo { 290 struct snd_pcm_substream *substream; 291 u32 dvma_buffer; /* Device view of ALSA DMA buffer */ 292 int size; /* Size of DMA buffer */ 293 size_t offset; /* offset in user buffer */ 294 int pipe; /* Data pipe used */ 295 int left_gain; /* mixer elements */ 296 int right_gain; 297}; 298 299/* This structure holds the information for both chips (DBRI & CS4215) */ 300struct snd_dbri { 301 int regs_size, irq; /* Needed for unload */ 302 struct platform_device *op; /* OF device info */ 303 spinlock_t lock; 304 305 struct dbri_dma *dma; /* Pointer to our DMA block */ 306 u32 dma_dvma; /* DBRI visible DMA address */ 307 308 void __iomem *regs; /* dbri HW regs */ 309 int dbri_irqp; /* intr queue pointer */ 310 311 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */ 312 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */ 313 spinlock_t cmdlock; /* Protects cmd queue accesses */ 314 s32 *cmdptr; /* Pointer to the last queued cmd */ 315 316 int chi_bpf; 317 318 struct cs4215 mm; /* mmcodec special info */ 319 /* per stream (playback/record) info */ 320 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS]; 321}; 322 323#define DBRI_MAX_VOLUME 63 /* Output volume */ 324#define DBRI_MAX_GAIN 15 /* Input gain */ 325 326/* DBRI Reg0 - Status Control Register - defines. (Page 17) */ 327#define D_P (1<<15) /* Program command & queue pointer valid */ 328#define D_G (1<<14) /* Allow 4-Word SBus Burst */ 329#define D_S (1<<13) /* Allow 16-Word SBus Burst */ 330#define D_E (1<<12) /* Allow 8-Word SBus Burst */ 331#define D_X (1<<7) /* Sanity Timer Disable */ 332#define D_T (1<<6) /* Permit activation of the TE interface */ 333#define D_N (1<<5) /* Permit activation of the NT interface */ 334#define D_C (1<<4) /* Permit activation of the CHI interface */ 335#define D_F (1<<3) /* Force Sanity Timer Time-Out */ 336#define D_D (1<<2) /* Disable Master Mode */ 337#define D_H (1<<1) /* Halt for Analysis */ 338#define D_R (1<<0) /* Soft Reset */ 339 340/* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */ 341#define D_LITTLE_END (1<<8) /* Byte Order */ 342#define D_BIG_END (0<<8) /* Byte Order */ 343#define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */ 344#define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */ 345#define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */ 346#define D_MBE (1<<1) /* Burst Error on SBus (read only) */ 347#define D_IR (1<<0) /* Interrupt Indicator (read only) */ 348 349/* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */ 350#define D_ENPIO3 (1<<7) /* Enable Pin 3 */ 351#define D_ENPIO2 (1<<6) /* Enable Pin 2 */ 352#define D_ENPIO1 (1<<5) /* Enable Pin 1 */ 353#define D_ENPIO0 (1<<4) /* Enable Pin 0 */ 354#define D_ENPIO (0xf0) /* Enable all the pins */ 355#define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */ 356#define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */ 357#define D_PIO1 (1<<1) /* Pin 1: 0: Reset */ 358#define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */ 359 360/* DBRI Commands (Page 20) */ 361#define D_WAIT 0x0 /* Stop execution */ 362#define D_PAUSE 0x1 /* Flush long pipes */ 363#define D_JUMP 0x2 /* New command queue */ 364#define D_IIQ 0x3 /* Initialize Interrupt Queue */ 365#define D_REX 0x4 /* Report command execution via interrupt */ 366#define D_SDP 0x5 /* Setup Data Pipe */ 367#define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */ 368#define D_DTS 0x7 /* Define Time Slot */ 369#define D_SSP 0x8 /* Set short Data Pipe */ 370#define D_CHI 0x9 /* Set CHI Global Mode */ 371#define D_NT 0xa /* NT Command */ 372#define D_TE 0xb /* TE Command */ 373#define D_CDEC 0xc /* Codec setup */ 374#define D_TEST 0xd /* No comment */ 375#define D_CDM 0xe /* CHI Data mode command */ 376 377/* Special bits for some commands */ 378#define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */ 379 380/* Setup Data Pipe */ 381/* IRM */ 382#define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */ 383#define D_SDP_CHANGE (2<<18) /* Report any changes */ 384#define D_SDP_EVERY (3<<18) /* Report any changes */ 385#define D_SDP_EOL (1<<17) /* EOL interrupt enable */ 386#define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */ 387 388/* Pipe data MODE */ 389#define D_SDP_MEM (0<<13) /* To/from memory */ 390#define D_SDP_HDLC (2<<13) 391#define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */ 392#define D_SDP_SER (4<<13) /* Serial to serial */ 393#define D_SDP_FIXED (6<<13) /* Short only */ 394#define D_SDP_MODE(v) ((v)&(7<<13)) 395 396#define D_SDP_TO_SER (1<<12) /* Direction */ 397#define D_SDP_FROM_SER (0<<12) /* Direction */ 398#define D_SDP_MSB (1<<11) /* Bit order within Byte */ 399#define D_SDP_LSB (0<<11) /* Bit order within Byte */ 400#define D_SDP_P (1<<10) /* Pointer Valid */ 401#define D_SDP_A (1<<8) /* Abort */ 402#define D_SDP_C (1<<7) /* Clear */ 403 404/* Define Time Slot */ 405#define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */ 406#define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */ 407#define D_DTS_INS (1<<15) /* Insert Time Slot */ 408#define D_DTS_DEL (0<<15) /* Delete Time Slot */ 409#define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */ 410#define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */ 411 412/* Time Slot defines */ 413#define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */ 414#define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */ 415#define D_TS_DI (1<<13) /* Data Invert */ 416#define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */ 417#define D_TS_MONITOR (2<<10) /* Monitor pipe */ 418#define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */ 419#define D_TS_ANCHOR (7<<10) /* Starting short pipes */ 420#define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */ 421#define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */ 422 423/* Concentration Highway Interface Modes */ 424#define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */ 425#define D_CHI_IR (1<<15) /* Immediate Interrupt Report */ 426#define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */ 427#define D_CHI_OD (1<<13) /* Open Drain Enable */ 428#define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */ 429#define D_CHI_FD (1<<11) /* Frame Drive */ 430#define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */ 431 432/* NT: These are here for completeness */ 433#define D_NT_FBIT (1<<17) /* Frame Bit */ 434#define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */ 435#define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */ 436#define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */ 437#define D_NT_ISNT (1<<13) /* Configure interface as NT */ 438#define D_NT_FT (1<<12) /* Fixed Timing */ 439#define D_NT_EZ (1<<11) /* Echo Channel is Zeros */ 440#define D_NT_IFA (1<<10) /* Inhibit Final Activation */ 441#define D_NT_ACT (1<<9) /* Activate Interface */ 442#define D_NT_MFE (1<<8) /* Multiframe Enable */ 443#define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */ 444#define D_NT_LLB(v) ((v)<<2) /* Local Loopback */ 445#define D_NT_FACT (1<<1) /* Force Activation */ 446#define D_NT_ABV (1<<0) /* Activate Bipolar Violation */ 447 448/* Codec Setup */ 449#define D_CDEC_CK(v) ((v)<<24) /* Clock Select */ 450#define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */ 451#define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */ 452 453/* Test */ 454#define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */ 455#define D_TEST_SIZE(v) ((v)<<11) /* */ 456#define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */ 457#define D_TEST_PROC 0x6 /* Microprocessor test */ 458#define D_TEST_SER 0x7 /* Serial-Controller test */ 459#define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */ 460#define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */ 461#define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */ 462#define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */ 463#define D_TEST_DUMP 0xe /* ROM Dump */ 464 465/* CHI Data Mode */ 466#define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */ 467#define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */ 468#define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */ 469#define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */ 470#define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */ 471#define D_CDM_REN (1 << 0) /* Receive Highway Enable */ 472 473/* The Interrupts */ 474#define D_INTR_BRDY 1 /* Buffer Ready for processing */ 475#define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */ 476#define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */ 477#define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */ 478#define D_INTR_EOL 5 /* End of List */ 479#define D_INTR_CMDI 6 /* Command has bean read */ 480#define D_INTR_XCMP 8 /* Transmission of frame complete */ 481#define D_INTR_SBRI 9 /* BRI status change info */ 482#define D_INTR_FXDT 10 /* Fixed data change */ 483#define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */ 484#define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */ 485#define D_INTR_DBYT 12 /* Dropped by frame slip */ 486#define D_INTR_RBYT 13 /* Repeated by frame slip */ 487#define D_INTR_LINT 14 /* Lost Interrupt */ 488#define D_INTR_UNDR 15 /* DMA underrun */ 489 490#define D_INTR_TE 32 491#define D_INTR_NT 34 492#define D_INTR_CHI 36 493#define D_INTR_CMD 38 494 495#define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f) 496#define D_INTR_GETCODE(v) (((v) >> 20) & 0xf) 497#define D_INTR_GETCMD(v) (((v) >> 16) & 0xf) 498#define D_INTR_GETVAL(v) ((v) & 0xffff) 499#define D_INTR_GETRVAL(v) ((v) & 0xfffff) 500 501#define D_P_0 0 /* TE receive anchor */ 502#define D_P_1 1 /* TE transmit anchor */ 503#define D_P_2 2 /* NT transmit anchor */ 504#define D_P_3 3 /* NT receive anchor */ 505#define D_P_4 4 /* CHI send data */ 506#define D_P_5 5 /* CHI receive data */ 507#define D_P_6 6 /* */ 508#define D_P_7 7 /* */ 509#define D_P_8 8 /* */ 510#define D_P_9 9 /* */ 511#define D_P_10 10 /* */ 512#define D_P_11 11 /* */ 513#define D_P_12 12 /* */ 514#define D_P_13 13 /* */ 515#define D_P_14 14 /* */ 516#define D_P_15 15 /* */ 517#define D_P_16 16 /* CHI anchor pipe */ 518#define D_P_17 17 /* CHI send */ 519#define D_P_18 18 /* CHI receive */ 520#define D_P_19 19 /* CHI receive */ 521#define D_P_20 20 /* CHI receive */ 522#define D_P_21 21 /* */ 523#define D_P_22 22 /* */ 524#define D_P_23 23 /* */ 525#define D_P_24 24 /* */ 526#define D_P_25 25 /* */ 527#define D_P_26 26 /* */ 528#define D_P_27 27 /* */ 529#define D_P_28 28 /* */ 530#define D_P_29 29 /* */ 531#define D_P_30 30 /* */ 532#define D_P_31 31 /* */ 533 534/* Transmit descriptor defines */ 535#define DBRI_TD_F (1 << 31) /* End of Frame */ 536#define DBRI_TD_D (1 << 30) /* Do not append CRC */ 537#define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */ 538#define DBRI_TD_B (1 << 15) /* Final interrupt */ 539#define DBRI_TD_M (1 << 14) /* Marker interrupt */ 540#define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */ 541#define DBRI_TD_FCNT(v) (v) /* Flag Count */ 542#define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */ 543#define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */ 544#define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */ 545#define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */ 546 /* Maximum buffer size per TD: almost 8KB */ 547#define DBRI_TD_MAXCNT ((1 << 13) - 4) 548 549/* Receive descriptor defines */ 550#define DBRI_RD_F (1 << 31) /* End of Frame */ 551#define DBRI_RD_C (1 << 30) /* Completed buffer */ 552#define DBRI_RD_B (1 << 15) /* Final interrupt */ 553#define DBRI_RD_M (1 << 14) /* Marker interrupt */ 554#define DBRI_RD_BCNT(v) (v) /* Buffer size */ 555#define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */ 556#define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */ 557#define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */ 558#define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */ 559#define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */ 560#define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */ 561 562/* stream_info[] access */ 563/* Translate the ALSA direction into the array index */ 564#define DBRI_STREAMNO(substream) \ 565 (substream->stream == \ 566 SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC) 567 568/* Return a pointer to dbri_streaminfo */ 569#define DBRI_STREAM(dbri, substream) \ 570 &dbri->stream_info[DBRI_STREAMNO(substream)] 571 572/* 573 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr. 574 * So we have to reverse the bits. Note: not all bit lengths are supported 575 */ 576static __u32 reverse_bytes(__u32 b, int len) 577{ 578 switch (len) { 579 case 32: 580 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 581 case 16: 582 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 583 case 8: 584 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 585 case 4: 586 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 587 case 2: 588 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 589 case 1: 590 case 0: 591 break; 592 default: 593 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n"); 594 }; 595 596 return b; 597} 598 599/* 600**************************************************************************** 601************** DBRI initialization and command synchronization ************* 602**************************************************************************** 603 604Commands are sent to the DBRI by building a list of them in memory, 605then writing the address of the first list item to DBRI register 8. 606The list is terminated with a WAIT command, which generates a 607CPU interrupt to signal completion. 608 609Since the DBRI can run in parallel with the CPU, several means of 610synchronization present themselves. The method implemented here uses 611the dbri_cmdwait() to wait for execution of batch of sent commands. 612 613A circular command buffer is used here. A new command is being added 614while another can be executed. The scheme works by adding two WAIT commands 615after each sent batch of commands. When the next batch is prepared it is 616added after the WAIT commands then the WAITs are replaced with single JUMP 617command to the new batch. The the DBRI is forced to reread the last WAIT 618command (replaced by the JUMP by then). If the DBRI is still executing 619previous commands the request to reread the WAIT command is ignored. 620 621Every time a routine wants to write commands to the DBRI, it must 622first call dbri_cmdlock() and get pointer to a free space in 623dbri->dma->cmd buffer. After this, the commands can be written to 624the buffer, and dbri_cmdsend() is called with the final pointer value 625to send them to the DBRI. 626 627*/ 628 629#define MAXLOOPS 20 630/* 631 * Wait for the current command string to execute 632 */ 633static void dbri_cmdwait(struct snd_dbri *dbri) 634{ 635 int maxloops = MAXLOOPS; 636 unsigned long flags; 637 638 /* Delay if previous commands are still being processed */ 639 spin_lock_irqsave(&dbri->lock, flags); 640 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) { 641 spin_unlock_irqrestore(&dbri->lock, flags); 642 msleep_interruptible(1); 643 spin_lock_irqsave(&dbri->lock, flags); 644 } 645 spin_unlock_irqrestore(&dbri->lock, flags); 646 647 if (maxloops == 0) 648 printk(KERN_ERR "DBRI: Chip never completed command buffer\n"); 649 else 650 dprintk(D_CMD, "Chip completed command buffer (%d)\n", 651 MAXLOOPS - maxloops - 1); 652} 653/* 654 * Lock the command queue and return pointer to space for len cmd words 655 * It locks the cmdlock spinlock. 656 */ 657static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len) 658{ 659 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */ 660 len += 2; 661 spin_lock(&dbri->cmdlock); 662 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2) 663 return dbri->cmdptr + 2; 664 else if (len < sbus_readl(dbri->regs + REG8) - dbri->dma_dvma) 665 return dbri->dma->cmd; 666 else 667 printk(KERN_ERR "DBRI: no space for commands."); 668 669 return NULL; 670} 671 672/* 673 * Send prepared cmd string. It works by writing a JUMP cmd into 674 * the last WAIT cmd and force DBRI to reread the cmd. 675 * The JUMP cmd points to the new cmd string. 676 * It also releases the cmdlock spinlock. 677 * 678 * Lock must be held before calling this. 679 */ 680static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len) 681{ 682 s32 tmp, addr; 683 static int wait_id = 0; 684 685 wait_id++; 686 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */ 687 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id); 688 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id); 689 690 /* Replace the last command with JUMP */ 691 addr = dbri->dma_dvma + (cmd - len - dbri->dma->cmd) * sizeof(s32); 692 *(dbri->cmdptr+1) = addr; 693 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0); 694 695#ifdef DBRI_DEBUG 696 if (cmd > dbri->cmdptr) { 697 s32 *ptr; 698 699 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++) 700 dprintk(D_CMD, "cmd: %lx:%08x\n", 701 (unsigned long)ptr, *ptr); 702 } else { 703 s32 *ptr = dbri->cmdptr; 704 705 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr); 706 ptr++; 707 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr); 708 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++) 709 dprintk(D_CMD, "cmd: %lx:%08x\n", 710 (unsigned long)ptr, *ptr); 711 } 712#endif 713 714 /* Reread the last command */ 715 tmp = sbus_readl(dbri->regs + REG0); 716 tmp |= D_P; 717 sbus_writel(tmp, dbri->regs + REG0); 718 719 dbri->cmdptr = cmd; 720 spin_unlock(&dbri->cmdlock); 721} 722 723/* Lock must be held when calling this */ 724static void dbri_reset(struct snd_dbri *dbri) 725{ 726 int i; 727 u32 tmp; 728 729 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n", 730 sbus_readl(dbri->regs + REG0), 731 sbus_readl(dbri->regs + REG2), 732 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9)); 733 734 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */ 735 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++) 736 udelay(10); 737 738 /* A brute approach - DBRI falls back to working burst size by itself 739 * On SS20 D_S does not work, so do not try so high. */ 740 tmp = sbus_readl(dbri->regs + REG0); 741 tmp |= D_G | D_E; 742 tmp &= ~D_S; 743 sbus_writel(tmp, dbri->regs + REG0); 744} 745 746/* Lock must not be held before calling this */ 747static void __devinit dbri_initialize(struct snd_dbri *dbri) 748{ 749 s32 *cmd; 750 u32 dma_addr; 751 unsigned long flags; 752 int n; 753 754 spin_lock_irqsave(&dbri->lock, flags); 755 756 dbri_reset(dbri); 757 758 /* Initialize pipes */ 759 for (n = 0; n < DBRI_NO_PIPES; n++) 760 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1; 761 762 spin_lock_init(&dbri->cmdlock); 763 /* 764 * Initialize the interrupt ring buffer. 765 */ 766 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0); 767 dbri->dma->intr[0] = dma_addr; 768 dbri->dbri_irqp = 1; 769 /* 770 * Set up the interrupt queue 771 */ 772 spin_lock(&dbri->cmdlock); 773 cmd = dbri->cmdptr = dbri->dma->cmd; 774 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0); 775 *(cmd++) = dma_addr; 776 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 777 dbri->cmdptr = cmd; 778 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0); 779 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0); 780 dma_addr = dbri->dma_dvma + dbri_dma_off(cmd, 0); 781 sbus_writel(dma_addr, dbri->regs + REG8); 782 spin_unlock(&dbri->cmdlock); 783 784 spin_unlock_irqrestore(&dbri->lock, flags); 785 dbri_cmdwait(dbri); 786} 787 788/* 789**************************************************************************** 790************************** DBRI data pipe management *********************** 791**************************************************************************** 792 793While DBRI control functions use the command and interrupt buffers, the 794main data path takes the form of data pipes, which can be short (command 795and interrupt driven), or long (attached to DMA buffers). These functions 796provide a rudimentary means of setting up and managing the DBRI's pipes, 797but the calling functions have to make sure they respect the pipes' linked 798list ordering, among other things. The transmit and receive functions 799here interface closely with the transmit and receive interrupt code. 800 801*/ 802static inline int pipe_active(struct snd_dbri *dbri, int pipe) 803{ 804 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1)); 805} 806 807/* reset_pipe(dbri, pipe) 808 * 809 * Called on an in-use pipe to clear anything being transmitted or received 810 * Lock must be held before calling this. 811 */ 812static void reset_pipe(struct snd_dbri *dbri, int pipe) 813{ 814 int sdp; 815 int desc; 816 s32 *cmd; 817 818 if (pipe < 0 || pipe > DBRI_MAX_PIPE) { 819 printk(KERN_ERR "DBRI: reset_pipe called with " 820 "illegal pipe number\n"); 821 return; 822 } 823 824 sdp = dbri->pipes[pipe].sdp; 825 if (sdp == 0) { 826 printk(KERN_ERR "DBRI: reset_pipe called " 827 "on uninitialized pipe\n"); 828 return; 829 } 830 831 cmd = dbri_cmdlock(dbri, 3); 832 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P); 833 *(cmd++) = 0; 834 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 835 dbri_cmdsend(dbri, cmd, 3); 836 837 desc = dbri->pipes[pipe].first_desc; 838 if (desc >= 0) 839 do { 840 dbri->dma->desc[desc].ba = 0; 841 dbri->dma->desc[desc].nda = 0; 842 desc = dbri->next_desc[desc]; 843 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc); 844 845 dbri->pipes[pipe].desc = -1; 846 dbri->pipes[pipe].first_desc = -1; 847} 848 849/* 850 * Lock must be held before calling this. 851 */ 852static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp) 853{ 854 if (pipe < 0 || pipe > DBRI_MAX_PIPE) { 855 printk(KERN_ERR "DBRI: setup_pipe called " 856 "with illegal pipe number\n"); 857 return; 858 } 859 860 if ((sdp & 0xf800) != sdp) { 861 printk(KERN_ERR "DBRI: setup_pipe called " 862 "with strange SDP value\n"); 863 /* sdp &= 0xf800; */ 864 } 865 866 /* If this is a fixed receive pipe, arrange for an interrupt 867 * every time its data changes 868 */ 869 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER)) 870 sdp |= D_SDP_CHANGE; 871 872 sdp |= D_PIPE(pipe); 873 dbri->pipes[pipe].sdp = sdp; 874 dbri->pipes[pipe].desc = -1; 875 dbri->pipes[pipe].first_desc = -1; 876 877 reset_pipe(dbri, pipe); 878} 879 880/* 881 * Lock must be held before calling this. 882 */ 883static void link_time_slot(struct snd_dbri *dbri, int pipe, 884 int prevpipe, int nextpipe, 885 int length, int cycle) 886{ 887 s32 *cmd; 888 int val; 889 890 if (pipe < 0 || pipe > DBRI_MAX_PIPE 891 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE 892 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) { 893 printk(KERN_ERR 894 "DBRI: link_time_slot called with illegal pipe number\n"); 895 return; 896 } 897 898 if (dbri->pipes[pipe].sdp == 0 899 || dbri->pipes[prevpipe].sdp == 0 900 || dbri->pipes[nextpipe].sdp == 0) { 901 printk(KERN_ERR "DBRI: link_time_slot called " 902 "on uninitialized pipe\n"); 903 return; 904 } 905 906 dbri->pipes[prevpipe].nextpipe = pipe; 907 dbri->pipes[pipe].nextpipe = nextpipe; 908 dbri->pipes[pipe].length = length; 909 910 cmd = dbri_cmdlock(dbri, 4); 911 912 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) { 913 /* Deal with CHI special case: 914 * "If transmission on edges 0 or 1 is desired, then cycle n 915 * (where n = # of bit times per frame...) must be used." 916 * - DBRI data sheet, page 11 917 */ 918 if (prevpipe == 16 && cycle == 0) 919 cycle = dbri->chi_bpf; 920 921 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe; 922 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 923 *(cmd++) = 0; 924 *(cmd++) = 925 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); 926 } else { 927 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe; 928 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 929 *(cmd++) = 930 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); 931 *(cmd++) = 0; 932 } 933 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 934 935 dbri_cmdsend(dbri, cmd, 4); 936} 937 938 939/* xmit_fixed() / recv_fixed() 940 * 941 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not 942 * expected to change much, and which we don't need to buffer. 943 * The DBRI only interrupts us when the data changes (receive pipes), 944 * or only changes the data when this function is called (transmit pipes). 945 * Only short pipes (numbers 16-31) can be used in fixed data mode. 946 * 947 * These function operate on a 32-bit field, no matter how large 948 * the actual time slot is. The interrupt handler takes care of bit 949 * ordering and alignment. An 8-bit time slot will always end up 950 * in the low-order 8 bits, filled either MSB-first or LSB-first, 951 * depending on the settings passed to setup_pipe(). 952 * 953 * Lock must not be held before calling it. 954 */ 955static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data) 956{ 957 s32 *cmd; 958 unsigned long flags; 959 960 if (pipe < 16 || pipe > DBRI_MAX_PIPE) { 961 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n"); 962 return; 963 } 964 965 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) { 966 printk(KERN_ERR "DBRI: xmit_fixed: " 967 "Uninitialized pipe %d\n", pipe); 968 return; 969 } 970 971 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { 972 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe); 973 return; 974 } 975 976 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) { 977 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n", 978 pipe); 979 return; 980 } 981 982 /* DBRI short pipes always transmit LSB first */ 983 984 if (dbri->pipes[pipe].sdp & D_SDP_MSB) 985 data = reverse_bytes(data, dbri->pipes[pipe].length); 986 987 cmd = dbri_cmdlock(dbri, 3); 988 989 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe); 990 *(cmd++) = data; 991 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 992 993 spin_lock_irqsave(&dbri->lock, flags); 994 dbri_cmdsend(dbri, cmd, 3); 995 spin_unlock_irqrestore(&dbri->lock, flags); 996 dbri_cmdwait(dbri); 997 998} 999 1000static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr) 1001{ 1002 if (pipe < 16 || pipe > DBRI_MAX_PIPE) { 1003 printk(KERN_ERR "DBRI: recv_fixed called with " 1004 "illegal pipe number\n"); 1005 return; 1006 } 1007 1008 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { 1009 printk(KERN_ERR "DBRI: recv_fixed called on " 1010 "non-fixed pipe %d\n", pipe); 1011 return; 1012 } 1013 1014 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) { 1015 printk(KERN_ERR "DBRI: recv_fixed called on " 1016 "transmit pipe %d\n", pipe); 1017 return; 1018 } 1019 1020 dbri->pipes[pipe].recv_fixed_ptr = ptr; 1021} 1022 1023/* setup_descs() 1024 * 1025 * Setup transmit/receive data on a "long" pipe - i.e, one associated 1026 * with a DMA buffer. 1027 * 1028 * Only pipe numbers 0-15 can be used in this mode. 1029 * 1030 * This function takes a stream number pointing to a data buffer, 1031 * and work by building chains of descriptors which identify the 1032 * data buffers. Buffers too large for a single descriptor will 1033 * be spread across multiple descriptors. 1034 * 1035 * All descriptors create a ring buffer. 1036 * 1037 * Lock must be held before calling this. 1038 */ 1039static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period) 1040{ 1041 struct dbri_streaminfo *info = &dbri->stream_info[streamno]; 1042 __u32 dvma_buffer; 1043 int desc; 1044 int len; 1045 int first_desc = -1; 1046 int last_desc = -1; 1047 1048 if (info->pipe < 0 || info->pipe > 15) { 1049 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n"); 1050 return -2; 1051 } 1052 1053 if (dbri->pipes[info->pipe].sdp == 0) { 1054 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n", 1055 info->pipe); 1056 return -2; 1057 } 1058 1059 dvma_buffer = info->dvma_buffer; 1060 len = info->size; 1061 1062 if (streamno == DBRI_PLAY) { 1063 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) { 1064 printk(KERN_ERR "DBRI: setup_descs: " 1065 "Called on receive pipe %d\n", info->pipe); 1066 return -2; 1067 } 1068 } else { 1069 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) { 1070 printk(KERN_ERR 1071 "DBRI: setup_descs: Called on transmit pipe %d\n", 1072 info->pipe); 1073 return -2; 1074 } 1075 /* Should be able to queue multiple buffers 1076 * to receive on a pipe 1077 */ 1078 if (pipe_active(dbri, info->pipe)) { 1079 printk(KERN_ERR "DBRI: recv_on_pipe: " 1080 "Called on active pipe %d\n", info->pipe); 1081 return -2; 1082 } 1083 1084 /* Make sure buffer size is multiple of four */ 1085 len &= ~3; 1086 } 1087 1088 /* Free descriptors if pipe has any */ 1089 desc = dbri->pipes[info->pipe].first_desc; 1090 if (desc >= 0) 1091 do { 1092 dbri->dma->desc[desc].ba = 0; 1093 dbri->dma->desc[desc].nda = 0; 1094 desc = dbri->next_desc[desc]; 1095 } while (desc != -1 && 1096 desc != dbri->pipes[info->pipe].first_desc); 1097 1098 dbri->pipes[info->pipe].desc = -1; 1099 dbri->pipes[info->pipe].first_desc = -1; 1100 1101 desc = 0; 1102 while (len > 0) { 1103 int mylen; 1104 1105 for (; desc < DBRI_NO_DESCS; desc++) { 1106 if (!dbri->dma->desc[desc].ba) 1107 break; 1108 } 1109 1110 if (desc == DBRI_NO_DESCS) { 1111 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n"); 1112 return -1; 1113 } 1114 1115 if (len > DBRI_TD_MAXCNT) 1116 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */ 1117 else 1118 mylen = len; 1119 1120 if (mylen > period) 1121 mylen = period; 1122 1123 dbri->next_desc[desc] = -1; 1124 dbri->dma->desc[desc].ba = dvma_buffer; 1125 dbri->dma->desc[desc].nda = 0; 1126 1127 if (streamno == DBRI_PLAY) { 1128 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen); 1129 dbri->dma->desc[desc].word4 = 0; 1130 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B; 1131 } else { 1132 dbri->dma->desc[desc].word1 = 0; 1133 dbri->dma->desc[desc].word4 = 1134 DBRI_RD_B | DBRI_RD_BCNT(mylen); 1135 } 1136 1137 if (first_desc == -1) 1138 first_desc = desc; 1139 else { 1140 dbri->next_desc[last_desc] = desc; 1141 dbri->dma->desc[last_desc].nda = 1142 dbri->dma_dvma + dbri_dma_off(desc, desc); 1143 } 1144 1145 last_desc = desc; 1146 dvma_buffer += mylen; 1147 len -= mylen; 1148 } 1149 1150 if (first_desc == -1 || last_desc == -1) { 1151 printk(KERN_ERR "DBRI: setup_descs: " 1152 " Not enough descriptors available\n"); 1153 return -1; 1154 } 1155 1156 dbri->dma->desc[last_desc].nda = 1157 dbri->dma_dvma + dbri_dma_off(desc, first_desc); 1158 dbri->next_desc[last_desc] = first_desc; 1159 dbri->pipes[info->pipe].first_desc = first_desc; 1160 dbri->pipes[info->pipe].desc = first_desc; 1161 1162#ifdef DBRI_DEBUG 1163 for (desc = first_desc; desc != -1;) { 1164 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n", 1165 desc, 1166 dbri->dma->desc[desc].word1, 1167 dbri->dma->desc[desc].ba, 1168 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4); 1169 desc = dbri->next_desc[desc]; 1170 if (desc == first_desc) 1171 break; 1172 } 1173#endif 1174 return 0; 1175} 1176 1177/* 1178**************************************************************************** 1179************************** DBRI - CHI interface **************************** 1180**************************************************************************** 1181 1182The CHI is a four-wire (clock, frame sync, data in, data out) time-division 1183multiplexed serial interface which the DBRI can operate in either master 1184(give clock/frame sync) or slave (take clock/frame sync) mode. 1185 1186*/ 1187 1188enum master_or_slave { CHImaster, CHIslave }; 1189 1190/* 1191 * Lock must not be held before calling it. 1192 */ 1193static void reset_chi(struct snd_dbri *dbri, 1194 enum master_or_slave master_or_slave, 1195 int bits_per_frame) 1196{ 1197 s32 *cmd; 1198 int val; 1199 1200 /* Set CHI Anchor: Pipe 16 */ 1201 1202 cmd = dbri_cmdlock(dbri, 4); 1203 val = D_DTS_VO | D_DTS_VI | D_DTS_INS 1204 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16); 1205 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 1206 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); 1207 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); 1208 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 1209 dbri_cmdsend(dbri, cmd, 4); 1210 1211 dbri->pipes[16].sdp = 1; 1212 dbri->pipes[16].nextpipe = 16; 1213 1214 cmd = dbri_cmdlock(dbri, 4); 1215 1216 if (master_or_slave == CHIslave) { 1217 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS) 1218 * 1219 * CHICM = 0 (slave mode, 8 kHz frame rate) 1220 * IR = give immediate CHI status interrupt 1221 * EN = give CHI status interrupt upon change 1222 */ 1223 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0)); 1224 } else { 1225 /* Setup DBRI for CHI Master - generate clock, FS 1226 * 1227 * BPF = bits per 8 kHz frame 1228 * 12.288 MHz / CHICM_divisor = clock rate 1229 * FD = 1 - drive CHIFS on rising edge of CHICK 1230 */ 1231 int clockrate = bits_per_frame * 8; 1232 int divisor = 12288 / clockrate; 1233 1234 if (divisor > 255 || divisor * clockrate != 12288) 1235 printk(KERN_ERR "DBRI: illegal bits_per_frame " 1236 "in setup_chi\n"); 1237 1238 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD 1239 | D_CHI_BPF(bits_per_frame)); 1240 } 1241 1242 dbri->chi_bpf = bits_per_frame; 1243 1244 /* CHI Data Mode 1245 * 1246 * RCE = 0 - receive on falling edge of CHICK 1247 * XCE = 1 - transmit on rising edge of CHICK 1248 * XEN = 1 - enable transmitter 1249 * REN = 1 - enable receiver 1250 */ 1251 1252 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 1253 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN); 1254 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 1255 1256 dbri_cmdsend(dbri, cmd, 4); 1257} 1258 1259/* 1260**************************************************************************** 1261*********************** CS4215 audio codec management ********************** 1262**************************************************************************** 1263 1264In the standard SPARC audio configuration, the CS4215 codec is attached 1265to the DBRI via the CHI interface and few of the DBRI's PIO pins. 1266 1267 * Lock must not be held before calling it. 1268 1269*/ 1270static __devinit void cs4215_setup_pipes(struct snd_dbri *dbri) 1271{ 1272 unsigned long flags; 1273 1274 spin_lock_irqsave(&dbri->lock, flags); 1275 /* 1276 * Data mode: 1277 * Pipe 4: Send timeslots 1-4 (audio data) 1278 * Pipe 20: Send timeslots 5-8 (part of ctrl data) 1279 * Pipe 6: Receive timeslots 1-4 (audio data) 1280 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via 1281 * interrupt, and the rest of the data (slot 5 and 8) is 1282 * not relevant for us (only for doublechecking). 1283 * 1284 * Control mode: 1285 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only) 1286 * Pipe 18: Receive timeslot 1 (clb). 1287 * Pipe 19: Receive timeslot 7 (version). 1288 */ 1289 1290 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB); 1291 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); 1292 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB); 1293 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); 1294 1295 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); 1296 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); 1297 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); 1298 spin_unlock_irqrestore(&dbri->lock, flags); 1299 1300 dbri_cmdwait(dbri); 1301} 1302 1303static __devinit int cs4215_init_data(struct cs4215 *mm) 1304{ 1305 /* 1306 * No action, memory resetting only. 1307 * 1308 * Data Time Slot 5-8 1309 * Speaker,Line and Headphone enable. Gain set to the half. 1310 * Input is mike. 1311 */ 1312 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE; 1313 mm->data[1] = CS4215_RO(0x20) | CS4215_SE; 1314 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1; 1315 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf); 1316 1317 /* 1318 * Control Time Slot 1-4 1319 * 0: Default I/O voltage scale 1320 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 1321 * 2: Serial enable, CHI master, 128 bits per frame, clock 1 1322 * 3: Tests disabled 1323 */ 1324 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB; 1325 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 1326 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 1327 mm->ctrl[3] = 0; 1328 1329 mm->status = 0; 1330 mm->version = 0xff; 1331 mm->precision = 8; /* For ULAW */ 1332 mm->channels = 1; 1333 1334 return 0; 1335} 1336 1337static void cs4215_setdata(struct snd_dbri *dbri, int muted) 1338{ 1339 if (muted) { 1340 dbri->mm.data[0] |= 63; 1341 dbri->mm.data[1] |= 63; 1342 dbri->mm.data[2] &= ~15; 1343 dbri->mm.data[3] &= ~15; 1344 } else { 1345 /* Start by setting the playback attenuation. */ 1346 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY]; 1347 int left_gain = info->left_gain & 0x3f; 1348 int right_gain = info->right_gain & 0x3f; 1349 1350 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */ 1351 dbri->mm.data[1] &= ~0x3f; 1352 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain); 1353 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain); 1354 1355 /* Now set the recording gain. */ 1356 info = &dbri->stream_info[DBRI_REC]; 1357 left_gain = info->left_gain & 0xf; 1358 right_gain = info->right_gain & 0xf; 1359 dbri->mm.data[2] |= CS4215_LG(left_gain); 1360 dbri->mm.data[3] |= CS4215_RG(right_gain); 1361 } 1362 1363 xmit_fixed(dbri, 20, *(int *)dbri->mm.data); 1364} 1365 1366/* 1367 * Set the CS4215 to data mode. 1368 */ 1369static void cs4215_open(struct snd_dbri *dbri) 1370{ 1371 int data_width; 1372 u32 tmp; 1373 unsigned long flags; 1374 1375 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n", 1376 dbri->mm.channels, dbri->mm.precision); 1377 1378 /* Temporarily mute outputs, and wait 1/8000 sec (125 us) 1379 * to make sure this takes. This avoids clicking noises. 1380 */ 1381 1382 cs4215_setdata(dbri, 1); 1383 udelay(125); 1384 1385 /* 1386 * Data mode: 1387 * Pipe 4: Send timeslots 1-4 (audio data) 1388 * Pipe 20: Send timeslots 5-8 (part of ctrl data) 1389 * Pipe 6: Receive timeslots 1-4 (audio data) 1390 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via 1391 * interrupt, and the rest of the data (slot 5 and 8) is 1392 * not relevant for us (only for doublechecking). 1393 * 1394 * Just like in control mode, the time slots are all offset by eight 1395 * bits. The CS4215, it seems, observes TSIN (the delayed signal) 1396 * even if it's the CHI master. Don't ask me... 1397 */ 1398 spin_lock_irqsave(&dbri->lock, flags); 1399 tmp = sbus_readl(dbri->regs + REG0); 1400 tmp &= ~(D_C); /* Disable CHI */ 1401 sbus_writel(tmp, dbri->regs + REG0); 1402 1403 /* Switch CS4215 to data mode - set PIO3 to 1 */ 1404 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 | 1405 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2); 1406 1407 reset_chi(dbri, CHIslave, 128); 1408 1409 /* Note: this next doesn't work for 8-bit stereo, because the two 1410 * channels would be on timeslots 1 and 3, with 2 and 4 idle. 1411 * (See CS4215 datasheet Fig 15) 1412 * 1413 * DBRI non-contiguous mode would be required to make this work. 1414 */ 1415 data_width = dbri->mm.channels * dbri->mm.precision; 1416 1417 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset); 1418 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32); 1419 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset); 1420 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40); 1421 1422 tmp = sbus_readl(dbri->regs + REG0); 1423 tmp |= D_C; /* Enable CHI */ 1424 sbus_writel(tmp, dbri->regs + REG0); 1425 spin_unlock_irqrestore(&dbri->lock, flags); 1426 1427 cs4215_setdata(dbri, 0); 1428} 1429 1430/* 1431 * Send the control information (i.e. audio format) 1432 */ 1433static int cs4215_setctrl(struct snd_dbri *dbri) 1434{ 1435 int i, val; 1436 u32 tmp; 1437 unsigned long flags; 1438 1439 1440 /* Temporarily mute outputs, and wait 1/8000 sec (125 us) 1441 * to make sure this takes. This avoids clicking noises. 1442 */ 1443 cs4215_setdata(dbri, 1); 1444 udelay(125); 1445 1446 /* 1447 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait 1448 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec 1449 */ 1450 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2); 1451 sbus_writel(val, dbri->regs + REG2); 1452 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val); 1453 udelay(34); 1454 1455 /* In Control mode, the CS4215 is a slave device, so the DBRI must 1456 * operate as CHI master, supplying clocking and frame synchronization. 1457 * 1458 * In Data mode, however, the CS4215 must be CHI master to insure 1459 * that its data stream is synchronous with its codec. 1460 * 1461 * The upshot of all this? We start by putting the DBRI into master 1462 * mode, program the CS4215 in Control mode, then switch the CS4215 1463 * into Data mode and put the DBRI into slave mode. Various timing 1464 * requirements must be observed along the way. 1465 * 1466 * Oh, and one more thing, on a SPARCStation 20 (and maybe 1467 * others?), the addressing of the CS4215's time slots is 1468 * offset by eight bits, so we add eight to all the "cycle" 1469 * values in the Define Time Slot (DTS) commands. This is 1470 * done in hardware by a TI 248 that delays the DBRI->4215 1471 * frame sync signal by eight clock cycles. Anybody know why? 1472 */ 1473 spin_lock_irqsave(&dbri->lock, flags); 1474 tmp = sbus_readl(dbri->regs + REG0); 1475 tmp &= ~D_C; /* Disable CHI */ 1476 sbus_writel(tmp, dbri->regs + REG0); 1477 1478 reset_chi(dbri, CHImaster, 128); 1479 1480 /* 1481 * Control mode: 1482 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only) 1483 * Pipe 18: Receive timeslot 1 (clb). 1484 * Pipe 19: Receive timeslot 7 (version). 1485 */ 1486 1487 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset); 1488 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset); 1489 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48); 1490 spin_unlock_irqrestore(&dbri->lock, flags); 1491 1492 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */ 1493 dbri->mm.ctrl[0] &= ~CS4215_CLB; 1494 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); 1495 1496 spin_lock_irqsave(&dbri->lock, flags); 1497 tmp = sbus_readl(dbri->regs + REG0); 1498 tmp |= D_C; /* Enable CHI */ 1499 sbus_writel(tmp, dbri->regs + REG0); 1500 spin_unlock_irqrestore(&dbri->lock, flags); 1501 1502 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i) 1503 msleep_interruptible(1); 1504 1505 if (i == 0) { 1506 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n", 1507 dbri->mm.status); 1508 return -1; 1509 } 1510 1511 /* Disable changes to our copy of the version number, as we are about 1512 * to leave control mode. 1513 */ 1514 recv_fixed(dbri, 19, NULL); 1515 1516 /* Terminate CS4215 control mode - data sheet says 1517 * "Set CLB=1 and send two more frames of valid control info" 1518 */ 1519 dbri->mm.ctrl[0] |= CS4215_CLB; 1520 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); 1521 1522 /* Two frames of control info @ 8kHz frame rate = 250 us delay */ 1523 udelay(250); 1524 1525 cs4215_setdata(dbri, 0); 1526 1527 return 0; 1528} 1529 1530/* 1531 * Setup the codec with the sampling rate, audio format and number of 1532 * channels. 1533 * As part of the process we resend the settings for the data 1534 * timeslots as well. 1535 */ 1536static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate, 1537 snd_pcm_format_t format, unsigned int channels) 1538{ 1539 int freq_idx; 1540 int ret = 0; 1541 1542 /* Lookup index for this rate */ 1543 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) { 1544 if (CS4215_FREQ[freq_idx].freq == rate) 1545 break; 1546 } 1547 if (CS4215_FREQ[freq_idx].freq != rate) { 1548 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate); 1549 return -1; 1550 } 1551 1552 switch (format) { 1553 case SNDRV_PCM_FORMAT_MU_LAW: 1554 dbri->mm.ctrl[1] = CS4215_DFR_ULAW; 1555 dbri->mm.precision = 8; 1556 break; 1557 case SNDRV_PCM_FORMAT_A_LAW: 1558 dbri->mm.ctrl[1] = CS4215_DFR_ALAW; 1559 dbri->mm.precision = 8; 1560 break; 1561 case SNDRV_PCM_FORMAT_U8: 1562 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8; 1563 dbri->mm.precision = 8; 1564 break; 1565 case SNDRV_PCM_FORMAT_S16_BE: 1566 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16; 1567 dbri->mm.precision = 16; 1568 break; 1569 default: 1570 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format); 1571 return -1; 1572 } 1573 1574 /* Add rate parameters */ 1575 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval; 1576 dbri->mm.ctrl[2] = CS4215_XCLK | 1577 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal; 1578 1579 dbri->mm.channels = channels; 1580 if (channels == 2) 1581 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO; 1582 1583 ret = cs4215_setctrl(dbri); 1584 if (ret == 0) 1585 cs4215_open(dbri); /* set codec to data mode */ 1586 1587 return ret; 1588} 1589 1590/* 1591 * 1592 */ 1593static __devinit int cs4215_init(struct snd_dbri *dbri) 1594{ 1595 u32 reg2 = sbus_readl(dbri->regs + REG2); 1596 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2); 1597 1598 /* Look for the cs4215 chips */ 1599 if (reg2 & D_PIO2) { 1600 dprintk(D_MM, "Onboard CS4215 detected\n"); 1601 dbri->mm.onboard = 1; 1602 } 1603 if (reg2 & D_PIO0) { 1604 dprintk(D_MM, "Speakerbox detected\n"); 1605 dbri->mm.onboard = 0; 1606 1607 if (reg2 & D_PIO2) { 1608 printk(KERN_INFO "DBRI: Using speakerbox / " 1609 "ignoring onboard mmcodec.\n"); 1610 sbus_writel(D_ENPIO2, dbri->regs + REG2); 1611 } 1612 } 1613 1614 if (!(reg2 & (D_PIO0 | D_PIO2))) { 1615 printk(KERN_ERR "DBRI: no mmcodec found.\n"); 1616 return -EIO; 1617 } 1618 1619 cs4215_setup_pipes(dbri); 1620 cs4215_init_data(&dbri->mm); 1621 1622 /* Enable capture of the status & version timeslots. */ 1623 recv_fixed(dbri, 18, &dbri->mm.status); 1624 recv_fixed(dbri, 19, &dbri->mm.version); 1625 1626 dbri->mm.offset = dbri->mm.onboard ? 0 : 8; 1627 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) { 1628 dprintk(D_MM, "CS4215 failed probe at offset %d\n", 1629 dbri->mm.offset); 1630 return -EIO; 1631 } 1632 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset); 1633 1634 return 0; 1635} 1636 1637/* 1638**************************************************************************** 1639*************************** DBRI interrupt handler ************************* 1640**************************************************************************** 1641 1642The DBRI communicates with the CPU mainly via a circular interrupt 1643buffer. When an interrupt is signaled, the CPU walks through the 1644buffer and calls dbri_process_one_interrupt() for each interrupt word. 1645Complicated interrupts are handled by dedicated functions (which 1646appear first in this file). Any pending interrupts can be serviced by 1647calling dbri_process_interrupt_buffer(), which works even if the CPU's 1648interrupts are disabled. 1649 1650*/ 1651 1652/* xmit_descs() 1653 * 1654 * Starts transmitting the current TD's for recording/playing. 1655 * For playback, ALSA has filled the DMA memory with new data (we hope). 1656 */ 1657static void xmit_descs(struct snd_dbri *dbri) 1658{ 1659 struct dbri_streaminfo *info; 1660 s32 *cmd; 1661 unsigned long flags; 1662 int first_td; 1663 1664 if (dbri == NULL) 1665 return; /* Disabled */ 1666 1667 info = &dbri->stream_info[DBRI_REC]; 1668 spin_lock_irqsave(&dbri->lock, flags); 1669 1670 if (info->pipe >= 0) { 1671 first_td = dbri->pipes[info->pipe].first_desc; 1672 1673 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td); 1674 1675 /* Stream could be closed by the time we run. */ 1676 if (first_td >= 0) { 1677 cmd = dbri_cmdlock(dbri, 2); 1678 *(cmd++) = DBRI_CMD(D_SDP, 0, 1679 dbri->pipes[info->pipe].sdp 1680 | D_SDP_P | D_SDP_EVERY | D_SDP_C); 1681 *(cmd++) = dbri->dma_dvma + 1682 dbri_dma_off(desc, first_td); 1683 dbri_cmdsend(dbri, cmd, 2); 1684 1685 /* Reset our admin of the pipe. */ 1686 dbri->pipes[info->pipe].desc = first_td; 1687 } 1688 } 1689 1690 info = &dbri->stream_info[DBRI_PLAY]; 1691 1692 if (info->pipe >= 0) { 1693 first_td = dbri->pipes[info->pipe].first_desc; 1694 1695 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td); 1696 1697 /* Stream could be closed by the time we run. */ 1698 if (first_td >= 0) { 1699 cmd = dbri_cmdlock(dbri, 2); 1700 *(cmd++) = DBRI_CMD(D_SDP, 0, 1701 dbri->pipes[info->pipe].sdp 1702 | D_SDP_P | D_SDP_EVERY | D_SDP_C); 1703 *(cmd++) = dbri->dma_dvma + 1704 dbri_dma_off(desc, first_td); 1705 dbri_cmdsend(dbri, cmd, 2); 1706 1707 /* Reset our admin of the pipe. */ 1708 dbri->pipes[info->pipe].desc = first_td; 1709 } 1710 } 1711 1712 spin_unlock_irqrestore(&dbri->lock, flags); 1713} 1714 1715/* transmission_complete_intr() 1716 * 1717 * Called by main interrupt handler when DBRI signals transmission complete 1718 * on a pipe (interrupt triggered by the B bit in a transmit descriptor). 1719 * 1720 * Walks through the pipe's list of transmit buffer descriptors and marks 1721 * them as available. Stops when the first descriptor is found without 1722 * TBC (Transmit Buffer Complete) set, or we've run through them all. 1723 * 1724 * The DMA buffers are not released. They form a ring buffer and 1725 * they are filled by ALSA while others are transmitted by DMA. 1726 * 1727 */ 1728 1729static void transmission_complete_intr(struct snd_dbri *dbri, int pipe) 1730{ 1731 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY]; 1732 int td = dbri->pipes[pipe].desc; 1733 int status; 1734 1735 while (td >= 0) { 1736 if (td >= DBRI_NO_DESCS) { 1737 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe); 1738 return; 1739 } 1740 1741 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4); 1742 if (!(status & DBRI_TD_TBC)) 1743 break; 1744 1745 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status); 1746 1747 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */ 1748 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1); 1749 1750 td = dbri->next_desc[td]; 1751 dbri->pipes[pipe].desc = td; 1752 } 1753 1754 /* Notify ALSA */ 1755 spin_unlock(&dbri->lock); 1756 snd_pcm_period_elapsed(info->substream); 1757 spin_lock(&dbri->lock); 1758} 1759 1760static void reception_complete_intr(struct snd_dbri *dbri, int pipe) 1761{ 1762 struct dbri_streaminfo *info; 1763 int rd = dbri->pipes[pipe].desc; 1764 s32 status; 1765 1766 if (rd < 0 || rd >= DBRI_NO_DESCS) { 1767 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe); 1768 return; 1769 } 1770 1771 dbri->pipes[pipe].desc = dbri->next_desc[rd]; 1772 status = dbri->dma->desc[rd].word1; 1773 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */ 1774 1775 info = &dbri->stream_info[DBRI_REC]; 1776 info->offset += DBRI_RD_CNT(status); 1777 1778 1779 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n", 1780 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status)); 1781 1782 /* Notify ALSA */ 1783 spin_unlock(&dbri->lock); 1784 snd_pcm_period_elapsed(info->substream); 1785 spin_lock(&dbri->lock); 1786} 1787 1788static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x) 1789{ 1790 int val = D_INTR_GETVAL(x); 1791 int channel = D_INTR_GETCHAN(x); 1792 int command = D_INTR_GETCMD(x); 1793 int code = D_INTR_GETCODE(x); 1794#ifdef DBRI_DEBUG 1795 int rval = D_INTR_GETRVAL(x); 1796#endif 1797 1798 if (channel == D_INTR_CMD) { 1799 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n", 1800 cmds[command], val); 1801 } else { 1802 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n", 1803 channel, code, rval); 1804 } 1805 1806 switch (code) { 1807 case D_INTR_CMDI: 1808 if (command != D_WAIT) 1809 printk(KERN_ERR "DBRI: Command read interrupt\n"); 1810 break; 1811 case D_INTR_BRDY: 1812 reception_complete_intr(dbri, channel); 1813 break; 1814 case D_INTR_XCMP: 1815 case D_INTR_MINT: 1816 transmission_complete_intr(dbri, channel); 1817 break; 1818 case D_INTR_UNDR: 1819 /* UNDR - Transmission underrun 1820 * resend SDP command with clear pipe bit (C) set 1821 */ 1822 { 1823 printk(KERN_ERR "DBRI: Underrun error\n"); 1824 } 1825 break; 1826 case D_INTR_FXDT: 1827 /* FXDT - Fixed data change */ 1828 if (dbri->pipes[channel].sdp & D_SDP_MSB) 1829 val = reverse_bytes(val, dbri->pipes[channel].length); 1830 1831 if (dbri->pipes[channel].recv_fixed_ptr) 1832 *(dbri->pipes[channel].recv_fixed_ptr) = val; 1833 break; 1834 default: 1835 if (channel != D_INTR_CMD) 1836 printk(KERN_WARNING 1837 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x); 1838 } 1839} 1840 1841/* dbri_process_interrupt_buffer advances through the DBRI's interrupt 1842 * buffer until it finds a zero word (indicating nothing more to do 1843 * right now). Non-zero words require processing and are handed off 1844 * to dbri_process_one_interrupt AFTER advancing the pointer. 1845 */ 1846static void dbri_process_interrupt_buffer(struct snd_dbri *dbri) 1847{ 1848 s32 x; 1849 1850 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) { 1851 dbri->dma->intr[dbri->dbri_irqp] = 0; 1852 dbri->dbri_irqp++; 1853 if (dbri->dbri_irqp == DBRI_INT_BLK) 1854 dbri->dbri_irqp = 1; 1855 1856 dbri_process_one_interrupt(dbri, x); 1857 } 1858} 1859 1860static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id) 1861{ 1862 struct snd_dbri *dbri = dev_id; 1863 static int errcnt = 0; 1864 int x; 1865 1866 if (dbri == NULL) 1867 return IRQ_NONE; 1868 spin_lock(&dbri->lock); 1869 1870 /* 1871 * Read it, so the interrupt goes away. 1872 */ 1873 x = sbus_readl(dbri->regs + REG1); 1874 1875 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) { 1876 u32 tmp; 1877 1878 if (x & D_MRR) 1879 printk(KERN_ERR 1880 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n", 1881 x); 1882 if (x & D_MLE) 1883 printk(KERN_ERR 1884 "DBRI: Multiple Late Error on SBus reg1=0x%x\n", 1885 x); 1886 if (x & D_LBG) 1887 printk(KERN_ERR 1888 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x); 1889 if (x & D_MBE) 1890 printk(KERN_ERR 1891 "DBRI: Burst Error on SBus reg1=0x%x\n", x); 1892 1893 /* Some of these SBus errors cause the chip's SBus circuitry 1894 * to be disabled, so just re-enable and try to keep going. 1895 * 1896 * The only one I've seen is MRR, which will be triggered 1897 * if you let a transmit pipe underrun, then try to CDP it. 1898 * 1899 * If these things persist, we reset the chip. 1900 */ 1901 if ((++errcnt) % 10 == 0) { 1902 dprintk(D_INT, "Interrupt errors exceeded.\n"); 1903 dbri_reset(dbri); 1904 } else { 1905 tmp = sbus_readl(dbri->regs + REG0); 1906 tmp &= ~(D_D); 1907 sbus_writel(tmp, dbri->regs + REG0); 1908 } 1909 } 1910 1911 dbri_process_interrupt_buffer(dbri); 1912 1913 spin_unlock(&dbri->lock); 1914 1915 return IRQ_HANDLED; 1916} 1917 1918/**************************************************************************** 1919 PCM Interface 1920****************************************************************************/ 1921static struct snd_pcm_hardware snd_dbri_pcm_hw = { 1922 .info = SNDRV_PCM_INFO_MMAP | 1923 SNDRV_PCM_INFO_INTERLEAVED | 1924 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1925 SNDRV_PCM_INFO_MMAP_VALID | 1926 SNDRV_PCM_INFO_BATCH, 1927 .formats = SNDRV_PCM_FMTBIT_MU_LAW | 1928 SNDRV_PCM_FMTBIT_A_LAW | 1929 SNDRV_PCM_FMTBIT_U8 | 1930 SNDRV_PCM_FMTBIT_S16_BE, 1931 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512, 1932 .rate_min = 5512, 1933 .rate_max = 48000, 1934 .channels_min = 1, 1935 .channels_max = 2, 1936 .buffer_bytes_max = 64 * 1024, 1937 .period_bytes_min = 1, 1938 .period_bytes_max = DBRI_TD_MAXCNT, 1939 .periods_min = 1, 1940 .periods_max = 1024, 1941}; 1942 1943static int snd_hw_rule_format(struct snd_pcm_hw_params *params, 1944 struct snd_pcm_hw_rule *rule) 1945{ 1946 struct snd_interval *c = hw_param_interval(params, 1947 SNDRV_PCM_HW_PARAM_CHANNELS); 1948 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1949 struct snd_mask fmt; 1950 1951 snd_mask_any(&fmt); 1952 if (c->min > 1) { 1953 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE; 1954 return snd_mask_refine(f, &fmt); 1955 } 1956 return 0; 1957} 1958 1959static int snd_hw_rule_channels(struct snd_pcm_hw_params *params, 1960 struct snd_pcm_hw_rule *rule) 1961{ 1962 struct snd_interval *c = hw_param_interval(params, 1963 SNDRV_PCM_HW_PARAM_CHANNELS); 1964 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1965 struct snd_interval ch; 1966 1967 snd_interval_any(&ch); 1968 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) { 1969 ch.min = 1; 1970 ch.max = 1; 1971 ch.integer = 1; 1972 return snd_interval_refine(c, &ch); 1973 } 1974 return 0; 1975} 1976 1977static int snd_dbri_open(struct snd_pcm_substream *substream) 1978{ 1979 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 1980 struct snd_pcm_runtime *runtime = substream->runtime; 1981 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 1982 unsigned long flags; 1983 1984 dprintk(D_USR, "open audio output.\n"); 1985 runtime->hw = snd_dbri_pcm_hw; 1986 1987 spin_lock_irqsave(&dbri->lock, flags); 1988 info->substream = substream; 1989 info->offset = 0; 1990 info->dvma_buffer = 0; 1991 info->pipe = -1; 1992 spin_unlock_irqrestore(&dbri->lock, flags); 1993 1994 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1995 snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT, 1996 -1); 1997 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT, 1998 snd_hw_rule_channels, NULL, 1999 SNDRV_PCM_HW_PARAM_CHANNELS, 2000 -1); 2001 2002 cs4215_open(dbri); 2003 2004 return 0; 2005} 2006 2007static int snd_dbri_close(struct snd_pcm_substream *substream) 2008{ 2009 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2010 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2011 2012 dprintk(D_USR, "close audio output.\n"); 2013 info->substream = NULL; 2014 info->offset = 0; 2015 2016 return 0; 2017} 2018 2019static int snd_dbri_hw_params(struct snd_pcm_substream *substream, 2020 struct snd_pcm_hw_params *hw_params) 2021{ 2022 struct snd_pcm_runtime *runtime = substream->runtime; 2023 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2024 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2025 int direction; 2026 int ret; 2027 2028 /* set sampling rate, audio format and number of channels */ 2029 ret = cs4215_prepare(dbri, params_rate(hw_params), 2030 params_format(hw_params), 2031 params_channels(hw_params)); 2032 if (ret != 0) 2033 return ret; 2034 2035 if ((ret = snd_pcm_lib_malloc_pages(substream, 2036 params_buffer_bytes(hw_params))) < 0) { 2037 printk(KERN_ERR "malloc_pages failed with %d\n", ret); 2038 return ret; 2039 } 2040 2041 /* hw_params can get called multiple times. Only map the DMA once. 2042 */ 2043 if (info->dvma_buffer == 0) { 2044 if (DBRI_STREAMNO(substream) == DBRI_PLAY) 2045 direction = DMA_TO_DEVICE; 2046 else 2047 direction = DMA_FROM_DEVICE; 2048 2049 info->dvma_buffer = 2050 dma_map_single(&dbri->op->dev, 2051 runtime->dma_area, 2052 params_buffer_bytes(hw_params), 2053 direction); 2054 } 2055 2056 direction = params_buffer_bytes(hw_params); 2057 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n", 2058 direction, info->dvma_buffer); 2059 return 0; 2060} 2061 2062static int snd_dbri_hw_free(struct snd_pcm_substream *substream) 2063{ 2064 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2065 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2066 int direction; 2067 2068 dprintk(D_USR, "hw_free.\n"); 2069 2070 /* hw_free can get called multiple times. Only unmap the DMA once. 2071 */ 2072 if (info->dvma_buffer) { 2073 if (DBRI_STREAMNO(substream) == DBRI_PLAY) 2074 direction = DMA_TO_DEVICE; 2075 else 2076 direction = DMA_FROM_DEVICE; 2077 2078 dma_unmap_single(&dbri->op->dev, info->dvma_buffer, 2079 substream->runtime->buffer_size, direction); 2080 info->dvma_buffer = 0; 2081 } 2082 if (info->pipe != -1) { 2083 reset_pipe(dbri, info->pipe); 2084 info->pipe = -1; 2085 } 2086 2087 return snd_pcm_lib_free_pages(substream); 2088} 2089 2090static int snd_dbri_prepare(struct snd_pcm_substream *substream) 2091{ 2092 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2093 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2094 int ret; 2095 2096 info->size = snd_pcm_lib_buffer_bytes(substream); 2097 if (DBRI_STREAMNO(substream) == DBRI_PLAY) 2098 info->pipe = 4; /* Send pipe */ 2099 else 2100 info->pipe = 6; /* Receive pipe */ 2101 2102 spin_lock_irq(&dbri->lock); 2103 info->offset = 0; 2104 2105 /* Setup the all the transmit/receive descriptors to cover the 2106 * whole DMA buffer. 2107 */ 2108 ret = setup_descs(dbri, DBRI_STREAMNO(substream), 2109 snd_pcm_lib_period_bytes(substream)); 2110 2111 spin_unlock_irq(&dbri->lock); 2112 2113 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size); 2114 return ret; 2115} 2116 2117static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd) 2118{ 2119 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2120 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2121 int ret = 0; 2122 2123 switch (cmd) { 2124 case SNDRV_PCM_TRIGGER_START: 2125 dprintk(D_USR, "start audio, period is %d bytes\n", 2126 (int)snd_pcm_lib_period_bytes(substream)); 2127 /* Re-submit the TDs. */ 2128 xmit_descs(dbri); 2129 break; 2130 case SNDRV_PCM_TRIGGER_STOP: 2131 dprintk(D_USR, "stop audio.\n"); 2132 reset_pipe(dbri, info->pipe); 2133 break; 2134 default: 2135 ret = -EINVAL; 2136 } 2137 2138 return ret; 2139} 2140 2141static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream) 2142{ 2143 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2144 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2145 snd_pcm_uframes_t ret; 2146 2147 ret = bytes_to_frames(substream->runtime, info->offset) 2148 % substream->runtime->buffer_size; 2149 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n", 2150 ret, substream->runtime->buffer_size); 2151 return ret; 2152} 2153 2154static struct snd_pcm_ops snd_dbri_ops = { 2155 .open = snd_dbri_open, 2156 .close = snd_dbri_close, 2157 .ioctl = snd_pcm_lib_ioctl, 2158 .hw_params = snd_dbri_hw_params, 2159 .hw_free = snd_dbri_hw_free, 2160 .prepare = snd_dbri_prepare, 2161 .trigger = snd_dbri_trigger, 2162 .pointer = snd_dbri_pointer, 2163}; 2164 2165static int __devinit snd_dbri_pcm(struct snd_card *card) 2166{ 2167 struct snd_pcm *pcm; 2168 int err; 2169 2170 if ((err = snd_pcm_new(card, 2171 /* ID */ "sun_dbri", 2172 /* device */ 0, 2173 /* playback count */ 1, 2174 /* capture count */ 1, &pcm)) < 0) 2175 return err; 2176 2177 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops); 2178 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops); 2179 2180 pcm->private_data = card->private_data; 2181 pcm->info_flags = 0; 2182 strcpy(pcm->name, card->shortname); 2183 2184 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm, 2185 SNDRV_DMA_TYPE_CONTINUOUS, 2186 snd_dma_continuous_data(GFP_KERNEL), 2187 64 * 1024, 64 * 1024)) < 0) 2188 return err; 2189 2190 return 0; 2191} 2192 2193/***************************************************************************** 2194 Mixer interface 2195*****************************************************************************/ 2196 2197static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol, 2198 struct snd_ctl_elem_info *uinfo) 2199{ 2200 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2201 uinfo->count = 2; 2202 uinfo->value.integer.min = 0; 2203 if (kcontrol->private_value == DBRI_PLAY) 2204 uinfo->value.integer.max = DBRI_MAX_VOLUME; 2205 else 2206 uinfo->value.integer.max = DBRI_MAX_GAIN; 2207 return 0; 2208} 2209 2210static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol, 2211 struct snd_ctl_elem_value *ucontrol) 2212{ 2213 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2214 struct dbri_streaminfo *info; 2215 2216 if (snd_BUG_ON(!dbri)) 2217 return -EINVAL; 2218 info = &dbri->stream_info[kcontrol->private_value]; 2219 2220 ucontrol->value.integer.value[0] = info->left_gain; 2221 ucontrol->value.integer.value[1] = info->right_gain; 2222 return 0; 2223} 2224 2225static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol, 2226 struct snd_ctl_elem_value *ucontrol) 2227{ 2228 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2229 struct dbri_streaminfo *info = 2230 &dbri->stream_info[kcontrol->private_value]; 2231 unsigned int vol[2]; 2232 int changed = 0; 2233 2234 vol[0] = ucontrol->value.integer.value[0]; 2235 vol[1] = ucontrol->value.integer.value[1]; 2236 if (kcontrol->private_value == DBRI_PLAY) { 2237 if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME) 2238 return -EINVAL; 2239 } else { 2240 if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN) 2241 return -EINVAL; 2242 } 2243 2244 if (info->left_gain != vol[0]) { 2245 info->left_gain = vol[0]; 2246 changed = 1; 2247 } 2248 if (info->right_gain != vol[1]) { 2249 info->right_gain = vol[1]; 2250 changed = 1; 2251 } 2252 if (changed) { 2253 /* First mute outputs, and wait 1/8000 sec (125 us) 2254 * to make sure this takes. This avoids clicking noises. 2255 */ 2256 cs4215_setdata(dbri, 1); 2257 udelay(125); 2258 cs4215_setdata(dbri, 0); 2259 } 2260 return changed; 2261} 2262 2263static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol, 2264 struct snd_ctl_elem_info *uinfo) 2265{ 2266 int mask = (kcontrol->private_value >> 16) & 0xff; 2267 2268 uinfo->type = (mask == 1) ? 2269 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 2270 uinfo->count = 1; 2271 uinfo->value.integer.min = 0; 2272 uinfo->value.integer.max = mask; 2273 return 0; 2274} 2275 2276static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol, 2277 struct snd_ctl_elem_value *ucontrol) 2278{ 2279 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2280 int elem = kcontrol->private_value & 0xff; 2281 int shift = (kcontrol->private_value >> 8) & 0xff; 2282 int mask = (kcontrol->private_value >> 16) & 0xff; 2283 int invert = (kcontrol->private_value >> 24) & 1; 2284 2285 if (snd_BUG_ON(!dbri)) 2286 return -EINVAL; 2287 2288 if (elem < 4) 2289 ucontrol->value.integer.value[0] = 2290 (dbri->mm.data[elem] >> shift) & mask; 2291 else 2292 ucontrol->value.integer.value[0] = 2293 (dbri->mm.ctrl[elem - 4] >> shift) & mask; 2294 2295 if (invert == 1) 2296 ucontrol->value.integer.value[0] = 2297 mask - ucontrol->value.integer.value[0]; 2298 return 0; 2299} 2300 2301static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol, 2302 struct snd_ctl_elem_value *ucontrol) 2303{ 2304 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2305 int elem = kcontrol->private_value & 0xff; 2306 int shift = (kcontrol->private_value >> 8) & 0xff; 2307 int mask = (kcontrol->private_value >> 16) & 0xff; 2308 int invert = (kcontrol->private_value >> 24) & 1; 2309 int changed = 0; 2310 unsigned short val; 2311 2312 if (snd_BUG_ON(!dbri)) 2313 return -EINVAL; 2314 2315 val = (ucontrol->value.integer.value[0] & mask); 2316 if (invert == 1) 2317 val = mask - val; 2318 val <<= shift; 2319 2320 if (elem < 4) { 2321 dbri->mm.data[elem] = (dbri->mm.data[elem] & 2322 ~(mask << shift)) | val; 2323 changed = (val != dbri->mm.data[elem]); 2324 } else { 2325 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] & 2326 ~(mask << shift)) | val; 2327 changed = (val != dbri->mm.ctrl[elem - 4]); 2328 } 2329 2330 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, " 2331 "mixer-value=%ld, mm-value=0x%x\n", 2332 mask, changed, ucontrol->value.integer.value[0], 2333 dbri->mm.data[elem & 3]); 2334 2335 if (changed) { 2336 /* First mute outputs, and wait 1/8000 sec (125 us) 2337 * to make sure this takes. This avoids clicking noises. 2338 */ 2339 cs4215_setdata(dbri, 1); 2340 udelay(125); 2341 cs4215_setdata(dbri, 0); 2342 } 2343 return changed; 2344} 2345 2346/* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control 2347 timeslots. Shift is the bit offset in the timeslot, mask defines the 2348 number of bits. invert is a boolean for use with attenuation. 2349 */ 2350#define CS4215_SINGLE(xname, entry, shift, mask, invert) \ 2351{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 2352 .info = snd_cs4215_info_single, \ 2353 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \ 2354 .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \ 2355 ((invert) << 24) }, 2356 2357static struct snd_kcontrol_new dbri_controls[] __devinitdata = { 2358 { 2359 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2360 .name = "Playback Volume", 2361 .info = snd_cs4215_info_volume, 2362 .get = snd_cs4215_get_volume, 2363 .put = snd_cs4215_put_volume, 2364 .private_value = DBRI_PLAY, 2365 }, 2366 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0) 2367 CS4215_SINGLE("Line out switch", 0, 6, 1, 0) 2368 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0) 2369 { 2370 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2371 .name = "Capture Volume", 2372 .info = snd_cs4215_info_volume, 2373 .get = snd_cs4215_get_volume, 2374 .put = snd_cs4215_put_volume, 2375 .private_value = DBRI_REC, 2376 }, 2377 CS4215_SINGLE("Line in switch", 2, 4, 1, 0) 2378 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0) 2379 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1) 2380 CS4215_SINGLE("Mic boost", 4, 4, 1, 1) 2381}; 2382 2383static int __devinit snd_dbri_mixer(struct snd_card *card) 2384{ 2385 int idx, err; 2386 struct snd_dbri *dbri; 2387 2388 if (snd_BUG_ON(!card || !card->private_data)) 2389 return -EINVAL; 2390 dbri = card->private_data; 2391 2392 strcpy(card->mixername, card->shortname); 2393 2394 for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) { 2395 err = snd_ctl_add(card, 2396 snd_ctl_new1(&dbri_controls[idx], dbri)); 2397 if (err < 0) 2398 return err; 2399 } 2400 2401 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) { 2402 dbri->stream_info[idx].left_gain = 0; 2403 dbri->stream_info[idx].right_gain = 0; 2404 } 2405 2406 return 0; 2407} 2408 2409/**************************************************************************** 2410 /proc interface 2411****************************************************************************/ 2412static void dbri_regs_read(struct snd_info_entry *entry, 2413 struct snd_info_buffer *buffer) 2414{ 2415 struct snd_dbri *dbri = entry->private_data; 2416 2417 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0)); 2418 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2)); 2419 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8)); 2420 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9)); 2421} 2422 2423#ifdef DBRI_DEBUG 2424static void dbri_debug_read(struct snd_info_entry *entry, 2425 struct snd_info_buffer *buffer) 2426{ 2427 struct snd_dbri *dbri = entry->private_data; 2428 int pipe; 2429 snd_iprintf(buffer, "debug=%d\n", dbri_debug); 2430 2431 for (pipe = 0; pipe < 32; pipe++) { 2432 if (pipe_active(dbri, pipe)) { 2433 struct dbri_pipe *pptr = &dbri->pipes[pipe]; 2434 snd_iprintf(buffer, 2435 "Pipe %d: %s SDP=0x%x desc=%d, " 2436 "len=%d next %d\n", 2437 pipe, 2438 (pptr->sdp & D_SDP_TO_SER) ? "output" : 2439 "input", 2440 pptr->sdp, pptr->desc, 2441 pptr->length, pptr->nextpipe); 2442 } 2443 } 2444} 2445#endif 2446 2447static void __devinit snd_dbri_proc(struct snd_card *card) 2448{ 2449 struct snd_dbri *dbri = card->private_data; 2450 struct snd_info_entry *entry; 2451 2452 if (!snd_card_proc_new(card, "regs", &entry)) 2453 snd_info_set_text_ops(entry, dbri, dbri_regs_read); 2454 2455#ifdef DBRI_DEBUG 2456 if (!snd_card_proc_new(card, "debug", &entry)) { 2457 snd_info_set_text_ops(entry, dbri, dbri_debug_read); 2458 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */ 2459 } 2460#endif 2461} 2462 2463/* 2464**************************************************************************** 2465**************************** Initialization ******************************** 2466**************************************************************************** 2467*/ 2468static void snd_dbri_free(struct snd_dbri *dbri); 2469 2470static int __devinit snd_dbri_create(struct snd_card *card, 2471 struct platform_device *op, 2472 int irq, int dev) 2473{ 2474 struct snd_dbri *dbri = card->private_data; 2475 int err; 2476 2477 spin_lock_init(&dbri->lock); 2478 dbri->op = op; 2479 dbri->irq = irq; 2480 2481 dbri->dma = dma_alloc_coherent(&op->dev, 2482 sizeof(struct dbri_dma), 2483 &dbri->dma_dvma, GFP_ATOMIC); 2484 if (!dbri->dma) 2485 return -ENOMEM; 2486 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma)); 2487 2488 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n", 2489 dbri->dma, dbri->dma_dvma); 2490 2491 /* Map the registers into memory. */ 2492 dbri->regs_size = resource_size(&op->resource[0]); 2493 dbri->regs = of_ioremap(&op->resource[0], 0, 2494 dbri->regs_size, "DBRI Registers"); 2495 if (!dbri->regs) { 2496 printk(KERN_ERR "DBRI: could not allocate registers\n"); 2497 dma_free_coherent(&op->dev, sizeof(struct dbri_dma), 2498 (void *)dbri->dma, dbri->dma_dvma); 2499 return -EIO; 2500 } 2501 2502 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED, 2503 "DBRI audio", dbri); 2504 if (err) { 2505 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq); 2506 of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size); 2507 dma_free_coherent(&op->dev, sizeof(struct dbri_dma), 2508 (void *)dbri->dma, dbri->dma_dvma); 2509 return err; 2510 } 2511 2512 /* Do low level initialization of the DBRI and CS4215 chips */ 2513 dbri_initialize(dbri); 2514 err = cs4215_init(dbri); 2515 if (err) { 2516 snd_dbri_free(dbri); 2517 return err; 2518 } 2519 2520 return 0; 2521} 2522 2523static void snd_dbri_free(struct snd_dbri *dbri) 2524{ 2525 dprintk(D_GEN, "snd_dbri_free\n"); 2526 dbri_reset(dbri); 2527 2528 if (dbri->irq) 2529 free_irq(dbri->irq, dbri); 2530 2531 if (dbri->regs) 2532 of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size); 2533 2534 if (dbri->dma) 2535 dma_free_coherent(&dbri->op->dev, 2536 sizeof(struct dbri_dma), 2537 (void *)dbri->dma, dbri->dma_dvma); 2538} 2539 2540static int __devinit dbri_probe(struct platform_device *op, const struct of_device_id *match) 2541{ 2542 struct snd_dbri *dbri; 2543 struct resource *rp; 2544 struct snd_card *card; 2545 static int dev = 0; 2546 int irq; 2547 int err; 2548 2549 if (dev >= SNDRV_CARDS) 2550 return -ENODEV; 2551 if (!enable[dev]) { 2552 dev++; 2553 return -ENOENT; 2554 } 2555 2556 irq = op->archdata.irqs[0]; 2557 if (irq <= 0) { 2558 printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev); 2559 return -ENODEV; 2560 } 2561 2562 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 2563 sizeof(struct snd_dbri), &card); 2564 if (err < 0) 2565 return err; 2566 2567 strcpy(card->driver, "DBRI"); 2568 strcpy(card->shortname, "Sun DBRI"); 2569 rp = &op->resource[0]; 2570 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d", 2571 card->shortname, 2572 rp->flags & 0xffL, (unsigned long long)rp->start, irq); 2573 2574 err = snd_dbri_create(card, op, irq, dev); 2575 if (err < 0) { 2576 snd_card_free(card); 2577 return err; 2578 } 2579 2580 dbri = card->private_data; 2581 err = snd_dbri_pcm(card); 2582 if (err < 0) 2583 goto _err; 2584 2585 err = snd_dbri_mixer(card); 2586 if (err < 0) 2587 goto _err; 2588 2589 /* /proc file handling */ 2590 snd_dbri_proc(card); 2591 dev_set_drvdata(&op->dev, card); 2592 2593 err = snd_card_register(card); 2594 if (err < 0) 2595 goto _err; 2596 2597 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n", 2598 dev, dbri->regs, 2599 dbri->irq, op->dev.of_node->name[9], dbri->mm.version); 2600 dev++; 2601 2602 return 0; 2603 2604_err: 2605 snd_dbri_free(dbri); 2606 snd_card_free(card); 2607 return err; 2608} 2609 2610static int __devexit dbri_remove(struct platform_device *op) 2611{ 2612 struct snd_card *card = dev_get_drvdata(&op->dev); 2613 2614 snd_dbri_free(card->private_data); 2615 snd_card_free(card); 2616 2617 dev_set_drvdata(&op->dev, NULL); 2618 2619 return 0; 2620} 2621 2622static const struct of_device_id dbri_match[] = { 2623 { 2624 .name = "SUNW,DBRIe", 2625 }, 2626 { 2627 .name = "SUNW,DBRIf", 2628 }, 2629 {}, 2630}; 2631 2632MODULE_DEVICE_TABLE(of, dbri_match); 2633 2634static struct of_platform_driver dbri_sbus_driver = { 2635 .driver = { 2636 .name = "dbri", 2637 .owner = THIS_MODULE, 2638 .of_match_table = dbri_match, 2639 }, 2640 .probe = dbri_probe, 2641 .remove = __devexit_p(dbri_remove), 2642}; 2643 2644/* Probe for the dbri chip and then attach the driver. */ 2645static int __init dbri_init(void) 2646{ 2647 return of_register_platform_driver(&dbri_sbus_driver); 2648} 2649 2650static void __exit dbri_exit(void) 2651{ 2652 of_unregister_platform_driver(&dbri_sbus_driver); 2653} 2654 2655module_init(dbri_init); 2656module_exit(dbri_exit); 2657