1/* 2 * Fifo-attached Serial Interface (FSI) support for SH7724 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 6 * 7 * Based on ssi.c 8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15#include <linux/delay.h> 16#include <linux/pm_runtime.h> 17#include <linux/io.h> 18#include <linux/slab.h> 19#include <sound/soc.h> 20#include <sound/sh_fsi.h> 21 22#define DO_FMT 0x0000 23#define DOFF_CTL 0x0004 24#define DOFF_ST 0x0008 25#define DI_FMT 0x000C 26#define DIFF_CTL 0x0010 27#define DIFF_ST 0x0014 28#define CKG1 0x0018 29#define CKG2 0x001C 30#define DIDT 0x0020 31#define DODT 0x0024 32#define MUTE_ST 0x0028 33#define OUT_SEL 0x0030 34#define REG_END OUT_SEL 35 36#define A_MST_CTLR 0x0180 37#define B_MST_CTLR 0x01A0 38#define CPU_INT_ST 0x01F4 39#define CPU_IEMSK 0x01F8 40#define CPU_IMSK 0x01FC 41#define INT_ST 0x0200 42#define IEMSK 0x0204 43#define IMSK 0x0208 44#define MUTE 0x020C 45#define CLK_RST 0x0210 46#define SOFT_RST 0x0214 47#define FIFO_SZ 0x0218 48#define MREG_START A_MST_CTLR 49#define MREG_END FIFO_SZ 50 51/* DO_FMT */ 52/* DI_FMT */ 53#define CR_MONO (0x0 << 4) 54#define CR_MONO_D (0x1 << 4) 55#define CR_PCM (0x2 << 4) 56#define CR_I2S (0x3 << 4) 57#define CR_TDM (0x4 << 4) 58#define CR_TDM_D (0x5 << 4) 59#define CR_SPDIF 0x00100120 60 61/* DOFF_CTL */ 62/* DIFF_CTL */ 63#define IRQ_HALF 0x00100000 64#define FIFO_CLR 0x00000001 65 66/* DOFF_ST */ 67#define ERR_OVER 0x00000010 68#define ERR_UNDER 0x00000001 69#define ST_ERR (ERR_OVER | ERR_UNDER) 70 71/* CKG1 */ 72#define ACKMD_MASK 0x00007000 73#define BPFMD_MASK 0x00000700 74 75/* A/B MST_CTLR */ 76#define BP (1 << 4) /* Fix the signal of Biphase output */ 77#define SE (1 << 0) /* Fix the master clock */ 78 79/* CLK_RST */ 80#define B_CLK 0x00000010 81#define A_CLK 0x00000001 82 83/* INT_ST */ 84#define INT_B_IN (1 << 12) 85#define INT_B_OUT (1 << 8) 86#define INT_A_IN (1 << 4) 87#define INT_A_OUT (1 << 0) 88 89/* SOFT_RST */ 90#define PBSR (1 << 12) /* Port B Software Reset */ 91#define PASR (1 << 8) /* Port A Software Reset */ 92#define IR (1 << 4) /* Interrupt Reset */ 93#define FSISR (1 << 0) /* Software Reset */ 94 95/* FIFO_SZ */ 96#define OUT_SZ_MASK 0x7 97#define BO_SZ_SHIFT 8 98#define AO_SZ_SHIFT 0 99 100#define FSI_RATES SNDRV_PCM_RATE_8000_96000 101 102#define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) 103 104/************************************************************************ 105 106 107 struct 108 109 110************************************************************************/ 111struct fsi_priv { 112 void __iomem *base; 113 struct snd_pcm_substream *substream; 114 struct fsi_master *master; 115 116 int fifo_max; 117 int chan; 118 119 int byte_offset; 120 int period_len; 121 int buffer_len; 122 int periods; 123 124 u32 mst_ctrl; 125}; 126 127struct fsi_core { 128 int ver; 129 130 u32 int_st; 131 u32 iemsk; 132 u32 imsk; 133}; 134 135struct fsi_master { 136 void __iomem *base; 137 int irq; 138 struct fsi_priv fsia; 139 struct fsi_priv fsib; 140 struct fsi_core *core; 141 struct sh_fsi_platform_info *info; 142 spinlock_t lock; 143}; 144 145/************************************************************************ 146 147 148 basic read write function 149 150 151************************************************************************/ 152static void __fsi_reg_write(u32 reg, u32 data) 153{ 154 /* valid data area is 24bit */ 155 data &= 0x00ffffff; 156 157 __raw_writel(data, reg); 158} 159 160static u32 __fsi_reg_read(u32 reg) 161{ 162 return __raw_readl(reg); 163} 164 165static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data) 166{ 167 u32 val = __fsi_reg_read(reg); 168 169 val &= ~mask; 170 val |= data & mask; 171 172 __fsi_reg_write(reg, val); 173} 174 175static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data) 176{ 177 if (reg > REG_END) { 178 pr_err("fsi: register access err (%s)\n", __func__); 179 return; 180 } 181 182 __fsi_reg_write((u32)(fsi->base + reg), data); 183} 184 185static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg) 186{ 187 if (reg > REG_END) { 188 pr_err("fsi: register access err (%s)\n", __func__); 189 return 0; 190 } 191 192 return __fsi_reg_read((u32)(fsi->base + reg)); 193} 194 195static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data) 196{ 197 if (reg > REG_END) { 198 pr_err("fsi: register access err (%s)\n", __func__); 199 return; 200 } 201 202 __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data); 203} 204 205static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data) 206{ 207 unsigned long flags; 208 209 if ((reg < MREG_START) || 210 (reg > MREG_END)) { 211 pr_err("fsi: register access err (%s)\n", __func__); 212 return; 213 } 214 215 spin_lock_irqsave(&master->lock, flags); 216 __fsi_reg_write((u32)(master->base + reg), data); 217 spin_unlock_irqrestore(&master->lock, flags); 218} 219 220static u32 fsi_master_read(struct fsi_master *master, u32 reg) 221{ 222 u32 ret; 223 unsigned long flags; 224 225 if ((reg < MREG_START) || 226 (reg > MREG_END)) { 227 pr_err("fsi: register access err (%s)\n", __func__); 228 return 0; 229 } 230 231 spin_lock_irqsave(&master->lock, flags); 232 ret = __fsi_reg_read((u32)(master->base + reg)); 233 spin_unlock_irqrestore(&master->lock, flags); 234 235 return ret; 236} 237 238static void fsi_master_mask_set(struct fsi_master *master, 239 u32 reg, u32 mask, u32 data) 240{ 241 unsigned long flags; 242 243 if ((reg < MREG_START) || 244 (reg > MREG_END)) { 245 pr_err("fsi: register access err (%s)\n", __func__); 246 return; 247 } 248 249 spin_lock_irqsave(&master->lock, flags); 250 __fsi_reg_mask_set((u32)(master->base + reg), mask, data); 251 spin_unlock_irqrestore(&master->lock, flags); 252} 253 254/************************************************************************ 255 256 257 basic function 258 259 260************************************************************************/ 261static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) 262{ 263 return fsi->master; 264} 265 266static int fsi_is_port_a(struct fsi_priv *fsi) 267{ 268 return fsi->master->base == fsi->base; 269} 270 271static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) 272{ 273 struct snd_soc_pcm_runtime *rtd = substream->private_data; 274 struct snd_soc_dai_link *machine = rtd->dai; 275 276 return machine->cpu_dai; 277} 278 279static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) 280{ 281 struct snd_soc_dai *dai = fsi_get_dai(substream); 282 283 return dai->private_data; 284} 285 286static u32 fsi_get_info_flags(struct fsi_priv *fsi) 287{ 288 int is_porta = fsi_is_port_a(fsi); 289 struct fsi_master *master = fsi_get_master(fsi); 290 291 return is_porta ? master->info->porta_flags : 292 master->info->portb_flags; 293} 294 295static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play) 296{ 297 u32 mode; 298 u32 flags = fsi_get_info_flags(fsi); 299 300 mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE; 301 302 /* return 303 * 1 : master mode 304 * 0 : slave mode 305 */ 306 307 return (mode & flags) != mode; 308} 309 310static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play) 311{ 312 int is_porta = fsi_is_port_a(fsi); 313 u32 data; 314 315 if (is_porta) 316 data = is_play ? (1 << 0) : (1 << 4); 317 else 318 data = is_play ? (1 << 8) : (1 << 12); 319 320 return data; 321} 322 323static void fsi_stream_push(struct fsi_priv *fsi, 324 struct snd_pcm_substream *substream, 325 u32 buffer_len, 326 u32 period_len) 327{ 328 fsi->substream = substream; 329 fsi->buffer_len = buffer_len; 330 fsi->period_len = period_len; 331 fsi->byte_offset = 0; 332 fsi->periods = 0; 333} 334 335static void fsi_stream_pop(struct fsi_priv *fsi) 336{ 337 fsi->substream = NULL; 338 fsi->buffer_len = 0; 339 fsi->period_len = 0; 340 fsi->byte_offset = 0; 341 fsi->periods = 0; 342} 343 344static int fsi_get_fifo_residue(struct fsi_priv *fsi, int is_play) 345{ 346 u32 status; 347 u32 reg = is_play ? DOFF_ST : DIFF_ST; 348 int residue; 349 350 status = fsi_reg_read(fsi, reg); 351 residue = 0x1ff & (status >> 8); 352 residue *= fsi->chan; 353 354 return residue; 355} 356 357/************************************************************************ 358 359 360 irq function 361 362 363************************************************************************/ 364static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) 365{ 366 u32 data = fsi_port_ab_io_bit(fsi, is_play); 367 struct fsi_master *master = fsi_get_master(fsi); 368 369 fsi_master_mask_set(master, master->core->imsk, data, data); 370 fsi_master_mask_set(master, master->core->iemsk, data, data); 371} 372 373static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) 374{ 375 u32 data = fsi_port_ab_io_bit(fsi, is_play); 376 struct fsi_master *master = fsi_get_master(fsi); 377 378 fsi_master_mask_set(master, master->core->imsk, data, 0); 379 fsi_master_mask_set(master, master->core->iemsk, data, 0); 380} 381 382static u32 fsi_irq_get_status(struct fsi_master *master) 383{ 384 return fsi_master_read(master, master->core->int_st); 385} 386 387static void fsi_irq_clear_all_status(struct fsi_master *master) 388{ 389 fsi_master_write(master, master->core->int_st, 0); 390} 391 392static void fsi_irq_clear_status(struct fsi_priv *fsi) 393{ 394 u32 data = 0; 395 struct fsi_master *master = fsi_get_master(fsi); 396 397 data |= fsi_port_ab_io_bit(fsi, 0); 398 data |= fsi_port_ab_io_bit(fsi, 1); 399 400 /* clear interrupt factor */ 401 fsi_master_mask_set(master, master->core->int_st, data, 0); 402} 403 404/************************************************************************ 405 406 407 SPDIF master clock function 408 409These functions are used later FSI2 410************************************************************************/ 411static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) 412{ 413 struct fsi_master *master = fsi_get_master(fsi); 414 u32 val = BP | SE; 415 416 if (master->core->ver < 2) { 417 pr_err("fsi: register access err (%s)\n", __func__); 418 return; 419 } 420 421 if (enable) 422 fsi_master_mask_set(master, fsi->mst_ctrl, val, val); 423 else 424 fsi_master_mask_set(master, fsi->mst_ctrl, val, 0); 425} 426 427/************************************************************************ 428 429 430 ctrl function 431 432 433************************************************************************/ 434static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable) 435{ 436 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4); 437 struct fsi_master *master = fsi_get_master(fsi); 438 439 if (enable) 440 fsi_master_mask_set(master, CLK_RST, val, val); 441 else 442 fsi_master_mask_set(master, CLK_RST, val, 0); 443} 444 445static void fsi_fifo_init(struct fsi_priv *fsi, 446 int is_play, 447 struct snd_soc_dai *dai) 448{ 449 struct fsi_master *master = fsi_get_master(fsi); 450 u32 ctrl, shift, i; 451 452 /* get on-chip RAM capacity */ 453 shift = fsi_master_read(master, FIFO_SZ); 454 shift >>= fsi_is_port_a(fsi) ? AO_SZ_SHIFT : BO_SZ_SHIFT; 455 shift &= OUT_SZ_MASK; 456 fsi->fifo_max = 256 << shift; 457 dev_dbg(dai->dev, "fifo = %d words\n", fsi->fifo_max); 458 459 /* 460 * The maximum number of sample data varies depending 461 * on the number of channels selected for the format. 462 * 463 * FIFOs are used in 4-channel units in 3-channel mode 464 * and in 8-channel units in 5- to 7-channel mode 465 * meaning that more FIFOs than the required size of DPRAM 466 * are used. 467 * 468 * ex) if 256 words of DP-RAM is connected 469 * 1 channel: 256 (256 x 1 = 256) 470 * 2 channels: 128 (128 x 2 = 256) 471 * 3 channels: 64 ( 64 x 3 = 192) 472 * 4 channels: 64 ( 64 x 4 = 256) 473 * 5 channels: 32 ( 32 x 5 = 160) 474 * 6 channels: 32 ( 32 x 6 = 192) 475 * 7 channels: 32 ( 32 x 7 = 224) 476 * 8 channels: 32 ( 32 x 8 = 256) 477 */ 478 for (i = 1; i < fsi->chan; i <<= 1) 479 fsi->fifo_max >>= 1; 480 dev_dbg(dai->dev, "%d channel %d store\n", fsi->chan, fsi->fifo_max); 481 482 ctrl = is_play ? DOFF_CTL : DIFF_CTL; 483 484 /* set interrupt generation factor */ 485 fsi_reg_write(fsi, ctrl, IRQ_HALF); 486 487 /* clear FIFO */ 488 fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR); 489} 490 491static void fsi_soft_all_reset(struct fsi_master *master) 492{ 493 /* port AB reset */ 494 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0); 495 mdelay(10); 496 497 /* soft reset */ 498 fsi_master_mask_set(master, SOFT_RST, FSISR, 0); 499 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR); 500 mdelay(10); 501} 502 503/* playback interrupt */ 504static int fsi_data_push(struct fsi_priv *fsi, int startup) 505{ 506 struct snd_pcm_runtime *runtime; 507 struct snd_pcm_substream *substream = NULL; 508 u32 status; 509 int send; 510 int fifo_free; 511 int width; 512 u8 *start; 513 int i, over_period; 514 515 if (!fsi || 516 !fsi->substream || 517 !fsi->substream->runtime) 518 return -EINVAL; 519 520 over_period = 0; 521 substream = fsi->substream; 522 runtime = substream->runtime; 523 524 /* FSI FIFO has limit. 525 * So, this driver can not send periods data at a time 526 */ 527 if (fsi->byte_offset >= 528 fsi->period_len * (fsi->periods + 1)) { 529 530 over_period = 1; 531 fsi->periods = (fsi->periods + 1) % runtime->periods; 532 533 if (0 == fsi->periods) 534 fsi->byte_offset = 0; 535 } 536 537 /* get 1 channel data width */ 538 width = frames_to_bytes(runtime, 1) / fsi->chan; 539 540 /* get send size for alsa */ 541 send = (fsi->buffer_len - fsi->byte_offset) / width; 542 543 /* get FIFO free size */ 544 fifo_free = (fsi->fifo_max * fsi->chan) - fsi_get_fifo_residue(fsi, 1); 545 546 /* size check */ 547 if (fifo_free < send) 548 send = fifo_free; 549 550 start = runtime->dma_area; 551 start += fsi->byte_offset; 552 553 switch (width) { 554 case 2: 555 for (i = 0; i < send; i++) 556 fsi_reg_write(fsi, DODT, 557 ((u32)*((u16 *)start + i) << 8)); 558 break; 559 case 4: 560 for (i = 0; i < send; i++) 561 fsi_reg_write(fsi, DODT, *((u32 *)start + i)); 562 break; 563 default: 564 return -EINVAL; 565 } 566 567 fsi->byte_offset += send * width; 568 569 status = fsi_reg_read(fsi, DOFF_ST); 570 if (!startup) { 571 struct snd_soc_dai *dai = fsi_get_dai(substream); 572 573 if (status & ERR_OVER) 574 dev_err(dai->dev, "over run\n"); 575 if (status & ERR_UNDER) 576 dev_err(dai->dev, "under run\n"); 577 } 578 fsi_reg_write(fsi, DOFF_ST, 0); 579 580 fsi_irq_enable(fsi, 1); 581 582 if (over_period) 583 snd_pcm_period_elapsed(substream); 584 585 return 0; 586} 587 588static int fsi_data_pop(struct fsi_priv *fsi, int startup) 589{ 590 struct snd_pcm_runtime *runtime; 591 struct snd_pcm_substream *substream = NULL; 592 u32 status; 593 int free; 594 int fifo_fill; 595 int width; 596 u8 *start; 597 int i, over_period; 598 599 if (!fsi || 600 !fsi->substream || 601 !fsi->substream->runtime) 602 return -EINVAL; 603 604 over_period = 0; 605 substream = fsi->substream; 606 runtime = substream->runtime; 607 608 /* FSI FIFO has limit. 609 * So, this driver can not send periods data at a time 610 */ 611 if (fsi->byte_offset >= 612 fsi->period_len * (fsi->periods + 1)) { 613 614 over_period = 1; 615 fsi->periods = (fsi->periods + 1) % runtime->periods; 616 617 if (0 == fsi->periods) 618 fsi->byte_offset = 0; 619 } 620 621 /* get 1 channel data width */ 622 width = frames_to_bytes(runtime, 1) / fsi->chan; 623 624 /* get free space for alsa */ 625 free = (fsi->buffer_len - fsi->byte_offset) / width; 626 627 /* get recv size */ 628 fifo_fill = fsi_get_fifo_residue(fsi, 0); 629 630 if (free < fifo_fill) 631 fifo_fill = free; 632 633 start = runtime->dma_area; 634 start += fsi->byte_offset; 635 636 switch (width) { 637 case 2: 638 for (i = 0; i < fifo_fill; i++) 639 *((u16 *)start + i) = 640 (u16)(fsi_reg_read(fsi, DIDT) >> 8); 641 break; 642 case 4: 643 for (i = 0; i < fifo_fill; i++) 644 *((u32 *)start + i) = fsi_reg_read(fsi, DIDT); 645 break; 646 default: 647 return -EINVAL; 648 } 649 650 fsi->byte_offset += fifo_fill * width; 651 652 status = fsi_reg_read(fsi, DIFF_ST); 653 if (!startup) { 654 struct snd_soc_dai *dai = fsi_get_dai(substream); 655 656 if (status & ERR_OVER) 657 dev_err(dai->dev, "over run\n"); 658 if (status & ERR_UNDER) 659 dev_err(dai->dev, "under run\n"); 660 } 661 fsi_reg_write(fsi, DIFF_ST, 0); 662 663 fsi_irq_enable(fsi, 0); 664 665 if (over_period) 666 snd_pcm_period_elapsed(substream); 667 668 return 0; 669} 670 671static irqreturn_t fsi_interrupt(int irq, void *data) 672{ 673 struct fsi_master *master = data; 674 u32 int_st = fsi_irq_get_status(master); 675 676 /* clear irq status */ 677 fsi_master_mask_set(master, SOFT_RST, IR, 0); 678 fsi_master_mask_set(master, SOFT_RST, IR, IR); 679 680 if (int_st & INT_A_OUT) 681 fsi_data_push(&master->fsia, 0); 682 if (int_st & INT_B_OUT) 683 fsi_data_push(&master->fsib, 0); 684 if (int_st & INT_A_IN) 685 fsi_data_pop(&master->fsia, 0); 686 if (int_st & INT_B_IN) 687 fsi_data_pop(&master->fsib, 0); 688 689 fsi_irq_clear_all_status(master); 690 691 return IRQ_HANDLED; 692} 693 694/************************************************************************ 695 696 697 dai ops 698 699 700************************************************************************/ 701static int fsi_dai_startup(struct snd_pcm_substream *substream, 702 struct snd_soc_dai *dai) 703{ 704 struct fsi_priv *fsi = fsi_get_priv(substream); 705 u32 flags = fsi_get_info_flags(fsi); 706 struct fsi_master *master = fsi_get_master(fsi); 707 u32 fmt; 708 u32 reg; 709 u32 data; 710 int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 711 int is_master; 712 int ret = 0; 713 714 pm_runtime_get_sync(dai->dev); 715 716 /* CKG1 */ 717 data = is_play ? (1 << 0) : (1 << 4); 718 is_master = fsi_is_master_mode(fsi, is_play); 719 if (is_master) 720 fsi_reg_mask_set(fsi, CKG1, data, data); 721 else 722 fsi_reg_mask_set(fsi, CKG1, data, 0); 723 724 /* clock inversion (CKG2) */ 725 data = 0; 726 if (SH_FSI_LRM_INV & flags) 727 data |= 1 << 12; 728 if (SH_FSI_BRM_INV & flags) 729 data |= 1 << 8; 730 if (SH_FSI_LRS_INV & flags) 731 data |= 1 << 4; 732 if (SH_FSI_BRS_INV & flags) 733 data |= 1 << 0; 734 735 fsi_reg_write(fsi, CKG2, data); 736 737 /* do fmt, di fmt */ 738 data = 0; 739 reg = is_play ? DO_FMT : DI_FMT; 740 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags); 741 switch (fmt) { 742 case SH_FSI_FMT_MONO: 743 data = CR_MONO; 744 fsi->chan = 1; 745 break; 746 case SH_FSI_FMT_MONO_DELAY: 747 data = CR_MONO_D; 748 fsi->chan = 1; 749 break; 750 case SH_FSI_FMT_PCM: 751 data = CR_PCM; 752 fsi->chan = 2; 753 break; 754 case SH_FSI_FMT_I2S: 755 data = CR_I2S; 756 fsi->chan = 2; 757 break; 758 case SH_FSI_FMT_TDM: 759 fsi->chan = is_play ? 760 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); 761 data = CR_TDM | (fsi->chan - 1); 762 break; 763 case SH_FSI_FMT_TDM_DELAY: 764 fsi->chan = is_play ? 765 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); 766 data = CR_TDM_D | (fsi->chan - 1); 767 break; 768 case SH_FSI_FMT_SPDIF: 769 if (master->core->ver < 2) { 770 dev_err(dai->dev, "This FSI can not use SPDIF\n"); 771 return -EINVAL; 772 } 773 data = CR_SPDIF; 774 fsi->chan = 2; 775 fsi_spdif_clk_ctrl(fsi, 1); 776 fsi_reg_mask_set(fsi, OUT_SEL, 0x0010, 0x0010); 777 break; 778 default: 779 dev_err(dai->dev, "unknown format.\n"); 780 return -EINVAL; 781 } 782 fsi_reg_write(fsi, reg, data); 783 784 /* irq clear */ 785 fsi_irq_disable(fsi, is_play); 786 fsi_irq_clear_status(fsi); 787 788 /* fifo init */ 789 fsi_fifo_init(fsi, is_play, dai); 790 791 return ret; 792} 793 794static void fsi_dai_shutdown(struct snd_pcm_substream *substream, 795 struct snd_soc_dai *dai) 796{ 797 struct fsi_priv *fsi = fsi_get_priv(substream); 798 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 799 800 fsi_irq_disable(fsi, is_play); 801 fsi_clk_ctrl(fsi, 0); 802 803 pm_runtime_put_sync(dai->dev); 804} 805 806static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 807 struct snd_soc_dai *dai) 808{ 809 struct fsi_priv *fsi = fsi_get_priv(substream); 810 struct snd_pcm_runtime *runtime = substream->runtime; 811 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 812 int ret = 0; 813 814 switch (cmd) { 815 case SNDRV_PCM_TRIGGER_START: 816 fsi_stream_push(fsi, substream, 817 frames_to_bytes(runtime, runtime->buffer_size), 818 frames_to_bytes(runtime, runtime->period_size)); 819 ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1); 820 break; 821 case SNDRV_PCM_TRIGGER_STOP: 822 fsi_irq_disable(fsi, is_play); 823 fsi_stream_pop(fsi); 824 break; 825 } 826 827 return ret; 828} 829 830static int fsi_dai_hw_params(struct snd_pcm_substream *substream, 831 struct snd_pcm_hw_params *params, 832 struct snd_soc_dai *dai) 833{ 834 struct fsi_priv *fsi = fsi_get_priv(substream); 835 struct fsi_master *master = fsi_get_master(fsi); 836 int (*set_rate)(int is_porta, int rate) = master->info->set_rate; 837 int fsi_ver = master->core->ver; 838 int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 839 int ret; 840 841 /* if slave mode, set_rate is not needed */ 842 if (!fsi_is_master_mode(fsi, is_play)) 843 return 0; 844 845 /* it is error if no set_rate */ 846 if (!set_rate) 847 return -EIO; 848 849 ret = set_rate(fsi_is_port_a(fsi), params_rate(params)); 850 if (ret > 0) { 851 u32 data = 0; 852 853 switch (ret & SH_FSI_ACKMD_MASK) { 854 default: 855 /* FALL THROUGH */ 856 case SH_FSI_ACKMD_512: 857 data |= (0x0 << 12); 858 break; 859 case SH_FSI_ACKMD_256: 860 data |= (0x1 << 12); 861 break; 862 case SH_FSI_ACKMD_128: 863 data |= (0x2 << 12); 864 break; 865 case SH_FSI_ACKMD_64: 866 data |= (0x3 << 12); 867 break; 868 case SH_FSI_ACKMD_32: 869 if (fsi_ver < 2) 870 dev_err(dai->dev, "unsupported ACKMD\n"); 871 else 872 data |= (0x4 << 12); 873 break; 874 } 875 876 switch (ret & SH_FSI_BPFMD_MASK) { 877 default: 878 /* FALL THROUGH */ 879 case SH_FSI_BPFMD_32: 880 data |= (0x0 << 8); 881 break; 882 case SH_FSI_BPFMD_64: 883 data |= (0x1 << 8); 884 break; 885 case SH_FSI_BPFMD_128: 886 data |= (0x2 << 8); 887 break; 888 case SH_FSI_BPFMD_256: 889 data |= (0x3 << 8); 890 break; 891 case SH_FSI_BPFMD_512: 892 data |= (0x4 << 8); 893 break; 894 case SH_FSI_BPFMD_16: 895 if (fsi_ver < 2) 896 dev_err(dai->dev, "unsupported ACKMD\n"); 897 else 898 data |= (0x7 << 8); 899 break; 900 } 901 902 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); 903 udelay(10); 904 fsi_clk_ctrl(fsi, 1); 905 ret = 0; 906 } 907 908 return ret; 909 910} 911 912static struct snd_soc_dai_ops fsi_dai_ops = { 913 .startup = fsi_dai_startup, 914 .shutdown = fsi_dai_shutdown, 915 .trigger = fsi_dai_trigger, 916 .hw_params = fsi_dai_hw_params, 917}; 918 919/************************************************************************ 920 921 922 pcm ops 923 924 925************************************************************************/ 926static struct snd_pcm_hardware fsi_pcm_hardware = { 927 .info = SNDRV_PCM_INFO_INTERLEAVED | 928 SNDRV_PCM_INFO_MMAP | 929 SNDRV_PCM_INFO_MMAP_VALID | 930 SNDRV_PCM_INFO_PAUSE, 931 .formats = FSI_FMTS, 932 .rates = FSI_RATES, 933 .rate_min = 8000, 934 .rate_max = 192000, 935 .channels_min = 1, 936 .channels_max = 2, 937 .buffer_bytes_max = 64 * 1024, 938 .period_bytes_min = 32, 939 .period_bytes_max = 8192, 940 .periods_min = 1, 941 .periods_max = 32, 942 .fifo_size = 256, 943}; 944 945static int fsi_pcm_open(struct snd_pcm_substream *substream) 946{ 947 struct snd_pcm_runtime *runtime = substream->runtime; 948 int ret = 0; 949 950 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); 951 952 ret = snd_pcm_hw_constraint_integer(runtime, 953 SNDRV_PCM_HW_PARAM_PERIODS); 954 955 return ret; 956} 957 958static int fsi_hw_params(struct snd_pcm_substream *substream, 959 struct snd_pcm_hw_params *hw_params) 960{ 961 return snd_pcm_lib_malloc_pages(substream, 962 params_buffer_bytes(hw_params)); 963} 964 965static int fsi_hw_free(struct snd_pcm_substream *substream) 966{ 967 return snd_pcm_lib_free_pages(substream); 968} 969 970static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) 971{ 972 struct snd_pcm_runtime *runtime = substream->runtime; 973 struct fsi_priv *fsi = fsi_get_priv(substream); 974 long location; 975 976 location = (fsi->byte_offset - 1); 977 if (location < 0) 978 location = 0; 979 980 return bytes_to_frames(runtime, location); 981} 982 983static struct snd_pcm_ops fsi_pcm_ops = { 984 .open = fsi_pcm_open, 985 .ioctl = snd_pcm_lib_ioctl, 986 .hw_params = fsi_hw_params, 987 .hw_free = fsi_hw_free, 988 .pointer = fsi_pointer, 989}; 990 991/************************************************************************ 992 993 994 snd_soc_platform 995 996 997************************************************************************/ 998#define PREALLOC_BUFFER (32 * 1024) 999#define PREALLOC_BUFFER_MAX (32 * 1024) 1000 1001static void fsi_pcm_free(struct snd_pcm *pcm) 1002{ 1003 snd_pcm_lib_preallocate_free_for_all(pcm); 1004} 1005 1006static int fsi_pcm_new(struct snd_card *card, 1007 struct snd_soc_dai *dai, 1008 struct snd_pcm *pcm) 1009{ 1010 /* 1011 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel 1012 * in MMAP mode (i.e. aplay -M) 1013 */ 1014 return snd_pcm_lib_preallocate_pages_for_all( 1015 pcm, 1016 SNDRV_DMA_TYPE_CONTINUOUS, 1017 snd_dma_continuous_data(GFP_KERNEL), 1018 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 1019} 1020 1021/************************************************************************ 1022 1023 1024 alsa struct 1025 1026 1027************************************************************************/ 1028struct snd_soc_dai fsi_soc_dai[] = { 1029 { 1030 .name = "FSIA", 1031 .id = 0, 1032 .playback = { 1033 .rates = FSI_RATES, 1034 .formats = FSI_FMTS, 1035 .channels_min = 1, 1036 .channels_max = 8, 1037 }, 1038 .capture = { 1039 .rates = FSI_RATES, 1040 .formats = FSI_FMTS, 1041 .channels_min = 1, 1042 .channels_max = 8, 1043 }, 1044 .ops = &fsi_dai_ops, 1045 }, 1046 { 1047 .name = "FSIB", 1048 .id = 1, 1049 .playback = { 1050 .rates = FSI_RATES, 1051 .formats = FSI_FMTS, 1052 .channels_min = 1, 1053 .channels_max = 8, 1054 }, 1055 .capture = { 1056 .rates = FSI_RATES, 1057 .formats = FSI_FMTS, 1058 .channels_min = 1, 1059 .channels_max = 8, 1060 }, 1061 .ops = &fsi_dai_ops, 1062 }, 1063}; 1064EXPORT_SYMBOL_GPL(fsi_soc_dai); 1065 1066struct snd_soc_platform fsi_soc_platform = { 1067 .name = "fsi-pcm", 1068 .pcm_ops = &fsi_pcm_ops, 1069 .pcm_new = fsi_pcm_new, 1070 .pcm_free = fsi_pcm_free, 1071}; 1072EXPORT_SYMBOL_GPL(fsi_soc_platform); 1073 1074/************************************************************************ 1075 1076 1077 platform function 1078 1079 1080************************************************************************/ 1081static int fsi_probe(struct platform_device *pdev) 1082{ 1083 struct fsi_master *master; 1084 const struct platform_device_id *id_entry; 1085 struct resource *res; 1086 unsigned int irq; 1087 int ret; 1088 1089 id_entry = pdev->id_entry; 1090 if (!id_entry) { 1091 dev_err(&pdev->dev, "unknown fsi device\n"); 1092 return -ENODEV; 1093 } 1094 1095 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1096 irq = platform_get_irq(pdev, 0); 1097 if (!res || (int)irq <= 0) { 1098 dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); 1099 ret = -ENODEV; 1100 goto exit; 1101 } 1102 1103 master = kzalloc(sizeof(*master), GFP_KERNEL); 1104 if (!master) { 1105 dev_err(&pdev->dev, "Could not allocate master\n"); 1106 ret = -ENOMEM; 1107 goto exit; 1108 } 1109 1110 master->base = ioremap_nocache(res->start, resource_size(res)); 1111 if (!master->base) { 1112 ret = -ENXIO; 1113 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); 1114 goto exit_kfree; 1115 } 1116 1117 /* master setting */ 1118 master->irq = irq; 1119 master->info = pdev->dev.platform_data; 1120 master->core = (struct fsi_core *)id_entry->driver_data; 1121 spin_lock_init(&master->lock); 1122 1123 /* FSI A setting */ 1124 master->fsia.base = master->base; 1125 master->fsia.master = master; 1126 master->fsia.mst_ctrl = A_MST_CTLR; 1127 1128 /* FSI B setting */ 1129 master->fsib.base = master->base + 0x40; 1130 master->fsib.master = master; 1131 master->fsib.mst_ctrl = B_MST_CTLR; 1132 1133 pm_runtime_enable(&pdev->dev); 1134 pm_runtime_resume(&pdev->dev); 1135 1136 fsi_soc_dai[0].dev = &pdev->dev; 1137 fsi_soc_dai[0].private_data = &master->fsia; 1138 fsi_soc_dai[1].dev = &pdev->dev; 1139 fsi_soc_dai[1].private_data = &master->fsib; 1140 1141 fsi_soft_all_reset(master); 1142 1143 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, 1144 id_entry->name, master); 1145 if (ret) { 1146 dev_err(&pdev->dev, "irq request err\n"); 1147 goto exit_iounmap; 1148 } 1149 1150 ret = snd_soc_register_platform(&fsi_soc_platform); 1151 if (ret < 0) { 1152 dev_err(&pdev->dev, "cannot snd soc register\n"); 1153 goto exit_free_irq; 1154 } 1155 1156 return snd_soc_register_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); 1157 1158exit_free_irq: 1159 free_irq(irq, master); 1160exit_iounmap: 1161 iounmap(master->base); 1162 pm_runtime_disable(&pdev->dev); 1163exit_kfree: 1164 kfree(master); 1165 master = NULL; 1166exit: 1167 return ret; 1168} 1169 1170static int fsi_remove(struct platform_device *pdev) 1171{ 1172 struct fsi_master *master; 1173 1174 master = fsi_get_master(fsi_soc_dai[0].private_data); 1175 1176 snd_soc_unregister_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); 1177 snd_soc_unregister_platform(&fsi_soc_platform); 1178 1179 pm_runtime_disable(&pdev->dev); 1180 1181 free_irq(master->irq, master); 1182 1183 iounmap(master->base); 1184 kfree(master); 1185 1186 fsi_soc_dai[0].dev = NULL; 1187 fsi_soc_dai[0].private_data = NULL; 1188 fsi_soc_dai[1].dev = NULL; 1189 fsi_soc_dai[1].private_data = NULL; 1190 1191 return 0; 1192} 1193 1194static int fsi_runtime_nop(struct device *dev) 1195{ 1196 /* Runtime PM callback shared between ->runtime_suspend() 1197 * and ->runtime_resume(). Simply returns success. 1198 * 1199 * This driver re-initializes all registers after 1200 * pm_runtime_get_sync() anyway so there is no need 1201 * to save and restore registers here. 1202 */ 1203 return 0; 1204} 1205 1206static struct dev_pm_ops fsi_pm_ops = { 1207 .runtime_suspend = fsi_runtime_nop, 1208 .runtime_resume = fsi_runtime_nop, 1209}; 1210 1211static struct fsi_core fsi1_core = { 1212 .ver = 1, 1213 1214 /* Interrupt */ 1215 .int_st = INT_ST, 1216 .iemsk = IEMSK, 1217 .imsk = IMSK, 1218}; 1219 1220static struct fsi_core fsi2_core = { 1221 .ver = 2, 1222 1223 /* Interrupt */ 1224 .int_st = CPU_INT_ST, 1225 .iemsk = CPU_IEMSK, 1226 .imsk = CPU_IMSK, 1227}; 1228 1229static struct platform_device_id fsi_id_table[] = { 1230 { "sh_fsi", (kernel_ulong_t)&fsi1_core }, 1231 { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, 1232}; 1233 1234static struct platform_driver fsi_driver = { 1235 .driver = { 1236 .name = "sh_fsi", 1237 .pm = &fsi_pm_ops, 1238 }, 1239 .probe = fsi_probe, 1240 .remove = fsi_remove, 1241 .id_table = fsi_id_table, 1242}; 1243 1244static int __init fsi_mobile_init(void) 1245{ 1246 return platform_driver_register(&fsi_driver); 1247} 1248 1249static void __exit fsi_mobile_exit(void) 1250{ 1251 platform_driver_unregister(&fsi_driver); 1252} 1253module_init(fsi_mobile_init); 1254module_exit(fsi_mobile_exit); 1255 1256MODULE_LICENSE("GPL"); 1257MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); 1258MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); 1259