1/* 2 * wm8900.c -- WM8900 ALSA Soc Audio driver 3 * 4 * Copyright 2007, 2008 Wolfson Microelectronics PLC. 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * TODO: 13 * - Tristating. 14 * - TDM. 15 * - Jack detect. 16 * - FLL source configuration, currently only MCLK is supported. 17 */ 18 19#include <linux/module.h> 20#include <linux/moduleparam.h> 21#include <linux/kernel.h> 22#include <linux/init.h> 23#include <linux/delay.h> 24#include <linux/pm.h> 25#include <linux/i2c.h> 26#include <linux/platform_device.h> 27#include <linux/slab.h> 28#include <sound/core.h> 29#include <sound/pcm.h> 30#include <sound/pcm_params.h> 31#include <sound/soc.h> 32#include <sound/soc-dapm.h> 33#include <sound/initval.h> 34#include <sound/tlv.h> 35 36#include "wm8900.h" 37 38/* WM8900 register space */ 39#define WM8900_REG_RESET 0x0 40#define WM8900_REG_ID 0x0 41#define WM8900_REG_POWER1 0x1 42#define WM8900_REG_POWER2 0x2 43#define WM8900_REG_POWER3 0x3 44#define WM8900_REG_AUDIO1 0x4 45#define WM8900_REG_AUDIO2 0x5 46#define WM8900_REG_CLOCKING1 0x6 47#define WM8900_REG_CLOCKING2 0x7 48#define WM8900_REG_AUDIO3 0x8 49#define WM8900_REG_AUDIO4 0x9 50#define WM8900_REG_DACCTRL 0xa 51#define WM8900_REG_LDAC_DV 0xb 52#define WM8900_REG_RDAC_DV 0xc 53#define WM8900_REG_SIDETONE 0xd 54#define WM8900_REG_ADCCTRL 0xe 55#define WM8900_REG_LADC_DV 0xf 56#define WM8900_REG_RADC_DV 0x10 57#define WM8900_REG_GPIO 0x12 58#define WM8900_REG_INCTL 0x15 59#define WM8900_REG_LINVOL 0x16 60#define WM8900_REG_RINVOL 0x17 61#define WM8900_REG_INBOOSTMIX1 0x18 62#define WM8900_REG_INBOOSTMIX2 0x19 63#define WM8900_REG_ADCPATH 0x1a 64#define WM8900_REG_AUXBOOST 0x1b 65#define WM8900_REG_ADDCTL 0x1e 66#define WM8900_REG_FLLCTL1 0x24 67#define WM8900_REG_FLLCTL2 0x25 68#define WM8900_REG_FLLCTL3 0x26 69#define WM8900_REG_FLLCTL4 0x27 70#define WM8900_REG_FLLCTL5 0x28 71#define WM8900_REG_FLLCTL6 0x29 72#define WM8900_REG_LOUTMIXCTL1 0x2c 73#define WM8900_REG_ROUTMIXCTL1 0x2d 74#define WM8900_REG_BYPASS1 0x2e 75#define WM8900_REG_BYPASS2 0x2f 76#define WM8900_REG_AUXOUT_CTL 0x30 77#define WM8900_REG_LOUT1CTL 0x33 78#define WM8900_REG_ROUT1CTL 0x34 79#define WM8900_REG_LOUT2CTL 0x35 80#define WM8900_REG_ROUT2CTL 0x36 81#define WM8900_REG_HPCTL1 0x3a 82#define WM8900_REG_OUTBIASCTL 0x73 83 84#define WM8900_MAXREG 0x80 85 86#define WM8900_REG_ADDCTL_OUT1_DIS 0x80 87#define WM8900_REG_ADDCTL_OUT2_DIS 0x40 88#define WM8900_REG_ADDCTL_VMID_DIS 0x20 89#define WM8900_REG_ADDCTL_BIAS_SRC 0x10 90#define WM8900_REG_ADDCTL_VMID_SOFTST 0x04 91#define WM8900_REG_ADDCTL_TEMP_SD 0x02 92 93#define WM8900_REG_GPIO_TEMP_ENA 0x2 94 95#define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100 96#define WM8900_REG_POWER1_BIAS_ENA 0x0008 97#define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004 98#define WM8900_REG_POWER1_FLL_ENA 0x0040 99 100#define WM8900_REG_POWER2_SYSCLK_ENA 0x8000 101#define WM8900_REG_POWER2_ADCL_ENA 0x0002 102#define WM8900_REG_POWER2_ADCR_ENA 0x0001 103 104#define WM8900_REG_POWER3_DACL_ENA 0x0002 105#define WM8900_REG_POWER3_DACR_ENA 0x0001 106 107#define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018 108#define WM8900_REG_AUDIO1_LRCLK_INV 0x0080 109#define WM8900_REG_AUDIO1_BCLK_INV 0x0100 110 111#define WM8900_REG_CLOCKING1_BCLK_DIR 0x1 112#define WM8900_REG_CLOCKING1_MCLK_SRC 0x100 113#define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e) 114#define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000) 115 116#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0 117#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c 118 119#define WM8900_REG_DACCTRL_MUTE 0x004 120#define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100 121#define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400 122 123#define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800 124 125#define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800 126 127#define WM8900_REG_FLLCTL1_OSC_ENA 0x100 128 129#define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100 130 131#define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80 132#define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40 133#define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20 134#define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10 135#define WM8900_REG_HPCTL1_HP_SHORT 0x08 136#define WM8900_REG_HPCTL1_HP_SHORT2 0x04 137 138#define WM8900_LRC_MASK 0xfc00 139 140struct snd_soc_codec_device soc_codec_dev_wm8900; 141 142struct wm8900_priv { 143 struct snd_soc_codec codec; 144 145 u16 reg_cache[WM8900_MAXREG]; 146 147 u32 fll_in; /* FLL input frequency */ 148 u32 fll_out; /* FLL output frequency */ 149}; 150 151/* 152 * wm8900 register cache. We can't read the entire register space and we 153 * have slow control buses so we cache the registers. 154 */ 155static const u16 wm8900_reg_defaults[WM8900_MAXREG] = { 156 0x8900, 0x0000, 157 0xc000, 0x0000, 158 0x4050, 0x4000, 159 0x0008, 0x0000, 160 0x0040, 0x0040, 161 0x1004, 0x00c0, 162 0x00c0, 0x0000, 163 0x0100, 0x00c0, 164 0x00c0, 0x0000, 165 0xb001, 0x0000, 166 0x0000, 0x0044, 167 0x004c, 0x004c, 168 0x0044, 0x0044, 169 0x0000, 0x0044, 170 0x0000, 0x0000, 171 0x0002, 0x0000, 172 0x0000, 0x0000, 173 0x0000, 0x0000, 174 0x0008, 0x0000, 175 0x0000, 0x0008, 176 0x0097, 0x0100, 177 0x0000, 0x0000, 178 0x0050, 0x0050, 179 0x0055, 0x0055, 180 0x0055, 0x0000, 181 0x0000, 0x0079, 182 0x0079, 0x0079, 183 0x0079, 0x0000, 184 /* Remaining registers all zero */ 185}; 186 187static int wm8900_volatile_register(unsigned int reg) 188{ 189 switch (reg) { 190 case WM8900_REG_ID: 191 return 1; 192 default: 193 return 0; 194 } 195} 196 197static void wm8900_reset(struct snd_soc_codec *codec) 198{ 199 snd_soc_write(codec, WM8900_REG_RESET, 0); 200 201 memcpy(codec->reg_cache, wm8900_reg_defaults, 202 sizeof(wm8900_reg_defaults)); 203} 204 205static int wm8900_hp_event(struct snd_soc_dapm_widget *w, 206 struct snd_kcontrol *kcontrol, int event) 207{ 208 struct snd_soc_codec *codec = w->codec; 209 u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1); 210 211 switch (event) { 212 case SND_SOC_DAPM_PRE_PMU: 213 /* Clamp headphone outputs */ 214 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP | 215 WM8900_REG_HPCTL1_HP_CLAMP_OP; 216 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); 217 break; 218 219 case SND_SOC_DAPM_POST_PMU: 220 /* Enable the input stage */ 221 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP; 222 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT | 223 WM8900_REG_HPCTL1_HP_SHORT2 | 224 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; 225 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); 226 227 msleep(400); 228 229 /* Enable the output stage */ 230 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP; 231 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; 232 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); 233 234 /* Remove the shorts */ 235 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2; 236 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); 237 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT; 238 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); 239 break; 240 241 case SND_SOC_DAPM_PRE_PMD: 242 /* Short the output */ 243 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT; 244 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); 245 246 /* Disable the output stage */ 247 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; 248 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); 249 250 /* Clamp the outputs and power down input */ 251 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP | 252 WM8900_REG_HPCTL1_HP_CLAMP_OP; 253 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; 254 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); 255 break; 256 257 case SND_SOC_DAPM_POST_PMD: 258 /* Disable everything */ 259 snd_soc_write(codec, WM8900_REG_HPCTL1, 0); 260 break; 261 262 default: 263 BUG(); 264 } 265 266 return 0; 267} 268 269static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0); 270 271static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0); 272 273static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0); 274 275static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0); 276 277static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 278 279static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1); 280 281static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0); 282 283static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1); 284 285static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" }; 286 287static const struct soc_enum mic_bias_level = 288SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt); 289 290static const char *dac_mute_rate_txt[] = { "Fast", "Slow" }; 291 292static const struct soc_enum dac_mute_rate = 293SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt); 294 295static const char *dac_deemphasis_txt[] = { 296 "Disabled", "32kHz", "44.1kHz", "48kHz" 297}; 298 299static const struct soc_enum dac_deemphasis = 300SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt); 301 302static const char *adc_hpf_cut_txt[] = { 303 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3" 304}; 305 306static const struct soc_enum adc_hpf_cut = 307SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt); 308 309static const char *lr_txt[] = { 310 "Left", "Right" 311}; 312 313static const struct soc_enum aifl_src = 314SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt); 315 316static const struct soc_enum aifr_src = 317SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt); 318 319static const struct soc_enum dacl_src = 320SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt); 321 322static const struct soc_enum dacr_src = 323SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt); 324 325static const char *sidetone_txt[] = { 326 "Disabled", "Left ADC", "Right ADC" 327}; 328 329static const struct soc_enum dacl_sidetone = 330SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt); 331 332static const struct soc_enum dacr_sidetone = 333SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt); 334 335static const struct snd_kcontrol_new wm8900_snd_controls[] = { 336SOC_ENUM("Mic Bias Level", mic_bias_level), 337 338SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0, 339 in_pga_tlv), 340SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1), 341SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0), 342 343SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0, 344 in_pga_tlv), 345SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1), 346SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0), 347 348SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1), 349SOC_ENUM("DAC Mute Rate", dac_mute_rate), 350SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0), 351SOC_ENUM("DAC Deemphasis", dac_deemphasis), 352SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL, 353 12, 1, 0), 354 355SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0), 356SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut), 357SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0), 358SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0, 359 adc_svol_tlv), 360SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0, 361 adc_svol_tlv), 362SOC_ENUM("Left Digital Audio Source", aifl_src), 363SOC_ENUM("Right Digital Audio Source", aifr_src), 364 365SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0, 366 dac_boost_tlv), 367SOC_ENUM("Left DAC Source", dacl_src), 368SOC_ENUM("Right DAC Source", dacr_src), 369SOC_ENUM("Left DAC Sidetone", dacl_sidetone), 370SOC_ENUM("Right DAC Sidetone", dacr_sidetone), 371SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0), 372 373SOC_DOUBLE_R_TLV("Digital Playback Volume", 374 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV, 375 1, 96, 0, dac_tlv), 376SOC_DOUBLE_R_TLV("Digital Capture Volume", 377 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv), 378 379SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0, 380 out_mix_tlv), 381SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0, 382 out_mix_tlv), 383SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0, 384 out_mix_tlv), 385SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0, 386 out_mix_tlv), 387 388SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0, 389 out_mix_tlv), 390SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0, 391 out_mix_tlv), 392SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0, 393 out_mix_tlv), 394SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0, 395 out_mix_tlv), 396 397SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0, 398 in_boost_tlv), 399SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0, 400 in_boost_tlv), 401SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0, 402 in_boost_tlv), 403SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0, 404 in_boost_tlv), 405SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0, 406 in_boost_tlv), 407SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0, 408 in_boost_tlv), 409 410SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL, 411 0, 63, 0, out_pga_tlv), 412SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL, 413 6, 1, 1), 414SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL, 415 7, 1, 0), 416 417SOC_DOUBLE_R_TLV("LINEOUT2 Volume", 418 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 419 0, 63, 0, out_pga_tlv), 420SOC_DOUBLE_R("LINEOUT2 Switch", 421 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1), 422SOC_DOUBLE_R("LINEOUT2 ZC Switch", 423 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0), 424SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1, 425 0, 1, 1), 426 427}; 428 429static const struct snd_kcontrol_new wm8900_dapm_loutput2_control = 430SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0); 431 432static const struct snd_kcontrol_new wm8900_dapm_routput2_control = 433SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0); 434 435static const struct snd_kcontrol_new wm8900_loutmix_controls[] = { 436SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0), 437SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0), 438SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0), 439SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0), 440SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0), 441}; 442 443static const struct snd_kcontrol_new wm8900_routmix_controls[] = { 444SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0), 445SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0), 446SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0), 447SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0), 448SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0), 449}; 450 451static const struct snd_kcontrol_new wm8900_linmix_controls[] = { 452SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1), 453SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1), 454SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1), 455SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0), 456}; 457 458static const struct snd_kcontrol_new wm8900_rinmix_controls[] = { 459SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1), 460SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1), 461SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1), 462SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0), 463}; 464 465static const struct snd_kcontrol_new wm8900_linpga_controls[] = { 466SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0), 467SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0), 468SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0), 469}; 470 471static const struct snd_kcontrol_new wm8900_rinpga_controls[] = { 472SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0), 473SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0), 474SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0), 475}; 476 477static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" }; 478 479static const struct soc_enum wm8900_lineout2_lp_mux = 480SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux); 481 482static const struct snd_kcontrol_new wm8900_lineout2_lp = 483SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux); 484 485static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = { 486 487/* Externally visible pins */ 488SND_SOC_DAPM_OUTPUT("LINEOUT1L"), 489SND_SOC_DAPM_OUTPUT("LINEOUT1R"), 490SND_SOC_DAPM_OUTPUT("LINEOUT2L"), 491SND_SOC_DAPM_OUTPUT("LINEOUT2R"), 492SND_SOC_DAPM_OUTPUT("HP_L"), 493SND_SOC_DAPM_OUTPUT("HP_R"), 494 495SND_SOC_DAPM_INPUT("RINPUT1"), 496SND_SOC_DAPM_INPUT("LINPUT1"), 497SND_SOC_DAPM_INPUT("RINPUT2"), 498SND_SOC_DAPM_INPUT("LINPUT2"), 499SND_SOC_DAPM_INPUT("RINPUT3"), 500SND_SOC_DAPM_INPUT("LINPUT3"), 501SND_SOC_DAPM_INPUT("AUX"), 502 503SND_SOC_DAPM_VMID("VMID"), 504 505/* Input */ 506SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0, 507 wm8900_linpga_controls, 508 ARRAY_SIZE(wm8900_linpga_controls)), 509SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0, 510 wm8900_rinpga_controls, 511 ARRAY_SIZE(wm8900_rinpga_controls)), 512 513SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0, 514 wm8900_linmix_controls, 515 ARRAY_SIZE(wm8900_linmix_controls)), 516SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0, 517 wm8900_rinmix_controls, 518 ARRAY_SIZE(wm8900_rinmix_controls)), 519 520SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1, 4, 0), 521 522SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0), 523SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0), 524 525/* Output */ 526SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0), 527SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0), 528 529SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0, 530 wm8900_hp_event, 531 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 532 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 533 534SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0), 535SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0), 536 537SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp), 538SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0), 539SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0), 540 541SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0, 542 wm8900_loutmix_controls, 543 ARRAY_SIZE(wm8900_loutmix_controls)), 544SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0, 545 wm8900_routmix_controls, 546 ARRAY_SIZE(wm8900_routmix_controls)), 547}; 548 549/* Target, Path, Source */ 550static const struct snd_soc_dapm_route audio_map[] = { 551/* Inputs */ 552{"Left Input PGA", "LINPUT1 Switch", "LINPUT1"}, 553{"Left Input PGA", "LINPUT2 Switch", "LINPUT2"}, 554{"Left Input PGA", "LINPUT3 Switch", "LINPUT3"}, 555 556{"Right Input PGA", "RINPUT1 Switch", "RINPUT1"}, 557{"Right Input PGA", "RINPUT2 Switch", "RINPUT2"}, 558{"Right Input PGA", "RINPUT3 Switch", "RINPUT3"}, 559 560{"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"}, 561{"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"}, 562{"Left Input Mixer", "AUX Switch", "AUX"}, 563{"Left Input Mixer", "Input PGA Switch", "Left Input PGA"}, 564 565{"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"}, 566{"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"}, 567{"Right Input Mixer", "AUX Switch", "AUX"}, 568{"Right Input Mixer", "Input PGA Switch", "Right Input PGA"}, 569 570{"ADCL", NULL, "Left Input Mixer"}, 571{"ADCR", NULL, "Right Input Mixer"}, 572 573/* Outputs */ 574{"LINEOUT1L", NULL, "LINEOUT1L PGA"}, 575{"LINEOUT1L PGA", NULL, "Left Output Mixer"}, 576{"LINEOUT1R", NULL, "LINEOUT1R PGA"}, 577{"LINEOUT1R PGA", NULL, "Right Output Mixer"}, 578 579{"LINEOUT2L PGA", NULL, "Left Output Mixer"}, 580{"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"}, 581{"LINEOUT2 LP", "Enabled", "Left Output Mixer"}, 582{"LINEOUT2L", NULL, "LINEOUT2 LP"}, 583 584{"LINEOUT2R PGA", NULL, "Right Output Mixer"}, 585{"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"}, 586{"LINEOUT2 LP", "Enabled", "Right Output Mixer"}, 587{"LINEOUT2R", NULL, "LINEOUT2 LP"}, 588 589{"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"}, 590{"Left Output Mixer", "AUX Bypass Switch", "AUX"}, 591{"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"}, 592{"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"}, 593{"Left Output Mixer", "DACL Switch", "DACL"}, 594 595{"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"}, 596{"Right Output Mixer", "AUX Bypass Switch", "AUX"}, 597{"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"}, 598{"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"}, 599{"Right Output Mixer", "DACR Switch", "DACR"}, 600 601/* Note that the headphone output stage needs to be connected 602 * externally to LINEOUT2 via DC blocking capacitors. Other 603 * configurations are not supported. 604 * 605 * Note also that left and right headphone paths are treated as a 606 * mono path. 607 */ 608{"Headphone Amplifier", NULL, "LINEOUT2 LP"}, 609{"Headphone Amplifier", NULL, "LINEOUT2 LP"}, 610{"HP_L", NULL, "Headphone Amplifier"}, 611{"HP_R", NULL, "Headphone Amplifier"}, 612}; 613 614static int wm8900_add_widgets(struct snd_soc_codec *codec) 615{ 616 snd_soc_dapm_new_controls(codec, wm8900_dapm_widgets, 617 ARRAY_SIZE(wm8900_dapm_widgets)); 618 619 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 620 621 return 0; 622} 623 624static int wm8900_hw_params(struct snd_pcm_substream *substream, 625 struct snd_pcm_hw_params *params, 626 struct snd_soc_dai *dai) 627{ 628 struct snd_soc_pcm_runtime *rtd = substream->private_data; 629 struct snd_soc_device *socdev = rtd->socdev; 630 struct snd_soc_codec *codec = socdev->card->codec; 631 u16 reg; 632 633 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60; 634 635 switch (params_format(params)) { 636 case SNDRV_PCM_FORMAT_S16_LE: 637 break; 638 case SNDRV_PCM_FORMAT_S20_3LE: 639 reg |= 0x20; 640 break; 641 case SNDRV_PCM_FORMAT_S24_LE: 642 reg |= 0x40; 643 break; 644 case SNDRV_PCM_FORMAT_S32_LE: 645 reg |= 0x60; 646 break; 647 default: 648 return -EINVAL; 649 } 650 651 snd_soc_write(codec, WM8900_REG_AUDIO1, reg); 652 653 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 654 reg = snd_soc_read(codec, WM8900_REG_DACCTRL); 655 656 if (params_rate(params) <= 24000) 657 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT; 658 else 659 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT; 660 661 snd_soc_write(codec, WM8900_REG_DACCTRL, reg); 662 } 663 664 return 0; 665} 666 667/* FLL divisors */ 668struct _fll_div { 669 u16 fll_ratio; 670 u16 fllclk_div; 671 u16 fll_slow_lock_ref; 672 u16 n; 673 u16 k; 674}; 675 676/* The size in bits of the FLL divide multiplied by 10 677 * to allow rounding later */ 678#define FIXED_FLL_SIZE ((1 << 16) * 10) 679 680static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 681 unsigned int Fout) 682{ 683 u64 Kpart; 684 unsigned int K, Ndiv, Nmod, target; 685 unsigned int div; 686 687 BUG_ON(!Fout); 688 689 /* The FLL must run at 90-100MHz which is then scaled down to 690 * the output value by FLLCLK_DIV. */ 691 target = Fout; 692 div = 1; 693 while (target < 90000000) { 694 div *= 2; 695 target *= 2; 696 } 697 698 if (target > 100000000) 699 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u" 700 " Fout=%u\n", target, Fref, Fout); 701 if (div > 32) { 702 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, " 703 "Fref=%u, Fout=%u, target=%u\n", 704 div, Fref, Fout, target); 705 return -EINVAL; 706 } 707 708 fll_div->fllclk_div = div >> 2; 709 710 if (Fref < 48000) 711 fll_div->fll_slow_lock_ref = 1; 712 else 713 fll_div->fll_slow_lock_ref = 0; 714 715 Ndiv = target / Fref; 716 717 if (Fref < 1000000) 718 fll_div->fll_ratio = 8; 719 else 720 fll_div->fll_ratio = 1; 721 722 fll_div->n = Ndiv / fll_div->fll_ratio; 723 Nmod = (target / fll_div->fll_ratio) % Fref; 724 725 /* Calculate fractional part - scale up so we can round. */ 726 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 727 728 do_div(Kpart, Fref); 729 730 K = Kpart & 0xFFFFFFFF; 731 732 if ((K % 10) >= 5) 733 K += 5; 734 735 /* Move down to proper range now rounding is done */ 736 fll_div->k = K / 10; 737 738 BUG_ON(target != Fout * (fll_div->fllclk_div << 2)); 739 BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n); 740 741 return 0; 742} 743 744static int wm8900_set_fll(struct snd_soc_codec *codec, 745 int fll_id, unsigned int freq_in, unsigned int freq_out) 746{ 747 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec); 748 struct _fll_div fll_div; 749 unsigned int reg; 750 751 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out) 752 return 0; 753 754 /* The digital side should be disabled during any change. */ 755 reg = snd_soc_read(codec, WM8900_REG_POWER1); 756 snd_soc_write(codec, WM8900_REG_POWER1, 757 reg & (~WM8900_REG_POWER1_FLL_ENA)); 758 759 /* Disable the FLL? */ 760 if (!freq_in || !freq_out) { 761 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1); 762 snd_soc_write(codec, WM8900_REG_CLOCKING1, 763 reg & (~WM8900_REG_CLOCKING1_MCLK_SRC)); 764 765 reg = snd_soc_read(codec, WM8900_REG_FLLCTL1); 766 snd_soc_write(codec, WM8900_REG_FLLCTL1, 767 reg & (~WM8900_REG_FLLCTL1_OSC_ENA)); 768 769 wm8900->fll_in = freq_in; 770 wm8900->fll_out = freq_out; 771 772 return 0; 773 } 774 775 if (fll_factors(&fll_div, freq_in, freq_out) != 0) 776 goto reenable; 777 778 wm8900->fll_in = freq_in; 779 wm8900->fll_out = freq_out; 780 781 /* The osclilator *MUST* be enabled before we enable the 782 * digital circuit. */ 783 snd_soc_write(codec, WM8900_REG_FLLCTL1, 784 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA); 785 786 snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5); 787 snd_soc_write(codec, WM8900_REG_FLLCTL5, 788 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f)); 789 790 if (fll_div.k) { 791 snd_soc_write(codec, WM8900_REG_FLLCTL2, 792 (fll_div.k >> 8) | 0x100); 793 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff); 794 } else 795 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0); 796 797 if (fll_div.fll_slow_lock_ref) 798 snd_soc_write(codec, WM8900_REG_FLLCTL6, 799 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF); 800 else 801 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0); 802 803 reg = snd_soc_read(codec, WM8900_REG_POWER1); 804 snd_soc_write(codec, WM8900_REG_POWER1, 805 reg | WM8900_REG_POWER1_FLL_ENA); 806 807reenable: 808 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1); 809 snd_soc_write(codec, WM8900_REG_CLOCKING1, 810 reg | WM8900_REG_CLOCKING1_MCLK_SRC); 811 812 return 0; 813} 814 815static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, 816 int source, unsigned int freq_in, unsigned int freq_out) 817{ 818 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out); 819} 820 821static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 822 int div_id, int div) 823{ 824 struct snd_soc_codec *codec = codec_dai->codec; 825 unsigned int reg; 826 827 switch (div_id) { 828 case WM8900_BCLK_DIV: 829 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1); 830 snd_soc_write(codec, WM8900_REG_CLOCKING1, 831 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK)); 832 break; 833 case WM8900_OPCLK_DIV: 834 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1); 835 snd_soc_write(codec, WM8900_REG_CLOCKING1, 836 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK)); 837 break; 838 case WM8900_DAC_LRCLK: 839 reg = snd_soc_read(codec, WM8900_REG_AUDIO4); 840 snd_soc_write(codec, WM8900_REG_AUDIO4, 841 div | (reg & WM8900_LRC_MASK)); 842 break; 843 case WM8900_ADC_LRCLK: 844 reg = snd_soc_read(codec, WM8900_REG_AUDIO3); 845 snd_soc_write(codec, WM8900_REG_AUDIO3, 846 div | (reg & WM8900_LRC_MASK)); 847 break; 848 case WM8900_DAC_CLKDIV: 849 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2); 850 snd_soc_write(codec, WM8900_REG_CLOCKING2, 851 div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV)); 852 break; 853 case WM8900_ADC_CLKDIV: 854 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2); 855 snd_soc_write(codec, WM8900_REG_CLOCKING2, 856 div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV)); 857 break; 858 case WM8900_LRCLK_MODE: 859 reg = snd_soc_read(codec, WM8900_REG_DACCTRL); 860 snd_soc_write(codec, WM8900_REG_DACCTRL, 861 div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE)); 862 break; 863 default: 864 return -EINVAL; 865 } 866 867 return 0; 868} 869 870 871static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai, 872 unsigned int fmt) 873{ 874 struct snd_soc_codec *codec = codec_dai->codec; 875 unsigned int clocking1, aif1, aif3, aif4; 876 877 clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1); 878 aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1); 879 aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3); 880 aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4); 881 882 /* set master/slave audio interface */ 883 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 884 case SND_SOC_DAIFMT_CBS_CFS: 885 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR; 886 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR; 887 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR; 888 break; 889 case SND_SOC_DAIFMT_CBS_CFM: 890 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR; 891 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR; 892 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR; 893 break; 894 case SND_SOC_DAIFMT_CBM_CFM: 895 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR; 896 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR; 897 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR; 898 break; 899 case SND_SOC_DAIFMT_CBM_CFS: 900 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR; 901 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR; 902 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR; 903 break; 904 default: 905 return -EINVAL; 906 } 907 908 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 909 case SND_SOC_DAIFMT_DSP_A: 910 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK; 911 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV; 912 break; 913 case SND_SOC_DAIFMT_DSP_B: 914 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK; 915 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV; 916 break; 917 case SND_SOC_DAIFMT_I2S: 918 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK; 919 aif1 |= 0x10; 920 break; 921 case SND_SOC_DAIFMT_RIGHT_J: 922 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK; 923 break; 924 case SND_SOC_DAIFMT_LEFT_J: 925 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK; 926 aif1 |= 0x8; 927 break; 928 default: 929 return -EINVAL; 930 } 931 932 /* Clock inversion */ 933 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 934 case SND_SOC_DAIFMT_DSP_A: 935 case SND_SOC_DAIFMT_DSP_B: 936 /* frame inversion not valid for DSP modes */ 937 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 938 case SND_SOC_DAIFMT_NB_NF: 939 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV; 940 break; 941 case SND_SOC_DAIFMT_IB_NF: 942 aif1 |= WM8900_REG_AUDIO1_BCLK_INV; 943 break; 944 default: 945 return -EINVAL; 946 } 947 break; 948 case SND_SOC_DAIFMT_I2S: 949 case SND_SOC_DAIFMT_RIGHT_J: 950 case SND_SOC_DAIFMT_LEFT_J: 951 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 952 case SND_SOC_DAIFMT_NB_NF: 953 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV; 954 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV; 955 break; 956 case SND_SOC_DAIFMT_IB_IF: 957 aif1 |= WM8900_REG_AUDIO1_BCLK_INV; 958 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV; 959 break; 960 case SND_SOC_DAIFMT_IB_NF: 961 aif1 |= WM8900_REG_AUDIO1_BCLK_INV; 962 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV; 963 break; 964 case SND_SOC_DAIFMT_NB_IF: 965 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV; 966 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV; 967 break; 968 default: 969 return -EINVAL; 970 } 971 break; 972 default: 973 return -EINVAL; 974 } 975 976 snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1); 977 snd_soc_write(codec, WM8900_REG_AUDIO1, aif1); 978 snd_soc_write(codec, WM8900_REG_AUDIO3, aif3); 979 snd_soc_write(codec, WM8900_REG_AUDIO4, aif4); 980 981 return 0; 982} 983 984static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute) 985{ 986 struct snd_soc_codec *codec = codec_dai->codec; 987 u16 reg; 988 989 reg = snd_soc_read(codec, WM8900_REG_DACCTRL); 990 991 if (mute) 992 reg |= WM8900_REG_DACCTRL_MUTE; 993 else 994 reg &= ~WM8900_REG_DACCTRL_MUTE; 995 996 snd_soc_write(codec, WM8900_REG_DACCTRL, reg); 997 998 return 0; 999} 1000 1001#define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 1002 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\ 1003 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 1004 1005#define WM8900_PCM_FORMATS \ 1006 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \ 1007 SNDRV_PCM_FORMAT_S24_LE) 1008 1009static struct snd_soc_dai_ops wm8900_dai_ops = { 1010 .hw_params = wm8900_hw_params, 1011 .set_clkdiv = wm8900_set_dai_clkdiv, 1012 .set_pll = wm8900_set_dai_pll, 1013 .set_fmt = wm8900_set_dai_fmt, 1014 .digital_mute = wm8900_digital_mute, 1015}; 1016 1017struct snd_soc_dai wm8900_dai = { 1018 .name = "WM8900 HiFi", 1019 .playback = { 1020 .stream_name = "HiFi Playback", 1021 .channels_min = 1, 1022 .channels_max = 2, 1023 .rates = WM8900_RATES, 1024 .formats = WM8900_PCM_FORMATS, 1025 }, 1026 .capture = { 1027 .stream_name = "HiFi Capture", 1028 .channels_min = 1, 1029 .channels_max = 2, 1030 .rates = WM8900_RATES, 1031 .formats = WM8900_PCM_FORMATS, 1032 }, 1033 .ops = &wm8900_dai_ops, 1034}; 1035EXPORT_SYMBOL_GPL(wm8900_dai); 1036 1037static int wm8900_set_bias_level(struct snd_soc_codec *codec, 1038 enum snd_soc_bias_level level) 1039{ 1040 u16 reg; 1041 1042 switch (level) { 1043 case SND_SOC_BIAS_ON: 1044 /* Enable thermal shutdown */ 1045 reg = snd_soc_read(codec, WM8900_REG_GPIO); 1046 snd_soc_write(codec, WM8900_REG_GPIO, 1047 reg | WM8900_REG_GPIO_TEMP_ENA); 1048 reg = snd_soc_read(codec, WM8900_REG_ADDCTL); 1049 snd_soc_write(codec, WM8900_REG_ADDCTL, 1050 reg | WM8900_REG_ADDCTL_TEMP_SD); 1051 break; 1052 1053 case SND_SOC_BIAS_PREPARE: 1054 break; 1055 1056 case SND_SOC_BIAS_STANDBY: 1057 /* Charge capacitors if initial power up */ 1058 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1059 /* STARTUP_BIAS_ENA on */ 1060 snd_soc_write(codec, WM8900_REG_POWER1, 1061 WM8900_REG_POWER1_STARTUP_BIAS_ENA); 1062 1063 /* Startup bias mode */ 1064 snd_soc_write(codec, WM8900_REG_ADDCTL, 1065 WM8900_REG_ADDCTL_BIAS_SRC | 1066 WM8900_REG_ADDCTL_VMID_SOFTST); 1067 1068 /* VMID 2x50k */ 1069 snd_soc_write(codec, WM8900_REG_POWER1, 1070 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1); 1071 1072 /* Allow capacitors to charge */ 1073 schedule_timeout_interruptible(msecs_to_jiffies(400)); 1074 1075 /* Enable bias */ 1076 snd_soc_write(codec, WM8900_REG_POWER1, 1077 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 1078 WM8900_REG_POWER1_BIAS_ENA | 0x1); 1079 1080 snd_soc_write(codec, WM8900_REG_ADDCTL, 0); 1081 1082 snd_soc_write(codec, WM8900_REG_POWER1, 1083 WM8900_REG_POWER1_BIAS_ENA | 0x1); 1084 } 1085 1086 reg = snd_soc_read(codec, WM8900_REG_POWER1); 1087 snd_soc_write(codec, WM8900_REG_POWER1, 1088 (reg & WM8900_REG_POWER1_FLL_ENA) | 1089 WM8900_REG_POWER1_BIAS_ENA | 0x1); 1090 snd_soc_write(codec, WM8900_REG_POWER2, 1091 WM8900_REG_POWER2_SYSCLK_ENA); 1092 snd_soc_write(codec, WM8900_REG_POWER3, 0); 1093 break; 1094 1095 case SND_SOC_BIAS_OFF: 1096 /* Startup bias enable */ 1097 reg = snd_soc_read(codec, WM8900_REG_POWER1); 1098 snd_soc_write(codec, WM8900_REG_POWER1, 1099 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA); 1100 snd_soc_write(codec, WM8900_REG_ADDCTL, 1101 WM8900_REG_ADDCTL_BIAS_SRC | 1102 WM8900_REG_ADDCTL_VMID_SOFTST); 1103 1104 /* Discharge caps */ 1105 snd_soc_write(codec, WM8900_REG_POWER1, 1106 WM8900_REG_POWER1_STARTUP_BIAS_ENA); 1107 schedule_timeout_interruptible(msecs_to_jiffies(500)); 1108 1109 /* Remove clamp */ 1110 snd_soc_write(codec, WM8900_REG_HPCTL1, 0); 1111 1112 /* Power down */ 1113 snd_soc_write(codec, WM8900_REG_ADDCTL, 0); 1114 snd_soc_write(codec, WM8900_REG_POWER1, 0); 1115 snd_soc_write(codec, WM8900_REG_POWER2, 0); 1116 snd_soc_write(codec, WM8900_REG_POWER3, 0); 1117 1118 /* Need to let things settle before stopping the clock 1119 * to ensure that restart works, see "Stopping the 1120 * master clock" in the datasheet. */ 1121 schedule_timeout_interruptible(msecs_to_jiffies(1)); 1122 snd_soc_write(codec, WM8900_REG_POWER2, 1123 WM8900_REG_POWER2_SYSCLK_ENA); 1124 break; 1125 } 1126 codec->bias_level = level; 1127 return 0; 1128} 1129 1130static int wm8900_suspend(struct platform_device *pdev, pm_message_t state) 1131{ 1132 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1133 struct snd_soc_codec *codec = socdev->card->codec; 1134 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec); 1135 int fll_out = wm8900->fll_out; 1136 int fll_in = wm8900->fll_in; 1137 int ret; 1138 1139 /* Stop the FLL in an orderly fashion */ 1140 ret = wm8900_set_fll(codec, 0, 0, 0); 1141 if (ret != 0) { 1142 dev_err(&pdev->dev, "Failed to stop FLL\n"); 1143 return ret; 1144 } 1145 1146 wm8900->fll_out = fll_out; 1147 wm8900->fll_in = fll_in; 1148 1149 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF); 1150 1151 return 0; 1152} 1153 1154static int wm8900_resume(struct platform_device *pdev) 1155{ 1156 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1157 struct snd_soc_codec *codec = socdev->card->codec; 1158 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec); 1159 u16 *cache; 1160 int i, ret; 1161 1162 cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults), 1163 GFP_KERNEL); 1164 1165 wm8900_reset(codec); 1166 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1167 1168 /* Restart the FLL? */ 1169 if (wm8900->fll_out) { 1170 int fll_out = wm8900->fll_out; 1171 int fll_in = wm8900->fll_in; 1172 1173 wm8900->fll_in = 0; 1174 wm8900->fll_out = 0; 1175 1176 ret = wm8900_set_fll(codec, 0, fll_in, fll_out); 1177 if (ret != 0) { 1178 dev_err(&pdev->dev, "Failed to restart FLL\n"); 1179 return ret; 1180 } 1181 } 1182 1183 if (cache) { 1184 for (i = 0; i < WM8900_MAXREG; i++) 1185 snd_soc_write(codec, i, cache[i]); 1186 kfree(cache); 1187 } else 1188 dev_err(&pdev->dev, "Unable to allocate register cache\n"); 1189 1190 return 0; 1191} 1192 1193static struct snd_soc_codec *wm8900_codec; 1194 1195static __devinit int wm8900_i2c_probe(struct i2c_client *i2c, 1196 const struct i2c_device_id *id) 1197{ 1198 struct wm8900_priv *wm8900; 1199 struct snd_soc_codec *codec; 1200 unsigned int reg; 1201 int ret; 1202 1203 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL); 1204 if (wm8900 == NULL) 1205 return -ENOMEM; 1206 1207 codec = &wm8900->codec; 1208 snd_soc_codec_set_drvdata(codec, wm8900); 1209 codec->reg_cache = &wm8900->reg_cache[0]; 1210 codec->reg_cache_size = WM8900_MAXREG; 1211 1212 mutex_init(&codec->mutex); 1213 INIT_LIST_HEAD(&codec->dapm_widgets); 1214 INIT_LIST_HEAD(&codec->dapm_paths); 1215 1216 codec->name = "WM8900"; 1217 codec->owner = THIS_MODULE; 1218 codec->dai = &wm8900_dai; 1219 codec->num_dai = 1; 1220 codec->control_data = i2c; 1221 codec->set_bias_level = wm8900_set_bias_level; 1222 codec->volatile_register = wm8900_volatile_register; 1223 codec->dev = &i2c->dev; 1224 1225 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); 1226 if (ret != 0) { 1227 dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret); 1228 goto err; 1229 } 1230 1231 reg = snd_soc_read(codec, WM8900_REG_ID); 1232 if (reg != 0x8900) { 1233 dev_err(&i2c->dev, "Device is not a WM8900 - ID %x\n", reg); 1234 ret = -ENODEV; 1235 goto err; 1236 } 1237 1238 wm8900_reset(codec); 1239 1240 /* Turn the chip on */ 1241 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1242 1243 /* Latch the volume update bits */ 1244 snd_soc_write(codec, WM8900_REG_LINVOL, 1245 snd_soc_read(codec, WM8900_REG_LINVOL) | 0x100); 1246 snd_soc_write(codec, WM8900_REG_RINVOL, 1247 snd_soc_read(codec, WM8900_REG_RINVOL) | 0x100); 1248 snd_soc_write(codec, WM8900_REG_LOUT1CTL, 1249 snd_soc_read(codec, WM8900_REG_LOUT1CTL) | 0x100); 1250 snd_soc_write(codec, WM8900_REG_ROUT1CTL, 1251 snd_soc_read(codec, WM8900_REG_ROUT1CTL) | 0x100); 1252 snd_soc_write(codec, WM8900_REG_LOUT2CTL, 1253 snd_soc_read(codec, WM8900_REG_LOUT2CTL) | 0x100); 1254 snd_soc_write(codec, WM8900_REG_ROUT2CTL, 1255 snd_soc_read(codec, WM8900_REG_ROUT2CTL) | 0x100); 1256 snd_soc_write(codec, WM8900_REG_LDAC_DV, 1257 snd_soc_read(codec, WM8900_REG_LDAC_DV) | 0x100); 1258 snd_soc_write(codec, WM8900_REG_RDAC_DV, 1259 snd_soc_read(codec, WM8900_REG_RDAC_DV) | 0x100); 1260 snd_soc_write(codec, WM8900_REG_LADC_DV, 1261 snd_soc_read(codec, WM8900_REG_LADC_DV) | 0x100); 1262 snd_soc_write(codec, WM8900_REG_RADC_DV, 1263 snd_soc_read(codec, WM8900_REG_RADC_DV) | 0x100); 1264 1265 /* Set the DAC and mixer output bias */ 1266 snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81); 1267 1268 wm8900_dai.dev = &i2c->dev; 1269 1270 wm8900_codec = codec; 1271 1272 ret = snd_soc_register_codec(codec); 1273 if (ret != 0) { 1274 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret); 1275 goto err; 1276 } 1277 1278 ret = snd_soc_register_dai(&wm8900_dai); 1279 if (ret != 0) { 1280 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret); 1281 goto err_codec; 1282 } 1283 1284 return ret; 1285 1286err_codec: 1287 snd_soc_unregister_codec(codec); 1288err: 1289 kfree(wm8900); 1290 wm8900_codec = NULL; 1291 return ret; 1292} 1293 1294static __devexit int wm8900_i2c_remove(struct i2c_client *client) 1295{ 1296 snd_soc_unregister_dai(&wm8900_dai); 1297 snd_soc_unregister_codec(wm8900_codec); 1298 1299 wm8900_set_bias_level(wm8900_codec, SND_SOC_BIAS_OFF); 1300 1301 wm8900_dai.dev = NULL; 1302 kfree(snd_soc_codec_get_drvdata(wm8900_codec)); 1303 wm8900_codec = NULL; 1304 1305 return 0; 1306} 1307 1308static const struct i2c_device_id wm8900_i2c_id[] = { 1309 { "wm8900", 0 }, 1310 { } 1311}; 1312MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id); 1313 1314static struct i2c_driver wm8900_i2c_driver = { 1315 .driver = { 1316 .name = "WM8900", 1317 .owner = THIS_MODULE, 1318 }, 1319 .probe = wm8900_i2c_probe, 1320 .remove = __devexit_p(wm8900_i2c_remove), 1321 .id_table = wm8900_i2c_id, 1322}; 1323 1324static int wm8900_probe(struct platform_device *pdev) 1325{ 1326 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1327 struct snd_soc_codec *codec; 1328 int ret = 0; 1329 1330 if (!wm8900_codec) { 1331 dev_err(&pdev->dev, "I2C client not yet instantiated\n"); 1332 return -ENODEV; 1333 } 1334 1335 codec = wm8900_codec; 1336 socdev->card->codec = codec; 1337 1338 /* Register pcms */ 1339 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 1340 if (ret < 0) { 1341 dev_err(&pdev->dev, "Failed to register new PCMs\n"); 1342 goto pcm_err; 1343 } 1344 1345 snd_soc_add_controls(codec, wm8900_snd_controls, 1346 ARRAY_SIZE(wm8900_snd_controls)); 1347 wm8900_add_widgets(codec); 1348 1349pcm_err: 1350 return ret; 1351} 1352 1353/* power down chip */ 1354static int wm8900_remove(struct platform_device *pdev) 1355{ 1356 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1357 1358 snd_soc_free_pcms(socdev); 1359 snd_soc_dapm_free(socdev); 1360 1361 return 0; 1362} 1363 1364struct snd_soc_codec_device soc_codec_dev_wm8900 = { 1365 .probe = wm8900_probe, 1366 .remove = wm8900_remove, 1367 .suspend = wm8900_suspend, 1368 .resume = wm8900_resume, 1369}; 1370EXPORT_SYMBOL_GPL(soc_codec_dev_wm8900); 1371 1372static int __init wm8900_modinit(void) 1373{ 1374 return i2c_add_driver(&wm8900_i2c_driver); 1375} 1376module_init(wm8900_modinit); 1377 1378static void __exit wm8900_exit(void) 1379{ 1380 i2c_del_driver(&wm8900_i2c_driver); 1381} 1382module_exit(wm8900_exit); 1383 1384MODULE_DESCRIPTION("ASoC WM8900 driver"); 1385MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>"); 1386MODULE_LICENSE("GPL"); 1387