1/* 2 * C-Media CMI8788 driver - main driver module 3 * 4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de> 5 * 6 * 7 * This driver is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License, version 2. 9 * 10 * This driver is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this driver; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20#include <linux/delay.h> 21#include <linux/interrupt.h> 22#include <linux/mutex.h> 23#include <linux/pci.h> 24#include <linux/slab.h> 25#include <sound/ac97_codec.h> 26#include <sound/asoundef.h> 27#include <sound/core.h> 28#include <sound/info.h> 29#include <sound/mpu401.h> 30#include <sound/pcm.h> 31#include "oxygen.h" 32#include "cm9780.h" 33 34MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); 35MODULE_DESCRIPTION("C-Media CMI8788 helper library"); 36MODULE_LICENSE("GPL v2"); 37 38#define DRIVER "oxygen" 39 40static inline int oxygen_uart_input_ready(struct oxygen *chip) 41{ 42 return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY); 43} 44 45static void oxygen_read_uart(struct oxygen *chip) 46{ 47 if (unlikely(!oxygen_uart_input_ready(chip))) { 48 /* no data, but read it anyway to clear the interrupt */ 49 oxygen_read8(chip, OXYGEN_MPU401); 50 return; 51 } 52 do { 53 u8 data = oxygen_read8(chip, OXYGEN_MPU401); 54 if (data == MPU401_ACK) 55 continue; 56 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input)) 57 chip->uart_input_count = 0; 58 chip->uart_input[chip->uart_input_count++] = data; 59 } while (oxygen_uart_input_ready(chip)); 60 if (chip->model.uart_input) 61 chip->model.uart_input(chip); 62} 63 64static irqreturn_t oxygen_interrupt(int dummy, void *dev_id) 65{ 66 struct oxygen *chip = dev_id; 67 unsigned int status, clear, elapsed_streams, i; 68 69 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS); 70 if (!status) 71 return IRQ_NONE; 72 73 spin_lock(&chip->reg_lock); 74 75 clear = status & (OXYGEN_CHANNEL_A | 76 OXYGEN_CHANNEL_B | 77 OXYGEN_CHANNEL_C | 78 OXYGEN_CHANNEL_SPDIF | 79 OXYGEN_CHANNEL_MULTICH | 80 OXYGEN_CHANNEL_AC97 | 81 OXYGEN_INT_SPDIF_IN_DETECT | 82 OXYGEN_INT_GPIO | 83 OXYGEN_INT_AC97); 84 if (clear) { 85 if (clear & OXYGEN_INT_SPDIF_IN_DETECT) 86 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT; 87 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 88 chip->interrupt_mask & ~clear); 89 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 90 chip->interrupt_mask); 91 } 92 93 elapsed_streams = status & chip->pcm_running; 94 95 spin_unlock(&chip->reg_lock); 96 97 for (i = 0; i < PCM_COUNT; ++i) 98 if ((elapsed_streams & (1 << i)) && chip->streams[i]) 99 snd_pcm_period_elapsed(chip->streams[i]); 100 101 if (status & OXYGEN_INT_SPDIF_IN_DETECT) { 102 spin_lock(&chip->reg_lock); 103 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); 104 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT | 105 OXYGEN_SPDIF_RATE_INT)) { 106 /* write the interrupt bit(s) to clear */ 107 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i); 108 schedule_work(&chip->spdif_input_bits_work); 109 } 110 spin_unlock(&chip->reg_lock); 111 } 112 113 if (status & OXYGEN_INT_GPIO) 114 schedule_work(&chip->gpio_work); 115 116 if (status & OXYGEN_INT_MIDI) { 117 if (chip->midi) 118 snd_mpu401_uart_interrupt(0, chip->midi->private_data); 119 else 120 oxygen_read_uart(chip); 121 } 122 123 if (status & OXYGEN_INT_AC97) 124 wake_up(&chip->ac97_waitqueue); 125 126 return IRQ_HANDLED; 127} 128 129static void oxygen_spdif_input_bits_changed(struct work_struct *work) 130{ 131 struct oxygen *chip = container_of(work, struct oxygen, 132 spdif_input_bits_work); 133 u32 reg; 134 135 /* 136 * This function gets called when there is new activity on the SPDIF 137 * input, or when we lose lock on the input signal, or when the rate 138 * changes. 139 */ 140 msleep(1); 141 spin_lock_irq(&chip->reg_lock); 142 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); 143 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS | 144 OXYGEN_SPDIF_LOCK_STATUS)) 145 == OXYGEN_SPDIF_SENSE_STATUS) { 146 /* 147 * If we detect activity on the SPDIF input but cannot lock to 148 * a signal, the clock bit is likely to be wrong. 149 */ 150 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK; 151 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg); 152 spin_unlock_irq(&chip->reg_lock); 153 msleep(1); 154 spin_lock_irq(&chip->reg_lock); 155 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); 156 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS | 157 OXYGEN_SPDIF_LOCK_STATUS)) 158 == OXYGEN_SPDIF_SENSE_STATUS) { 159 /* nothing detected with either clock; give up */ 160 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK) 161 == OXYGEN_SPDIF_IN_CLOCK_192) { 162 /* 163 * Reset clock to <= 96 kHz because this is 164 * more likely to be received next time. 165 */ 166 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK; 167 reg |= OXYGEN_SPDIF_IN_CLOCK_96; 168 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg); 169 } 170 } 171 } 172 spin_unlock_irq(&chip->reg_lock); 173 174 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) { 175 spin_lock_irq(&chip->reg_lock); 176 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT; 177 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 178 chip->interrupt_mask); 179 spin_unlock_irq(&chip->reg_lock); 180 181 /* 182 * We don't actually know that any channel status bits have 183 * changed, but let's send a notification just to be sure. 184 */ 185 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 186 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id); 187 } 188} 189 190static void oxygen_gpio_changed(struct work_struct *work) 191{ 192 struct oxygen *chip = container_of(work, struct oxygen, gpio_work); 193 194 if (chip->model.gpio_changed) 195 chip->model.gpio_changed(chip); 196} 197 198#ifdef CONFIG_PROC_FS 199static void oxygen_proc_read(struct snd_info_entry *entry, 200 struct snd_info_buffer *buffer) 201{ 202 struct oxygen *chip = entry->private_data; 203 int i, j; 204 205 snd_iprintf(buffer, "CMI8788\n\n"); 206 for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) { 207 snd_iprintf(buffer, "%02x:", i); 208 for (j = 0; j < 0x10; ++j) 209 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j)); 210 snd_iprintf(buffer, "\n"); 211 } 212 if (mutex_lock_interruptible(&chip->mutex) < 0) 213 return; 214 if (chip->has_ac97_0) { 215 snd_iprintf(buffer, "\nAC97\n"); 216 for (i = 0; i < 0x80; i += 0x10) { 217 snd_iprintf(buffer, "%02x:", i); 218 for (j = 0; j < 0x10; j += 2) 219 snd_iprintf(buffer, " %04x", 220 oxygen_read_ac97(chip, 0, i + j)); 221 snd_iprintf(buffer, "\n"); 222 } 223 } 224 if (chip->has_ac97_1) { 225 snd_iprintf(buffer, "\nAC97 2\n"); 226 for (i = 0; i < 0x80; i += 0x10) { 227 snd_iprintf(buffer, "%02x:", i); 228 for (j = 0; j < 0x10; j += 2) 229 snd_iprintf(buffer, " %04x", 230 oxygen_read_ac97(chip, 1, i + j)); 231 snd_iprintf(buffer, "\n"); 232 } 233 } 234 mutex_unlock(&chip->mutex); 235} 236 237static void oxygen_proc_init(struct oxygen *chip) 238{ 239 struct snd_info_entry *entry; 240 241 if (!snd_card_proc_new(chip->card, "cmi8788", &entry)) 242 snd_info_set_text_ops(entry, chip, oxygen_proc_read); 243} 244#else 245#define oxygen_proc_init(chip) 246#endif 247 248static const struct pci_device_id * 249oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[]) 250{ 251 u16 subdevice; 252 253 /* 254 * Make sure the EEPROM pins are available, i.e., not used for SPI. 255 * (This function is called before we initialize or use SPI.) 256 */ 257 oxygen_clear_bits8(chip, OXYGEN_FUNCTION, 258 OXYGEN_FUNCTION_ENABLE_SPI_4_5); 259 /* 260 * Read the subsystem device ID directly from the EEPROM, because the 261 * chip didn't if the first EEPROM word was overwritten. 262 */ 263 subdevice = oxygen_read_eeprom(chip, 2); 264 /* use default ID if EEPROM is missing */ 265 if (subdevice == 0xffff) 266 subdevice = 0x8788; 267 /* 268 * We use only the subsystem device ID for searching because it is 269 * unique even without the subsystem vendor ID, which may have been 270 * overwritten in the EEPROM. 271 */ 272 for (; ids->vendor; ++ids) 273 if (ids->subdevice == subdevice && 274 ids->driver_data != BROKEN_EEPROM_DRIVER_DATA) 275 return ids; 276 return NULL; 277} 278 279static void oxygen_restore_eeprom(struct oxygen *chip, 280 const struct pci_device_id *id) 281{ 282 u16 eeprom_id; 283 284 eeprom_id = oxygen_read_eeprom(chip, 0); 285 if (eeprom_id != OXYGEN_EEPROM_ID && 286 (eeprom_id != 0xffff || id->subdevice != 0x8788)) { 287 /* 288 * This function gets called only when a known card model has 289 * been detected, i.e., we know there is a valid subsystem 290 * product ID at index 2 in the EEPROM. Therefore, we have 291 * been able to deduce the correct subsystem vendor ID, and 292 * this is enough information to restore the original EEPROM 293 * contents. 294 */ 295 oxygen_write_eeprom(chip, 1, id->subvendor); 296 oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID); 297 298 oxygen_set_bits8(chip, OXYGEN_MISC, 299 OXYGEN_MISC_WRITE_PCI_SUBID); 300 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, 301 id->subvendor); 302 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID, 303 id->subdevice); 304 oxygen_clear_bits8(chip, OXYGEN_MISC, 305 OXYGEN_MISC_WRITE_PCI_SUBID); 306 307 snd_printk(KERN_INFO "EEPROM ID restored\n"); 308 } 309} 310 311static void pci_bridge_magic(void) 312{ 313 struct pci_dev *pci = NULL; 314 u32 tmp; 315 316 for (;;) { 317 /* If there is any Pericom PI7C9X110 PCI-E/PCI bridge ... */ 318 pci = pci_get_device(0x12d8, 0xe110, pci); 319 if (!pci) 320 break; 321 /* 322 * ... configure its secondary internal arbiter to park to 323 * the secondary port, instead of to the last master. 324 */ 325 if (!pci_read_config_dword(pci, 0x40, &tmp)) { 326 tmp |= 1; 327 pci_write_config_dword(pci, 0x40, tmp); 328 } 329 /* Why? Try asking C-Media. */ 330 } 331} 332 333static void oxygen_init(struct oxygen *chip) 334{ 335 unsigned int i; 336 337 chip->dac_routing = 1; 338 for (i = 0; i < 8; ++i) 339 chip->dac_volume[i] = chip->model.dac_volume_min; 340 chip->dac_mute = 1; 341 chip->spdif_playback_enable = 1; 342 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL | 343 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT); 344 chip->spdif_pcm_bits = chip->spdif_bits; 345 346 if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2) 347 chip->revision = 2; 348 else 349 chip->revision = 1; 350 351 if (chip->revision == 1) 352 oxygen_set_bits8(chip, OXYGEN_MISC, 353 OXYGEN_MISC_PCI_MEM_W_1_CLOCK); 354 355 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL); 356 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0; 357 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0; 358 359 oxygen_write8_masked(chip, OXYGEN_FUNCTION, 360 OXYGEN_FUNCTION_RESET_CODEC | 361 chip->model.function_flags, 362 OXYGEN_FUNCTION_RESET_CODEC | 363 OXYGEN_FUNCTION_2WIRE_SPI_MASK | 364 OXYGEN_FUNCTION_ENABLE_SPI_4_5); 365 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0); 366 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0); 367 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS, 368 OXYGEN_PLAY_CHANNELS_2 | 369 OXYGEN_DMA_A_BURST_8 | 370 OXYGEN_DMA_MULTICH_BURST_8); 371 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); 372 oxygen_write8_masked(chip, OXYGEN_MISC, 373 chip->model.misc_flags, 374 OXYGEN_MISC_WRITE_PCI_SUBID | 375 OXYGEN_MISC_REC_C_FROM_SPDIF | 376 OXYGEN_MISC_REC_B_FROM_AC97 | 377 OXYGEN_MISC_REC_A_FROM_MULTICH | 378 OXYGEN_MISC_MIDI); 379 oxygen_write8(chip, OXYGEN_REC_FORMAT, 380 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) | 381 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) | 382 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT)); 383 oxygen_write8(chip, OXYGEN_PLAY_FORMAT, 384 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) | 385 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT)); 386 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2); 387 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT, 388 OXYGEN_RATE_48000 | chip->model.dac_i2s_format | 389 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 | 390 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); 391 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1) 392 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, 393 OXYGEN_RATE_48000 | chip->model.adc_i2s_format | 394 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 | 395 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); 396 else 397 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, 398 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK); 399 if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 | 400 CAPTURE_2_FROM_I2S_2)) 401 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, 402 OXYGEN_RATE_48000 | chip->model.adc_i2s_format | 403 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 | 404 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); 405 else 406 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, 407 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK); 408 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT, 409 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK); 410 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, 411 OXYGEN_SPDIF_OUT_ENABLE | 412 OXYGEN_SPDIF_LOOPBACK); 413 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) 414 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL, 415 OXYGEN_SPDIF_SENSE_MASK | 416 OXYGEN_SPDIF_LOCK_MASK | 417 OXYGEN_SPDIF_RATE_MASK | 418 OXYGEN_SPDIF_LOCK_PAR | 419 OXYGEN_SPDIF_IN_CLOCK_96, 420 OXYGEN_SPDIF_SENSE_MASK | 421 OXYGEN_SPDIF_LOCK_MASK | 422 OXYGEN_SPDIF_RATE_MASK | 423 OXYGEN_SPDIF_SENSE_PAR | 424 OXYGEN_SPDIF_LOCK_PAR | 425 OXYGEN_SPDIF_IN_CLOCK_MASK); 426 else 427 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, 428 OXYGEN_SPDIF_SENSE_MASK | 429 OXYGEN_SPDIF_LOCK_MASK | 430 OXYGEN_SPDIF_RATE_MASK); 431 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits); 432 oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS, 433 OXYGEN_2WIRE_LENGTH_8 | 434 OXYGEN_2WIRE_INTERRUPT_MASK | 435 OXYGEN_2WIRE_SPEED_STANDARD); 436 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK); 437 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0); 438 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0); 439 oxygen_write16(chip, OXYGEN_PLAY_ROUTING, 440 OXYGEN_PLAY_MULTICH_I2S_DAC | 441 OXYGEN_PLAY_SPDIF_SPDIF | 442 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) | 443 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) | 444 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) | 445 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT)); 446 oxygen_write8(chip, OXYGEN_REC_ROUTING, 447 OXYGEN_REC_A_ROUTE_I2S_ADC_1 | 448 OXYGEN_REC_B_ROUTE_I2S_ADC_2 | 449 OXYGEN_REC_C_ROUTE_SPDIF); 450 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0); 451 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING, 452 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) | 453 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) | 454 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) | 455 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT)); 456 457 if (chip->has_ac97_0 | chip->has_ac97_1) 458 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 459 OXYGEN_AC97_INT_READ_DONE | 460 OXYGEN_AC97_INT_WRITE_DONE); 461 else 462 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0); 463 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0); 464 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0); 465 if (!(chip->has_ac97_0 | chip->has_ac97_1)) 466 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL, 467 OXYGEN_AC97_CLOCK_DISABLE); 468 if (!chip->has_ac97_0) { 469 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL, 470 OXYGEN_AC97_NO_CODEC_0); 471 } else { 472 oxygen_write_ac97(chip, 0, AC97_RESET, 0); 473 msleep(1); 474 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP, 475 CM9780_GPIO0IO | CM9780_GPIO1IO); 476 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER, 477 CM9780_BSTSEL | CM9780_STRO_MIC | 478 CM9780_MIX2FR | CM9780_PCBSW); 479 oxygen_ac97_set_bits(chip, 0, CM9780_JACK, 480 CM9780_RSOE | CM9780_CBOE | 481 CM9780_SSOE | CM9780_FROE | 482 CM9780_MIC2MIC | CM9780_LI2LI); 483 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000); 484 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000); 485 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808); 486 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808); 487 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808); 488 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808); 489 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808); 490 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000); 491 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080); 492 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080); 493 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS, 494 CM9780_GPO0); 495 /* power down unused ADCs and DACs */ 496 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN, 497 AC97_PD_PR0 | AC97_PD_PR1); 498 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS, 499 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK); 500 } 501 if (chip->has_ac97_1) { 502 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG, 503 OXYGEN_AC97_CODEC1_SLOT3 | 504 OXYGEN_AC97_CODEC1_SLOT4); 505 oxygen_write_ac97(chip, 1, AC97_RESET, 0); 506 msleep(1); 507 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000); 508 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000); 509 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000); 510 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808); 511 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808); 512 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808); 513 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808); 514 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808); 515 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808); 516 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000); 517 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000); 518 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040); 519 } 520} 521 522static void oxygen_shutdown(struct oxygen *chip) 523{ 524 spin_lock_irq(&chip->reg_lock); 525 chip->interrupt_mask = 0; 526 chip->pcm_running = 0; 527 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0); 528 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); 529 spin_unlock_irq(&chip->reg_lock); 530} 531 532static void oxygen_card_free(struct snd_card *card) 533{ 534 struct oxygen *chip = card->private_data; 535 536 oxygen_shutdown(chip); 537 if (chip->irq >= 0) 538 free_irq(chip->irq, chip); 539 flush_scheduled_work(); 540 chip->model.cleanup(chip); 541 kfree(chip->model_data); 542 mutex_destroy(&chip->mutex); 543 pci_release_regions(chip->pci); 544 pci_disable_device(chip->pci); 545} 546 547int oxygen_pci_probe(struct pci_dev *pci, int index, char *id, 548 struct module *owner, 549 const struct pci_device_id *ids, 550 int (*get_model)(struct oxygen *chip, 551 const struct pci_device_id *id 552 ) 553 ) 554{ 555 struct snd_card *card; 556 struct oxygen *chip; 557 const struct pci_device_id *pci_id; 558 int err; 559 560 err = snd_card_create(index, id, owner, sizeof(*chip), &card); 561 if (err < 0) 562 return err; 563 564 chip = card->private_data; 565 chip->card = card; 566 chip->pci = pci; 567 chip->irq = -1; 568 spin_lock_init(&chip->reg_lock); 569 mutex_init(&chip->mutex); 570 INIT_WORK(&chip->spdif_input_bits_work, 571 oxygen_spdif_input_bits_changed); 572 INIT_WORK(&chip->gpio_work, oxygen_gpio_changed); 573 init_waitqueue_head(&chip->ac97_waitqueue); 574 575 err = pci_enable_device(pci); 576 if (err < 0) 577 goto err_card; 578 579 err = pci_request_regions(pci, DRIVER); 580 if (err < 0) { 581 snd_printk(KERN_ERR "cannot reserve PCI resources\n"); 582 goto err_pci_enable; 583 } 584 585 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) || 586 pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) { 587 snd_printk(KERN_ERR "invalid PCI I/O range\n"); 588 err = -ENXIO; 589 goto err_pci_regions; 590 } 591 chip->addr = pci_resource_start(pci, 0); 592 593 pci_id = oxygen_search_pci_id(chip, ids); 594 if (!pci_id) { 595 err = -ENODEV; 596 goto err_pci_regions; 597 } 598 oxygen_restore_eeprom(chip, pci_id); 599 err = get_model(chip, pci_id); 600 if (err < 0) 601 goto err_pci_regions; 602 603 if (chip->model.model_data_size) { 604 chip->model_data = kzalloc(chip->model.model_data_size, 605 GFP_KERNEL); 606 if (!chip->model_data) { 607 err = -ENOMEM; 608 goto err_pci_regions; 609 } 610 } 611 612 pci_set_master(pci); 613 snd_card_set_dev(card, &pci->dev); 614 card->private_free = oxygen_card_free; 615 616 pci_bridge_magic(); 617 oxygen_init(chip); 618 chip->model.init(chip); 619 620 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED, 621 DRIVER, chip); 622 if (err < 0) { 623 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq); 624 goto err_card; 625 } 626 chip->irq = pci->irq; 627 628 strcpy(card->driver, chip->model.chip); 629 strcpy(card->shortname, chip->model.shortname); 630 sprintf(card->longname, "%s (rev %u) at %#lx, irq %i", 631 chip->model.longname, chip->revision, chip->addr, chip->irq); 632 strcpy(card->mixername, chip->model.chip); 633 snd_component_add(card, chip->model.chip); 634 635 err = oxygen_pcm_init(chip); 636 if (err < 0) 637 goto err_card; 638 639 err = oxygen_mixer_init(chip); 640 if (err < 0) 641 goto err_card; 642 643 if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) { 644 unsigned int info_flags = MPU401_INFO_INTEGRATED; 645 if (chip->model.device_config & MIDI_OUTPUT) 646 info_flags |= MPU401_INFO_OUTPUT; 647 if (chip->model.device_config & MIDI_INPUT) 648 info_flags |= MPU401_INFO_INPUT; 649 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI, 650 chip->addr + OXYGEN_MPU401, 651 info_flags, 0, 0, 652 &chip->midi); 653 if (err < 0) 654 goto err_card; 655 } 656 657 oxygen_proc_init(chip); 658 659 spin_lock_irq(&chip->reg_lock); 660 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) 661 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT; 662 if (chip->has_ac97_0 | chip->has_ac97_1) 663 chip->interrupt_mask |= OXYGEN_INT_AC97; 664 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); 665 spin_unlock_irq(&chip->reg_lock); 666 667 err = snd_card_register(card); 668 if (err < 0) 669 goto err_card; 670 671 pci_set_drvdata(pci, card); 672 return 0; 673 674err_pci_regions: 675 pci_release_regions(pci); 676err_pci_enable: 677 pci_disable_device(pci); 678err_card: 679 snd_card_free(card); 680 return err; 681} 682EXPORT_SYMBOL(oxygen_pci_probe); 683 684void oxygen_pci_remove(struct pci_dev *pci) 685{ 686 snd_card_free(pci_get_drvdata(pci)); 687 pci_set_drvdata(pci, NULL); 688} 689EXPORT_SYMBOL(oxygen_pci_remove); 690 691#ifdef CONFIG_PM 692int oxygen_pci_suspend(struct pci_dev *pci, pm_message_t state) 693{ 694 struct snd_card *card = pci_get_drvdata(pci); 695 struct oxygen *chip = card->private_data; 696 unsigned int i, saved_interrupt_mask; 697 698 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 699 700 for (i = 0; i < PCM_COUNT; ++i) 701 if (chip->streams[i]) 702 snd_pcm_suspend(chip->streams[i]); 703 704 if (chip->model.suspend) 705 chip->model.suspend(chip); 706 707 spin_lock_irq(&chip->reg_lock); 708 saved_interrupt_mask = chip->interrupt_mask; 709 chip->interrupt_mask = 0; 710 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0); 711 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); 712 spin_unlock_irq(&chip->reg_lock); 713 714 synchronize_irq(chip->irq); 715 flush_scheduled_work(); 716 chip->interrupt_mask = saved_interrupt_mask; 717 718 pci_disable_device(pci); 719 pci_save_state(pci); 720 pci_set_power_state(pci, pci_choose_state(pci, state)); 721 return 0; 722} 723EXPORT_SYMBOL(oxygen_pci_suspend); 724 725static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = { 726 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff, 727 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000 728}; 729static const u32 ac97_registers_to_restore[2][0x40 / 32] = { 730 { 0x18284fa2, 0x03060000 }, 731 { 0x00007fa6, 0x00200000 } 732}; 733 734static inline int is_bit_set(const u32 *bitmap, unsigned int bit) 735{ 736 return bitmap[bit / 32] & (1 << (bit & 31)); 737} 738 739static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec) 740{ 741 unsigned int i; 742 743 oxygen_write_ac97(chip, codec, AC97_RESET, 0); 744 msleep(1); 745 for (i = 1; i < 0x40; ++i) 746 if (is_bit_set(ac97_registers_to_restore[codec], i)) 747 oxygen_write_ac97(chip, codec, i * 2, 748 chip->saved_ac97_registers[codec][i]); 749} 750 751int oxygen_pci_resume(struct pci_dev *pci) 752{ 753 struct snd_card *card = pci_get_drvdata(pci); 754 struct oxygen *chip = card->private_data; 755 unsigned int i; 756 757 pci_set_power_state(pci, PCI_D0); 758 pci_restore_state(pci); 759 if (pci_enable_device(pci) < 0) { 760 snd_printk(KERN_ERR "cannot reenable device"); 761 snd_card_disconnect(card); 762 return -EIO; 763 } 764 pci_set_master(pci); 765 766 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0); 767 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); 768 for (i = 0; i < OXYGEN_IO_SIZE; ++i) 769 if (is_bit_set(registers_to_restore, i)) 770 oxygen_write8(chip, i, chip->saved_registers._8[i]); 771 if (chip->has_ac97_0) 772 oxygen_restore_ac97(chip, 0); 773 if (chip->has_ac97_1) 774 oxygen_restore_ac97(chip, 1); 775 776 if (chip->model.resume) 777 chip->model.resume(chip); 778 779 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); 780 781 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 782 return 0; 783} 784EXPORT_SYMBOL(oxygen_pci_resume); 785#endif /* CONFIG_PM */ 786 787void oxygen_pci_shutdown(struct pci_dev *pci) 788{ 789 struct snd_card *card = pci_get_drvdata(pci); 790 struct oxygen *chip = card->private_data; 791 792 oxygen_shutdown(chip); 793 chip->model.cleanup(chip); 794} 795EXPORT_SYMBOL(oxygen_pci_shutdown); 796