1/* 2 * ALSA driver for Intel ICH (i8x0) chipsets 3 * 4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz> 5 * 6 * 7 * This code also contains alpha support for SiS 735 chipsets provided 8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet 9 * for SiS735, so the code is not fully functional. 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 26 * 27 */ 28 29#include <asm/io.h> 30#include <linux/delay.h> 31#include <linux/interrupt.h> 32#include <linux/init.h> 33#include <linux/pci.h> 34#include <linux/slab.h> 35#include <linux/moduleparam.h> 36#include <sound/core.h> 37#include <sound/pcm.h> 38#include <sound/ac97_codec.h> 39#include <sound/info.h> 40#include <sound/initval.h> 41#include <asm/pgtable.h> 42#include <asm/cacheflush.h> 43 44MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>"); 45MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455"); 46MODULE_LICENSE("GPL"); 47MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH}," 48 "{Intel,82901AB-ICH0}," 49 "{Intel,82801BA-ICH2}," 50 "{Intel,82801CA-ICH3}," 51 "{Intel,82801DB-ICH4}," 52 "{Intel,ICH5}," 53 "{Intel,ICH6}," 54 "{Intel,ICH7}," 55 "{Intel,6300ESB}," 56 "{Intel,ESB2}," 57 "{Intel,MX440}," 58 "{SiS,SI7012}," 59 "{NVidia,nForce Audio}," 60 "{NVidia,nForce2 Audio}," 61 "{NVidia,nForce3 Audio}," 62 "{NVidia,MCP04}," 63 "{NVidia,MCP501}," 64 "{NVidia,CK804}," 65 "{NVidia,CK8}," 66 "{NVidia,CK8S}," 67 "{AMD,AMD768}," 68 "{AMD,AMD8111}," 69 "{ALI,M5455}}"); 70 71static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ 72static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ 73static int ac97_clock; 74static char *ac97_quirk; 75static int buggy_semaphore; 76static int buggy_irq = -1; /* auto-check */ 77static int xbox; 78static int spdif_aclink = -1; 79 80module_param(index, int, 0444); 81MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard."); 82module_param(id, charp, 0444); 83MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard."); 84module_param(ac97_clock, int, 0444); 85MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect)."); 86module_param(ac97_quirk, charp, 0444); 87MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); 88module_param(buggy_semaphore, bool, 0444); 89MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores."); 90module_param(buggy_irq, bool, 0444); 91MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards."); 92module_param(xbox, bool, 0444); 93MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection."); 94module_param(spdif_aclink, int, 0444); 95MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link."); 96 97/* just for backward compatibility */ 98static int enable; 99module_param(enable, bool, 0444); 100static int joystick; 101module_param(joystick, int, 0444); 102 103/* 104 * Direct registers 105 */ 106enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; 107 108#define ICHREG(x) ICH_REG_##x 109 110#define DEFINE_REGSET(name,base) \ 111enum { \ 112 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ 113 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ 114 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ 115 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ 116 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ 117 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ 118 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ 119}; 120 121/* busmaster blocks */ 122DEFINE_REGSET(OFF, 0); /* offset */ 123DEFINE_REGSET(PI, 0x00); /* PCM in */ 124DEFINE_REGSET(PO, 0x10); /* PCM out */ 125DEFINE_REGSET(MC, 0x20); /* Mic in */ 126 127/* ICH4 busmaster blocks */ 128DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */ 129DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */ 130DEFINE_REGSET(SP, 0x60); /* SPDIF out */ 131 132/* values for each busmaster block */ 133 134/* LVI */ 135#define ICH_REG_LVI_MASK 0x1f 136 137/* SR */ 138#define ICH_FIFOE 0x10 /* FIFO error */ 139#define ICH_BCIS 0x08 /* buffer completion interrupt status */ 140#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ 141#define ICH_CELV 0x02 /* current equals last valid */ 142#define ICH_DCH 0x01 /* DMA controller halted */ 143 144/* PIV */ 145#define ICH_REG_PIV_MASK 0x1f /* mask */ 146 147/* CR */ 148#define ICH_IOCE 0x10 /* interrupt on completion enable */ 149#define ICH_FEIE 0x08 /* fifo error interrupt enable */ 150#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ 151#define ICH_RESETREGS 0x02 /* reset busmaster registers */ 152#define ICH_STARTBM 0x01 /* start busmaster operation */ 153 154 155/* global block */ 156#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */ 157#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */ 158#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */ 159#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */ 160#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */ 161#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */ 162#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */ 163#define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */ 164#define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */ 165#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */ 166#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */ 167#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */ 168#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */ 169#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */ 170#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */ 171#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */ 172#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ 173#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ 174#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ 175#define ICH_ACLINK 0x00000008 /* AClink shut off */ 176#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ 177#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ 178#define ICH_GIE 0x00000001 /* GPI interrupt enable */ 179#define ICH_REG_GLOB_STA 0x30 /* dword - global status */ 180#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ 181#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ 182#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ 183#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ 184#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ 185#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ 186#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ 187#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */ 188#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 189#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */ 190#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */ 191#define ICH_MD3 0x00020000 /* modem power down semaphore */ 192#define ICH_AD3 0x00010000 /* audio power down semaphore */ 193#define ICH_RCS 0x00008000 /* read completion status */ 194#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ 195#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ 196#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ 197#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ 198#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ 199#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ 200#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ 201#define ICH_MCINT 0x00000080 /* MIC capture interrupt */ 202#define ICH_POINT 0x00000040 /* playback interrupt */ 203#define ICH_PIINT 0x00000020 /* capture interrupt */ 204#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ 205#define ICH_MOINT 0x00000004 /* modem playback interrupt */ 206#define ICH_MIINT 0x00000002 /* modem capture interrupt */ 207#define ICH_GSCI 0x00000001 /* GPI status change interrupt */ 208#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */ 209#define ICH_CAS 0x01 /* codec access semaphore */ 210#define ICH_REG_SDM 0x80 211#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */ 212#define ICH_DI2L_SHIFT 6 213#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */ 214#define ICH_DI1L_SHIFT 4 215#define ICH_SE 0x00000008 /* steer enable */ 216#define ICH_LDI_MASK 0x00000003 /* last codec read data input */ 217 218#define ICH_MAX_FRAGS 32 /* max hw frags */ 219 220 221/* 222 * registers for Ali5455 223 */ 224 225/* ALi 5455 busmaster blocks */ 226DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */ 227DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */ 228DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */ 229DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */ 230DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */ 231DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */ 232DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */ 233DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */ 234DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */ 235DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */ 236DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */ 237 238enum { 239 ICH_REG_ALI_SCR = 0x00, /* System Control Register */ 240 ICH_REG_ALI_SSR = 0x04, /* System Status Register */ 241 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */ 242 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */ 243 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */ 244 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */ 245 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */ 246 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */ 247 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */ 248 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */ 249 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */ 250 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */ 251 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */ 252 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */ 253 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */ 254 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */ 255 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */ 256 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */ 257 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */ 258 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */ 259 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */ 260}; 261 262#define ALI_CAS_SEM_BUSY 0x80000000 263#define ALI_CPR_ADDR_SECONDARY 0x100 264#define ALI_CPR_ADDR_READ 0x80 265#define ALI_CSPSR_CODEC_READY 0x08 266#define ALI_CSPSR_READ_OK 0x02 267#define ALI_CSPSR_WRITE_OK 0x01 268 269/* interrupts for the whole chip by interrupt status register finish */ 270 271#define ALI_INT_MICIN2 (1<<26) 272#define ALI_INT_PCMIN2 (1<<25) 273#define ALI_INT_I2SIN (1<<24) 274#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */ 275#define ALI_INT_SPDIFIN (1<<22) 276#define ALI_INT_LFEOUT (1<<21) 277#define ALI_INT_CENTEROUT (1<<20) 278#define ALI_INT_CODECSPDIFOUT (1<<19) 279#define ALI_INT_MICIN (1<<18) 280#define ALI_INT_PCMOUT (1<<17) 281#define ALI_INT_PCMIN (1<<16) 282#define ALI_INT_CPRAIS (1<<7) /* command port available */ 283#define ALI_INT_SPRAIS (1<<5) /* status port available */ 284#define ALI_INT_GPIO (1<<1) 285#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\ 286 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN) 287 288#define ICH_ALI_SC_RESET (1<<31) /* master reset */ 289#define ICH_ALI_SC_AC97_DBL (1<<30) 290#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */ 291#define ICH_ALI_SC_IN_BITS (3<<18) 292#define ICH_ALI_SC_OUT_BITS (3<<16) 293#define ICH_ALI_SC_6CH_CFG (3<<14) 294#define ICH_ALI_SC_PCM_4 (1<<8) 295#define ICH_ALI_SC_PCM_6 (2<<8) 296#define ICH_ALI_SC_PCM_246_MASK (3<<8) 297 298#define ICH_ALI_SS_SEC_ID (3<<5) 299#define ICH_ALI_SS_PRI_ID (3<<3) 300 301#define ICH_ALI_IF_AC97SP (1<<21) 302#define ICH_ALI_IF_MC (1<<20) 303#define ICH_ALI_IF_PI (1<<19) 304#define ICH_ALI_IF_MC2 (1<<18) 305#define ICH_ALI_IF_PI2 (1<<17) 306#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */ 307#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */ 308#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */ 309#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */ 310#define ICH_ALI_IF_PO_SPDF (1<<3) 311#define ICH_ALI_IF_PO (1<<1) 312 313/* 314 * 315 */ 316 317enum { 318 ICHD_PCMIN, 319 ICHD_PCMOUT, 320 ICHD_MIC, 321 ICHD_MIC2, 322 ICHD_PCM2IN, 323 ICHD_SPBAR, 324 ICHD_LAST = ICHD_SPBAR 325}; 326enum { 327 NVD_PCMIN, 328 NVD_PCMOUT, 329 NVD_MIC, 330 NVD_SPBAR, 331 NVD_LAST = NVD_SPBAR 332}; 333enum { 334 ALID_PCMIN, 335 ALID_PCMOUT, 336 ALID_MIC, 337 ALID_AC97SPDIFOUT, 338 ALID_SPDIFIN, 339 ALID_SPDIFOUT, 340 ALID_LAST = ALID_SPDIFOUT 341}; 342 343#define get_ichdev(substream) (substream->runtime->private_data) 344 345struct ichdev { 346 unsigned int ichd; /* ich device number */ 347 unsigned long reg_offset; /* offset to bmaddr */ 348 u32 *bdbar; /* CPU address (32bit) */ 349 unsigned int bdbar_addr; /* PCI bus address (32bit) */ 350 struct snd_pcm_substream *substream; 351 unsigned int physbuf; /* physical address (32bit) */ 352 unsigned int size; 353 unsigned int fragsize; 354 unsigned int fragsize1; 355 unsigned int position; 356 unsigned int pos_shift; 357 unsigned int last_pos; 358 int frags; 359 int lvi; 360 int lvi_frag; 361 int civ; 362 int ack; 363 int ack_reload; 364 unsigned int ack_bit; 365 unsigned int roff_sr; 366 unsigned int roff_picb; 367 unsigned int int_sta_mask; /* interrupt status mask */ 368 unsigned int ali_slot; /* ALI DMA slot */ 369 struct ac97_pcm *pcm; 370 int pcm_open_flag; 371 unsigned int page_attr_changed: 1; 372 unsigned int suspended: 1; 373}; 374 375struct intel8x0 { 376 unsigned int device_type; 377 378 int irq; 379 380 void __iomem *addr; 381 void __iomem *bmaddr; 382 383 struct pci_dev *pci; 384 struct snd_card *card; 385 386 int pcm_devs; 387 struct snd_pcm *pcm[6]; 388 struct ichdev ichd[6]; 389 390 unsigned multi4: 1, 391 multi6: 1, 392 multi8 :1, 393 dra: 1, 394 smp20bit: 1; 395 unsigned in_ac97_init: 1, 396 in_sdin_init: 1; 397 unsigned in_measurement: 1; /* during ac97 clock measurement */ 398 unsigned fix_nocache: 1; 399 unsigned buggy_irq: 1; 400 unsigned xbox: 1; 401 unsigned buggy_semaphore: 1; 402 403 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */ 404 unsigned int sdm_saved; /* SDM reg value */ 405 406 struct snd_ac97_bus *ac97_bus; 407 struct snd_ac97 *ac97[3]; 408 unsigned int ac97_sdin[3]; 409 unsigned int max_codecs, ncodecs; 410 unsigned int *codec_bit; 411 unsigned int codec_isr_bits; 412 unsigned int codec_ready_bits; 413 414 spinlock_t reg_lock; 415 416 u32 bdbars_count; 417 struct snd_dma_buffer bdbars; 418 u32 int_sta_reg; /* interrupt status register */ 419 u32 int_sta_mask; /* interrupt status mask */ 420}; 421 422static DEFINE_PCI_DEVICE_TABLE(snd_intel8x0_ids) = { 423 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */ 424 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */ 425 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */ 426 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */ 427 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */ 428 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */ 429 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */ 430 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */ 431 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */ 432 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */ 433 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */ 434 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */ 435 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */ 436 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */ 437 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */ 438 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */ 439 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */ 440 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */ 441 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */ 442 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */ 443 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */ 444 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */ 445 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */ 446 { 0, } 447}; 448 449MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids); 450 451/* 452 * Lowlevel I/O - busmaster 453 */ 454 455static inline u8 igetbyte(struct intel8x0 *chip, u32 offset) 456{ 457 return ioread8(chip->bmaddr + offset); 458} 459 460static inline u16 igetword(struct intel8x0 *chip, u32 offset) 461{ 462 return ioread16(chip->bmaddr + offset); 463} 464 465static inline u32 igetdword(struct intel8x0 *chip, u32 offset) 466{ 467 return ioread32(chip->bmaddr + offset); 468} 469 470static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val) 471{ 472 iowrite8(val, chip->bmaddr + offset); 473} 474 475static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val) 476{ 477 iowrite16(val, chip->bmaddr + offset); 478} 479 480static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val) 481{ 482 iowrite32(val, chip->bmaddr + offset); 483} 484 485/* 486 * Lowlevel I/O - AC'97 registers 487 */ 488 489static inline u16 iagetword(struct intel8x0 *chip, u32 offset) 490{ 491 return ioread16(chip->addr + offset); 492} 493 494static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val) 495{ 496 iowrite16(val, chip->addr + offset); 497} 498 499/* 500 * Basic I/O 501 */ 502 503/* 504 * access to AC97 codec via normal i/o (for ICH and SIS7012) 505 */ 506 507static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec) 508{ 509 int time; 510 511 if (codec > 2) 512 return -EIO; 513 if (chip->in_sdin_init) { 514 /* we don't know the ready bit assignment at the moment */ 515 /* so we check any */ 516 codec = chip->codec_isr_bits; 517 } else { 518 codec = chip->codec_bit[chip->ac97_sdin[codec]]; 519 } 520 521 /* codec ready ? */ 522 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) 523 return -EIO; 524 525 if (chip->buggy_semaphore) 526 return 0; /* just ignore ... */ 527 528 /* Anyone holding a semaphore for 1 msec should be shot... */ 529 time = 100; 530 do { 531 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) 532 return 0; 533 udelay(10); 534 } while (time--); 535 536 /* access to some forbidden (non existant) ac97 registers will not 537 * reset the semaphore. So even if you don't get the semaphore, still 538 * continue the access. We don't need the semaphore anyway. */ 539 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", 540 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); 541 iagetword(chip, 0); /* clear semaphore flag */ 542 /* I don't care about the semaphore */ 543 return -EBUSY; 544} 545 546static void snd_intel8x0_codec_write(struct snd_ac97 *ac97, 547 unsigned short reg, 548 unsigned short val) 549{ 550 struct intel8x0 *chip = ac97->private_data; 551 552 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 553 if (! chip->in_ac97_init) 554 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 555 } 556 iaputword(chip, reg + ac97->num * 0x80, val); 557} 558 559static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97, 560 unsigned short reg) 561{ 562 struct intel8x0 *chip = ac97->private_data; 563 unsigned short res; 564 unsigned int tmp; 565 566 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 567 if (! chip->in_ac97_init) 568 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 569 res = 0xffff; 570 } else { 571 res = iagetword(chip, reg + ac97->num * 0x80); 572 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 573 /* reset RCS and preserve other R/WC bits */ 574 iputdword(chip, ICHREG(GLOB_STA), tmp & 575 ~(chip->codec_ready_bits | ICH_GSCI)); 576 if (! chip->in_ac97_init) 577 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg); 578 res = 0xffff; 579 } 580 } 581 return res; 582} 583 584static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip, 585 unsigned int codec) 586{ 587 unsigned int tmp; 588 589 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) { 590 iagetword(chip, codec * 0x80); 591 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 592 /* reset RCS and preserve other R/WC bits */ 593 iputdword(chip, ICHREG(GLOB_STA), tmp & 594 ~(chip->codec_ready_bits | ICH_GSCI)); 595 } 596 } 597} 598 599/* 600 * access to AC97 for Ali5455 601 */ 602static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask) 603{ 604 int count = 0; 605 for (count = 0; count < 0x7f; count++) { 606 int val = igetbyte(chip, ICHREG(ALI_CSPSR)); 607 if (val & mask) 608 return 0; 609 } 610 if (! chip->in_ac97_init) 611 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n"); 612 return -EBUSY; 613} 614 615static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip) 616{ 617 int time = 100; 618 if (chip->buggy_semaphore) 619 return 0; /* just ignore ... */ 620 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY)) 621 udelay(1); 622 if (! time && ! chip->in_ac97_init) 623 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n"); 624 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY); 625} 626 627static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg) 628{ 629 struct intel8x0 *chip = ac97->private_data; 630 unsigned short data = 0xffff; 631 632 if (snd_intel8x0_ali_codec_semaphore(chip)) 633 goto __err; 634 reg |= ALI_CPR_ADDR_READ; 635 if (ac97->num) 636 reg |= ALI_CPR_ADDR_SECONDARY; 637 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 638 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK)) 639 goto __err; 640 data = igetword(chip, ICHREG(ALI_SPR)); 641 __err: 642 return data; 643} 644 645static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg, 646 unsigned short val) 647{ 648 struct intel8x0 *chip = ac97->private_data; 649 650 if (snd_intel8x0_ali_codec_semaphore(chip)) 651 return; 652 iputword(chip, ICHREG(ALI_CPR), val); 653 if (ac97->num) 654 reg |= ALI_CPR_ADDR_SECONDARY; 655 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 656 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK); 657} 658 659 660/* 661 * DMA I/O 662 */ 663static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) 664{ 665 int idx; 666 u32 *bdbar = ichdev->bdbar; 667 unsigned long port = ichdev->reg_offset; 668 669 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 670 if (ichdev->size == ichdev->fragsize) { 671 ichdev->ack_reload = ichdev->ack = 2; 672 ichdev->fragsize1 = ichdev->fragsize >> 1; 673 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { 674 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); 675 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 676 ichdev->fragsize1 >> ichdev->pos_shift); 677 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); 678 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 679 ichdev->fragsize1 >> ichdev->pos_shift); 680 } 681 ichdev->frags = 2; 682 } else { 683 ichdev->ack_reload = ichdev->ack = 1; 684 ichdev->fragsize1 = ichdev->fragsize; 685 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { 686 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + 687 (((idx >> 1) * ichdev->fragsize) % 688 ichdev->size)); 689 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 690 ichdev->fragsize >> ichdev->pos_shift); 691 } 692 ichdev->frags = ichdev->size / ichdev->fragsize; 693 } 694 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); 695 ichdev->civ = 0; 696 iputbyte(chip, port + ICH_REG_OFF_CIV, 0); 697 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; 698 ichdev->position = 0; 699 /* clear interrupts */ 700 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 701} 702 703#ifdef __i386__ 704static void fill_nocache(void *buf, int size, int nocache) 705{ 706 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; 707 if (nocache) 708 set_pages_uc(virt_to_page(buf), size); 709 else 710 set_pages_wb(virt_to_page(buf), size); 711} 712#else 713#define fill_nocache(buf, size, nocache) do { ; } while (0) 714#endif 715 716/* 717 * Interrupt handler 718 */ 719 720static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev) 721{ 722 unsigned long port = ichdev->reg_offset; 723 unsigned long flags; 724 int status, civ, i, step; 725 int ack = 0; 726 727 spin_lock_irqsave(&chip->reg_lock, flags); 728 status = igetbyte(chip, port + ichdev->roff_sr); 729 civ = igetbyte(chip, port + ICH_REG_OFF_CIV); 730 if (!(status & ICH_BCIS)) { 731 step = 0; 732 } else if (civ == ichdev->civ) { 733 // snd_printd("civ same %d\n", civ); 734 step = 1; 735 ichdev->civ++; 736 ichdev->civ &= ICH_REG_LVI_MASK; 737 } else { 738 step = civ - ichdev->civ; 739 if (step < 0) 740 step += ICH_REG_LVI_MASK + 1; 741 // if (step != 1) 742 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); 743 ichdev->civ = civ; 744 } 745 746 ichdev->position += step * ichdev->fragsize1; 747 if (! chip->in_measurement) 748 ichdev->position %= ichdev->size; 749 ichdev->lvi += step; 750 ichdev->lvi &= ICH_REG_LVI_MASK; 751 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 752 for (i = 0; i < step; i++) { 753 ichdev->lvi_frag++; 754 ichdev->lvi_frag %= ichdev->frags; 755 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1); 756 if (--ichdev->ack == 0) { 757 ichdev->ack = ichdev->ack_reload; 758 ack = 1; 759 } 760 } 761 spin_unlock_irqrestore(&chip->reg_lock, flags); 762 if (ack && ichdev->substream) { 763 snd_pcm_period_elapsed(ichdev->substream); 764 } 765 iputbyte(chip, port + ichdev->roff_sr, 766 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI)); 767} 768 769static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id) 770{ 771 struct intel8x0 *chip = dev_id; 772 struct ichdev *ichdev; 773 unsigned int status; 774 unsigned int i; 775 776 status = igetdword(chip, chip->int_sta_reg); 777 if (status == 0xffffffff) /* we are not yet resumed */ 778 return IRQ_NONE; 779 780 if ((status & chip->int_sta_mask) == 0) { 781 if (status) { 782 /* ack */ 783 iputdword(chip, chip->int_sta_reg, status); 784 if (! chip->buggy_irq) 785 status = 0; 786 } 787 return IRQ_RETVAL(status); 788 } 789 790 for (i = 0; i < chip->bdbars_count; i++) { 791 ichdev = &chip->ichd[i]; 792 if (status & ichdev->int_sta_mask) 793 snd_intel8x0_update(chip, ichdev); 794 } 795 796 /* ack them */ 797 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); 798 799 return IRQ_HANDLED; 800} 801 802/* 803 * PCM part 804 */ 805 806static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 807{ 808 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 809 struct ichdev *ichdev = get_ichdev(substream); 810 unsigned char val = 0; 811 unsigned long port = ichdev->reg_offset; 812 813 switch (cmd) { 814 case SNDRV_PCM_TRIGGER_RESUME: 815 ichdev->suspended = 0; 816 /* fallthru */ 817 case SNDRV_PCM_TRIGGER_START: 818 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 819 val = ICH_IOCE | ICH_STARTBM; 820 ichdev->last_pos = ichdev->position; 821 break; 822 case SNDRV_PCM_TRIGGER_SUSPEND: 823 ichdev->suspended = 1; 824 /* fallthru */ 825 case SNDRV_PCM_TRIGGER_STOP: 826 val = 0; 827 break; 828 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 829 val = ICH_IOCE; 830 break; 831 default: 832 return -EINVAL; 833 } 834 iputbyte(chip, port + ICH_REG_OFF_CR, val); 835 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 836 /* wait until DMA stopped */ 837 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; 838 /* reset whole DMA things */ 839 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 840 } 841 return 0; 842} 843 844static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd) 845{ 846 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 847 struct ichdev *ichdev = get_ichdev(substream); 848 unsigned long port = ichdev->reg_offset; 849 static int fiforeg[] = { 850 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) 851 }; 852 unsigned int val, fifo; 853 854 val = igetdword(chip, ICHREG(ALI_DMACR)); 855 switch (cmd) { 856 case SNDRV_PCM_TRIGGER_RESUME: 857 ichdev->suspended = 0; 858 /* fallthru */ 859 case SNDRV_PCM_TRIGGER_START: 860 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 861 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 862 /* clear FIFO for synchronization of channels */ 863 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]); 864 fifo &= ~(0xff << (ichdev->ali_slot % 4)); 865 fifo |= 0x83 << (ichdev->ali_slot % 4); 866 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo); 867 } 868 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 869 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */ 870 /* start DMA */ 871 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); 872 break; 873 case SNDRV_PCM_TRIGGER_SUSPEND: 874 ichdev->suspended = 1; 875 /* fallthru */ 876 case SNDRV_PCM_TRIGGER_STOP: 877 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 878 /* pause */ 879 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); 880 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 881 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 882 ; 883 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 884 break; 885 /* reset whole DMA things */ 886 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 887 /* clear interrupts */ 888 iputbyte(chip, port + ICH_REG_OFF_SR, 889 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e); 890 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 891 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask); 892 break; 893 default: 894 return -EINVAL; 895 } 896 return 0; 897} 898 899static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream, 900 struct snd_pcm_hw_params *hw_params) 901{ 902 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 903 struct ichdev *ichdev = get_ichdev(substream); 904 struct snd_pcm_runtime *runtime = substream->runtime; 905 int dbl = params_rate(hw_params) > 48000; 906 int err; 907 908 if (chip->fix_nocache && ichdev->page_attr_changed) { 909 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */ 910 ichdev->page_attr_changed = 0; 911 } 912 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 913 if (err < 0) 914 return err; 915 if (chip->fix_nocache) { 916 if (runtime->dma_area && ! ichdev->page_attr_changed) { 917 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); 918 ichdev->page_attr_changed = 1; 919 } 920 } 921 if (ichdev->pcm_open_flag) { 922 snd_ac97_pcm_close(ichdev->pcm); 923 ichdev->pcm_open_flag = 0; 924 } 925 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params), 926 params_channels(hw_params), 927 ichdev->pcm->r[dbl].slots); 928 if (err >= 0) { 929 ichdev->pcm_open_flag = 1; 930 /* Force SPDIF setting */ 931 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0) 932 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, 933 params_rate(hw_params)); 934 } 935 return err; 936} 937 938static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream) 939{ 940 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 941 struct ichdev *ichdev = get_ichdev(substream); 942 943 if (ichdev->pcm_open_flag) { 944 snd_ac97_pcm_close(ichdev->pcm); 945 ichdev->pcm_open_flag = 0; 946 } 947 if (chip->fix_nocache && ichdev->page_attr_changed) { 948 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0); 949 ichdev->page_attr_changed = 0; 950 } 951 return snd_pcm_lib_free_pages(substream); 952} 953 954static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip, 955 struct snd_pcm_runtime *runtime) 956{ 957 unsigned int cnt; 958 int dbl = runtime->rate > 48000; 959 960 spin_lock_irq(&chip->reg_lock); 961 switch (chip->device_type) { 962 case DEVICE_ALI: 963 cnt = igetdword(chip, ICHREG(ALI_SCR)); 964 cnt &= ~ICH_ALI_SC_PCM_246_MASK; 965 if (runtime->channels == 4 || dbl) 966 cnt |= ICH_ALI_SC_PCM_4; 967 else if (runtime->channels == 6) 968 cnt |= ICH_ALI_SC_PCM_6; 969 iputdword(chip, ICHREG(ALI_SCR), cnt); 970 break; 971 case DEVICE_SIS: 972 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 973 cnt &= ~ICH_SIS_PCM_246_MASK; 974 if (runtime->channels == 4 || dbl) 975 cnt |= ICH_SIS_PCM_4; 976 else if (runtime->channels == 6) 977 cnt |= ICH_SIS_PCM_6; 978 iputdword(chip, ICHREG(GLOB_CNT), cnt); 979 break; 980 default: 981 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 982 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT); 983 if (runtime->channels == 4 || dbl) 984 cnt |= ICH_PCM_4; 985 else if (runtime->channels == 6) 986 cnt |= ICH_PCM_6; 987 else if (runtime->channels == 8) 988 cnt |= ICH_PCM_8; 989 if (chip->device_type == DEVICE_NFORCE) { 990 /* reset to 2ch once to keep the 6 channel data in alignment, 991 * to start from Front Left always 992 */ 993 if (cnt & ICH_PCM_246_MASK) { 994 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK); 995 spin_unlock_irq(&chip->reg_lock); 996 msleep(50); /* grrr... */ 997 spin_lock_irq(&chip->reg_lock); 998 } 999 } else if (chip->device_type == DEVICE_INTEL_ICH4) { 1000 if (runtime->sample_bits > 16) 1001 cnt |= ICH_PCM_20BIT; 1002 } 1003 iputdword(chip, ICHREG(GLOB_CNT), cnt); 1004 break; 1005 } 1006 spin_unlock_irq(&chip->reg_lock); 1007} 1008 1009static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream) 1010{ 1011 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1012 struct snd_pcm_runtime *runtime = substream->runtime; 1013 struct ichdev *ichdev = get_ichdev(substream); 1014 1015 ichdev->physbuf = runtime->dma_addr; 1016 ichdev->size = snd_pcm_lib_buffer_bytes(substream); 1017 ichdev->fragsize = snd_pcm_lib_period_bytes(substream); 1018 if (ichdev->ichd == ICHD_PCMOUT) { 1019 snd_intel8x0_setup_pcm_out(chip, runtime); 1020 if (chip->device_type == DEVICE_INTEL_ICH4) 1021 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1; 1022 } 1023 snd_intel8x0_setup_periods(chip, ichdev); 1024 return 0; 1025} 1026 1027static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream) 1028{ 1029 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1030 struct ichdev *ichdev = get_ichdev(substream); 1031 size_t ptr1, ptr; 1032 int civ, timeout = 10; 1033 unsigned int position; 1034 1035 spin_lock(&chip->reg_lock); 1036 do { 1037 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); 1038 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); 1039 position = ichdev->position; 1040 if (ptr1 == 0) { 1041 udelay(10); 1042 continue; 1043 } 1044 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) && 1045 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) 1046 break; 1047 } while (timeout--); 1048 ptr = ichdev->last_pos; 1049 if (ptr1 != 0) { 1050 ptr1 <<= ichdev->pos_shift; 1051 ptr = ichdev->fragsize1 - ptr1; 1052 ptr += position; 1053 if (ptr < ichdev->last_pos) { 1054 unsigned int pos_base, last_base; 1055 pos_base = position / ichdev->fragsize1; 1056 last_base = ichdev->last_pos / ichdev->fragsize1; 1057 /* another sanity check; ptr1 can go back to full 1058 * before the base position is updated 1059 */ 1060 if (pos_base == last_base) 1061 ptr = ichdev->last_pos; 1062 } 1063 } 1064 ichdev->last_pos = ptr; 1065 spin_unlock(&chip->reg_lock); 1066 if (ptr >= ichdev->size) 1067 return 0; 1068 return bytes_to_frames(substream->runtime, ptr); 1069} 1070 1071static struct snd_pcm_hardware snd_intel8x0_stream = 1072{ 1073 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1074 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1075 SNDRV_PCM_INFO_MMAP_VALID | 1076 SNDRV_PCM_INFO_PAUSE | 1077 SNDRV_PCM_INFO_RESUME), 1078 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1079 .rates = SNDRV_PCM_RATE_48000, 1080 .rate_min = 48000, 1081 .rate_max = 48000, 1082 .channels_min = 2, 1083 .channels_max = 2, 1084 .buffer_bytes_max = 128 * 1024, 1085 .period_bytes_min = 32, 1086 .period_bytes_max = 128 * 1024, 1087 .periods_min = 1, 1088 .periods_max = 1024, 1089 .fifo_size = 0, 1090}; 1091 1092static unsigned int channels4[] = { 1093 2, 4, 1094}; 1095 1096static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = { 1097 .count = ARRAY_SIZE(channels4), 1098 .list = channels4, 1099 .mask = 0, 1100}; 1101 1102static unsigned int channels6[] = { 1103 2, 4, 6, 1104}; 1105 1106static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = { 1107 .count = ARRAY_SIZE(channels6), 1108 .list = channels6, 1109 .mask = 0, 1110}; 1111 1112static unsigned int channels8[] = { 1113 2, 4, 6, 8, 1114}; 1115 1116static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = { 1117 .count = ARRAY_SIZE(channels8), 1118 .list = channels8, 1119 .mask = 0, 1120}; 1121 1122static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev) 1123{ 1124 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1125 struct snd_pcm_runtime *runtime = substream->runtime; 1126 int err; 1127 1128 ichdev->substream = substream; 1129 runtime->hw = snd_intel8x0_stream; 1130 runtime->hw.rates = ichdev->pcm->rates; 1131 snd_pcm_limit_hw_rates(runtime); 1132 if (chip->device_type == DEVICE_SIS) { 1133 runtime->hw.buffer_bytes_max = 64*1024; 1134 runtime->hw.period_bytes_max = 64*1024; 1135 } 1136 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) 1137 return err; 1138 runtime->private_data = ichdev; 1139 return 0; 1140} 1141 1142static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream) 1143{ 1144 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1145 struct snd_pcm_runtime *runtime = substream->runtime; 1146 int err; 1147 1148 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]); 1149 if (err < 0) 1150 return err; 1151 1152 if (chip->multi8) { 1153 runtime->hw.channels_max = 8; 1154 snd_pcm_hw_constraint_list(runtime, 0, 1155 SNDRV_PCM_HW_PARAM_CHANNELS, 1156 &hw_constraints_channels8); 1157 } else if (chip->multi6) { 1158 runtime->hw.channels_max = 6; 1159 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1160 &hw_constraints_channels6); 1161 } else if (chip->multi4) { 1162 runtime->hw.channels_max = 4; 1163 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1164 &hw_constraints_channels4); 1165 } 1166 if (chip->dra) { 1167 snd_ac97_pcm_double_rate_rules(runtime); 1168 } 1169 if (chip->smp20bit) { 1170 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1171 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 1172 } 1173 return 0; 1174} 1175 1176static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream) 1177{ 1178 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1179 1180 chip->ichd[ICHD_PCMOUT].substream = NULL; 1181 return 0; 1182} 1183 1184static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream) 1185{ 1186 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1187 1188 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]); 1189} 1190 1191static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream) 1192{ 1193 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1194 1195 chip->ichd[ICHD_PCMIN].substream = NULL; 1196 return 0; 1197} 1198 1199static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream) 1200{ 1201 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1202 1203 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]); 1204} 1205 1206static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream) 1207{ 1208 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1209 1210 chip->ichd[ICHD_MIC].substream = NULL; 1211 return 0; 1212} 1213 1214static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream) 1215{ 1216 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1217 1218 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]); 1219} 1220 1221static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream) 1222{ 1223 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1224 1225 chip->ichd[ICHD_MIC2].substream = NULL; 1226 return 0; 1227} 1228 1229static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream) 1230{ 1231 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1232 1233 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]); 1234} 1235 1236static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream) 1237{ 1238 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1239 1240 chip->ichd[ICHD_PCM2IN].substream = NULL; 1241 return 0; 1242} 1243 1244static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream) 1245{ 1246 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1247 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1248 1249 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]); 1250} 1251 1252static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream) 1253{ 1254 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1255 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1256 1257 chip->ichd[idx].substream = NULL; 1258 return 0; 1259} 1260 1261static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream) 1262{ 1263 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1264 unsigned int val; 1265 1266 spin_lock_irq(&chip->reg_lock); 1267 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1268 val |= ICH_ALI_IF_AC97SP; 1269 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1270 /* also needs to set ALI_SC_CODEC_SPDF correctly */ 1271 spin_unlock_irq(&chip->reg_lock); 1272 1273 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]); 1274} 1275 1276static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream) 1277{ 1278 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1279 unsigned int val; 1280 1281 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL; 1282 spin_lock_irq(&chip->reg_lock); 1283 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1284 val &= ~ICH_ALI_IF_AC97SP; 1285 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1286 spin_unlock_irq(&chip->reg_lock); 1287 1288 return 0; 1289} 1290 1291 1292static struct snd_pcm_ops snd_intel8x0_playback_ops = { 1293 .open = snd_intel8x0_playback_open, 1294 .close = snd_intel8x0_playback_close, 1295 .ioctl = snd_pcm_lib_ioctl, 1296 .hw_params = snd_intel8x0_hw_params, 1297 .hw_free = snd_intel8x0_hw_free, 1298 .prepare = snd_intel8x0_pcm_prepare, 1299 .trigger = snd_intel8x0_pcm_trigger, 1300 .pointer = snd_intel8x0_pcm_pointer, 1301}; 1302 1303static struct snd_pcm_ops snd_intel8x0_capture_ops = { 1304 .open = snd_intel8x0_capture_open, 1305 .close = snd_intel8x0_capture_close, 1306 .ioctl = snd_pcm_lib_ioctl, 1307 .hw_params = snd_intel8x0_hw_params, 1308 .hw_free = snd_intel8x0_hw_free, 1309 .prepare = snd_intel8x0_pcm_prepare, 1310 .trigger = snd_intel8x0_pcm_trigger, 1311 .pointer = snd_intel8x0_pcm_pointer, 1312}; 1313 1314static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = { 1315 .open = snd_intel8x0_mic_open, 1316 .close = snd_intel8x0_mic_close, 1317 .ioctl = snd_pcm_lib_ioctl, 1318 .hw_params = snd_intel8x0_hw_params, 1319 .hw_free = snd_intel8x0_hw_free, 1320 .prepare = snd_intel8x0_pcm_prepare, 1321 .trigger = snd_intel8x0_pcm_trigger, 1322 .pointer = snd_intel8x0_pcm_pointer, 1323}; 1324 1325static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = { 1326 .open = snd_intel8x0_mic2_open, 1327 .close = snd_intel8x0_mic2_close, 1328 .ioctl = snd_pcm_lib_ioctl, 1329 .hw_params = snd_intel8x0_hw_params, 1330 .hw_free = snd_intel8x0_hw_free, 1331 .prepare = snd_intel8x0_pcm_prepare, 1332 .trigger = snd_intel8x0_pcm_trigger, 1333 .pointer = snd_intel8x0_pcm_pointer, 1334}; 1335 1336static struct snd_pcm_ops snd_intel8x0_capture2_ops = { 1337 .open = snd_intel8x0_capture2_open, 1338 .close = snd_intel8x0_capture2_close, 1339 .ioctl = snd_pcm_lib_ioctl, 1340 .hw_params = snd_intel8x0_hw_params, 1341 .hw_free = snd_intel8x0_hw_free, 1342 .prepare = snd_intel8x0_pcm_prepare, 1343 .trigger = snd_intel8x0_pcm_trigger, 1344 .pointer = snd_intel8x0_pcm_pointer, 1345}; 1346 1347static struct snd_pcm_ops snd_intel8x0_spdif_ops = { 1348 .open = snd_intel8x0_spdif_open, 1349 .close = snd_intel8x0_spdif_close, 1350 .ioctl = snd_pcm_lib_ioctl, 1351 .hw_params = snd_intel8x0_hw_params, 1352 .hw_free = snd_intel8x0_hw_free, 1353 .prepare = snd_intel8x0_pcm_prepare, 1354 .trigger = snd_intel8x0_pcm_trigger, 1355 .pointer = snd_intel8x0_pcm_pointer, 1356}; 1357 1358static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = { 1359 .open = snd_intel8x0_playback_open, 1360 .close = snd_intel8x0_playback_close, 1361 .ioctl = snd_pcm_lib_ioctl, 1362 .hw_params = snd_intel8x0_hw_params, 1363 .hw_free = snd_intel8x0_hw_free, 1364 .prepare = snd_intel8x0_pcm_prepare, 1365 .trigger = snd_intel8x0_ali_trigger, 1366 .pointer = snd_intel8x0_pcm_pointer, 1367}; 1368 1369static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = { 1370 .open = snd_intel8x0_capture_open, 1371 .close = snd_intel8x0_capture_close, 1372 .ioctl = snd_pcm_lib_ioctl, 1373 .hw_params = snd_intel8x0_hw_params, 1374 .hw_free = snd_intel8x0_hw_free, 1375 .prepare = snd_intel8x0_pcm_prepare, 1376 .trigger = snd_intel8x0_ali_trigger, 1377 .pointer = snd_intel8x0_pcm_pointer, 1378}; 1379 1380static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = { 1381 .open = snd_intel8x0_mic_open, 1382 .close = snd_intel8x0_mic_close, 1383 .ioctl = snd_pcm_lib_ioctl, 1384 .hw_params = snd_intel8x0_hw_params, 1385 .hw_free = snd_intel8x0_hw_free, 1386 .prepare = snd_intel8x0_pcm_prepare, 1387 .trigger = snd_intel8x0_ali_trigger, 1388 .pointer = snd_intel8x0_pcm_pointer, 1389}; 1390 1391static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = { 1392 .open = snd_intel8x0_ali_ac97spdifout_open, 1393 .close = snd_intel8x0_ali_ac97spdifout_close, 1394 .ioctl = snd_pcm_lib_ioctl, 1395 .hw_params = snd_intel8x0_hw_params, 1396 .hw_free = snd_intel8x0_hw_free, 1397 .prepare = snd_intel8x0_pcm_prepare, 1398 .trigger = snd_intel8x0_ali_trigger, 1399 .pointer = snd_intel8x0_pcm_pointer, 1400}; 1401 1402 1403struct ich_pcm_table { 1404 char *suffix; 1405 struct snd_pcm_ops *playback_ops; 1406 struct snd_pcm_ops *capture_ops; 1407 size_t prealloc_size; 1408 size_t prealloc_max_size; 1409 int ac97_idx; 1410}; 1411 1412static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device, 1413 struct ich_pcm_table *rec) 1414{ 1415 struct snd_pcm *pcm; 1416 int err; 1417 char name[32]; 1418 1419 if (rec->suffix) 1420 sprintf(name, "Intel ICH - %s", rec->suffix); 1421 else 1422 strcpy(name, "Intel ICH"); 1423 err = snd_pcm_new(chip->card, name, device, 1424 rec->playback_ops ? 1 : 0, 1425 rec->capture_ops ? 1 : 0, &pcm); 1426 if (err < 0) 1427 return err; 1428 1429 if (rec->playback_ops) 1430 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); 1431 if (rec->capture_ops) 1432 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); 1433 1434 pcm->private_data = chip; 1435 pcm->info_flags = 0; 1436 if (rec->suffix) 1437 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); 1438 else 1439 strcpy(pcm->name, chip->card->shortname); 1440 chip->pcm[device] = pcm; 1441 1442 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1443 snd_dma_pci_data(chip->pci), 1444 rec->prealloc_size, rec->prealloc_max_size); 1445 1446 return 0; 1447} 1448 1449static struct ich_pcm_table intel_pcms[] __devinitdata = { 1450 { 1451 .playback_ops = &snd_intel8x0_playback_ops, 1452 .capture_ops = &snd_intel8x0_capture_ops, 1453 .prealloc_size = 64 * 1024, 1454 .prealloc_max_size = 128 * 1024, 1455 }, 1456 { 1457 .suffix = "MIC ADC", 1458 .capture_ops = &snd_intel8x0_capture_mic_ops, 1459 .prealloc_size = 0, 1460 .prealloc_max_size = 128 * 1024, 1461 .ac97_idx = ICHD_MIC, 1462 }, 1463 { 1464 .suffix = "MIC2 ADC", 1465 .capture_ops = &snd_intel8x0_capture_mic2_ops, 1466 .prealloc_size = 0, 1467 .prealloc_max_size = 128 * 1024, 1468 .ac97_idx = ICHD_MIC2, 1469 }, 1470 { 1471 .suffix = "ADC2", 1472 .capture_ops = &snd_intel8x0_capture2_ops, 1473 .prealloc_size = 0, 1474 .prealloc_max_size = 128 * 1024, 1475 .ac97_idx = ICHD_PCM2IN, 1476 }, 1477 { 1478 .suffix = "IEC958", 1479 .playback_ops = &snd_intel8x0_spdif_ops, 1480 .prealloc_size = 64 * 1024, 1481 .prealloc_max_size = 128 * 1024, 1482 .ac97_idx = ICHD_SPBAR, 1483 }, 1484}; 1485 1486static struct ich_pcm_table nforce_pcms[] __devinitdata = { 1487 { 1488 .playback_ops = &snd_intel8x0_playback_ops, 1489 .capture_ops = &snd_intel8x0_capture_ops, 1490 .prealloc_size = 64 * 1024, 1491 .prealloc_max_size = 128 * 1024, 1492 }, 1493 { 1494 .suffix = "MIC ADC", 1495 .capture_ops = &snd_intel8x0_capture_mic_ops, 1496 .prealloc_size = 0, 1497 .prealloc_max_size = 128 * 1024, 1498 .ac97_idx = NVD_MIC, 1499 }, 1500 { 1501 .suffix = "IEC958", 1502 .playback_ops = &snd_intel8x0_spdif_ops, 1503 .prealloc_size = 64 * 1024, 1504 .prealloc_max_size = 128 * 1024, 1505 .ac97_idx = NVD_SPBAR, 1506 }, 1507}; 1508 1509static struct ich_pcm_table ali_pcms[] __devinitdata = { 1510 { 1511 .playback_ops = &snd_intel8x0_ali_playback_ops, 1512 .capture_ops = &snd_intel8x0_ali_capture_ops, 1513 .prealloc_size = 64 * 1024, 1514 .prealloc_max_size = 128 * 1024, 1515 }, 1516 { 1517 .suffix = "MIC ADC", 1518 .capture_ops = &snd_intel8x0_ali_capture_mic_ops, 1519 .prealloc_size = 0, 1520 .prealloc_max_size = 128 * 1024, 1521 .ac97_idx = ALID_MIC, 1522 }, 1523 { 1524 .suffix = "IEC958", 1525 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops, 1526 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */ 1527 .prealloc_size = 64 * 1024, 1528 .prealloc_max_size = 128 * 1024, 1529 .ac97_idx = ALID_AC97SPDIFOUT, 1530 }, 1531}; 1532 1533static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip) 1534{ 1535 int i, tblsize, device, err; 1536 struct ich_pcm_table *tbl, *rec; 1537 1538 switch (chip->device_type) { 1539 case DEVICE_INTEL_ICH4: 1540 tbl = intel_pcms; 1541 tblsize = ARRAY_SIZE(intel_pcms); 1542 if (spdif_aclink) 1543 tblsize--; 1544 break; 1545 case DEVICE_NFORCE: 1546 tbl = nforce_pcms; 1547 tblsize = ARRAY_SIZE(nforce_pcms); 1548 if (spdif_aclink) 1549 tblsize--; 1550 break; 1551 case DEVICE_ALI: 1552 tbl = ali_pcms; 1553 tblsize = ARRAY_SIZE(ali_pcms); 1554 break; 1555 default: 1556 tbl = intel_pcms; 1557 tblsize = 2; 1558 break; 1559 } 1560 1561 device = 0; 1562 for (i = 0; i < tblsize; i++) { 1563 rec = tbl + i; 1564 if (i > 0 && rec->ac97_idx) { 1565 /* activate PCM only when associated AC'97 codec */ 1566 if (! chip->ichd[rec->ac97_idx].pcm) 1567 continue; 1568 } 1569 err = snd_intel8x0_pcm1(chip, device, rec); 1570 if (err < 0) 1571 return err; 1572 device++; 1573 } 1574 1575 chip->pcm_devs = device; 1576 return 0; 1577} 1578 1579 1580/* 1581 * Mixer part 1582 */ 1583 1584static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 1585{ 1586 struct intel8x0 *chip = bus->private_data; 1587 chip->ac97_bus = NULL; 1588} 1589 1590static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97) 1591{ 1592 struct intel8x0 *chip = ac97->private_data; 1593 chip->ac97[ac97->num] = NULL; 1594} 1595 1596static struct ac97_pcm ac97_pcm_defs[] __devinitdata = { 1597 /* front PCM */ 1598 { 1599 .exclusive = 1, 1600 .r = { { 1601 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1602 (1 << AC97_SLOT_PCM_RIGHT) | 1603 (1 << AC97_SLOT_PCM_CENTER) | 1604 (1 << AC97_SLOT_PCM_SLEFT) | 1605 (1 << AC97_SLOT_PCM_SRIGHT) | 1606 (1 << AC97_SLOT_LFE) 1607 }, 1608 { 1609 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1610 (1 << AC97_SLOT_PCM_RIGHT) | 1611 (1 << AC97_SLOT_PCM_LEFT_0) | 1612 (1 << AC97_SLOT_PCM_RIGHT_0) 1613 } 1614 } 1615 }, 1616 /* PCM IN #1 */ 1617 { 1618 .stream = 1, 1619 .exclusive = 1, 1620 .r = { { 1621 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1622 (1 << AC97_SLOT_PCM_RIGHT) 1623 } 1624 } 1625 }, 1626 /* MIC IN #1 */ 1627 { 1628 .stream = 1, 1629 .exclusive = 1, 1630 .r = { { 1631 .slots = (1 << AC97_SLOT_MIC) 1632 } 1633 } 1634 }, 1635 /* S/PDIF PCM */ 1636 { 1637 .exclusive = 1, 1638 .spdif = 1, 1639 .r = { { 1640 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | 1641 (1 << AC97_SLOT_SPDIF_RIGHT2) 1642 } 1643 } 1644 }, 1645 /* PCM IN #2 */ 1646 { 1647 .stream = 1, 1648 .exclusive = 1, 1649 .r = { { 1650 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1651 (1 << AC97_SLOT_PCM_RIGHT) 1652 } 1653 } 1654 }, 1655 /* MIC IN #2 */ 1656 { 1657 .stream = 1, 1658 .exclusive = 1, 1659 .r = { { 1660 .slots = (1 << AC97_SLOT_MIC) 1661 } 1662 } 1663 }, 1664}; 1665 1666static struct ac97_quirk ac97_quirks[] __devinitdata = { 1667 { 1668 .subvendor = 0x0e11, 1669 .subdevice = 0x000e, 1670 .name = "Compaq Deskpro EN", /* AD1885 */ 1671 .type = AC97_TUNE_HP_ONLY 1672 }, 1673 { 1674 .subvendor = 0x0e11, 1675 .subdevice = 0x008a, 1676 .name = "Compaq Evo W4000", /* AD1885 */ 1677 .type = AC97_TUNE_HP_ONLY 1678 }, 1679 { 1680 .subvendor = 0x0e11, 1681 .subdevice = 0x00b8, 1682 .name = "Compaq Evo D510C", 1683 .type = AC97_TUNE_HP_ONLY 1684 }, 1685 { 1686 .subvendor = 0x0e11, 1687 .subdevice = 0x0860, 1688 .name = "HP/Compaq nx7010", 1689 .type = AC97_TUNE_MUTE_LED 1690 }, 1691 { 1692 .subvendor = 0x1014, 1693 .subdevice = 0x0534, 1694 .name = "ThinkPad X31", 1695 .type = AC97_TUNE_INV_EAPD 1696 }, 1697 { 1698 .subvendor = 0x1014, 1699 .subdevice = 0x1f00, 1700 .name = "MS-9128", 1701 .type = AC97_TUNE_ALC_JACK 1702 }, 1703 { 1704 .subvendor = 0x1014, 1705 .subdevice = 0x0267, 1706 .name = "IBM NetVista A30p", /* AD1981B */ 1707 .type = AC97_TUNE_HP_ONLY 1708 }, 1709 { 1710 .subvendor = 0x1025, 1711 .subdevice = 0x0082, 1712 .name = "Acer Travelmate 2310", 1713 .type = AC97_TUNE_HP_ONLY 1714 }, 1715 { 1716 .subvendor = 0x1025, 1717 .subdevice = 0x0083, 1718 .name = "Acer Aspire 3003LCi", 1719 .type = AC97_TUNE_HP_ONLY 1720 }, 1721 { 1722 .subvendor = 0x1028, 1723 .subdevice = 0x00d8, 1724 .name = "Dell Precision 530", /* AD1885 */ 1725 .type = AC97_TUNE_HP_ONLY 1726 }, 1727 { 1728 .subvendor = 0x1028, 1729 .subdevice = 0x010d, 1730 .name = "Dell", /* which model? AD1885 */ 1731 .type = AC97_TUNE_HP_ONLY 1732 }, 1733 { 1734 .subvendor = 0x1028, 1735 .subdevice = 0x0126, 1736 .name = "Dell Optiplex GX260", /* AD1981A */ 1737 .type = AC97_TUNE_HP_ONLY 1738 }, 1739 { 1740 .subvendor = 0x1028, 1741 .subdevice = 0x012c, 1742 .name = "Dell Precision 650", /* AD1981A */ 1743 .type = AC97_TUNE_HP_ONLY 1744 }, 1745 { 1746 .subvendor = 0x1028, 1747 .subdevice = 0x012d, 1748 .name = "Dell Precision 450", /* AD1981B*/ 1749 .type = AC97_TUNE_HP_ONLY 1750 }, 1751 { 1752 .subvendor = 0x1028, 1753 .subdevice = 0x0147, 1754 .name = "Dell", /* which model? AD1981B*/ 1755 .type = AC97_TUNE_HP_ONLY 1756 }, 1757 { 1758 .subvendor = 0x1028, 1759 .subdevice = 0x0151, 1760 .name = "Dell Optiplex GX270", /* AD1981B */ 1761 .type = AC97_TUNE_HP_ONLY 1762 }, 1763 { 1764 .subvendor = 0x1028, 1765 .subdevice = 0x014e, 1766 .name = "Dell D800", /* STAC9750/51 */ 1767 .type = AC97_TUNE_HP_ONLY 1768 }, 1769 { 1770 .subvendor = 0x1028, 1771 .subdevice = 0x0163, 1772 .name = "Dell Unknown", /* STAC9750/51 */ 1773 .type = AC97_TUNE_HP_ONLY 1774 }, 1775 { 1776 .subvendor = 0x1028, 1777 .subdevice = 0x016a, 1778 .name = "Dell Inspiron 8600", /* STAC9750/51 */ 1779 .type = AC97_TUNE_HP_ONLY 1780 }, 1781 { 1782 .subvendor = 0x1028, 1783 .subdevice = 0x0182, 1784 .name = "Dell Latitude D610", /* STAC9750/51 */ 1785 .type = AC97_TUNE_HP_ONLY 1786 }, 1787 { 1788 .subvendor = 0x1028, 1789 .subdevice = 0x0186, 1790 .name = "Dell Latitude D810", /* cf. Malone #41015 */ 1791 .type = AC97_TUNE_HP_MUTE_LED 1792 }, 1793 { 1794 .subvendor = 0x1028, 1795 .subdevice = 0x0188, 1796 .name = "Dell Inspiron 6000", 1797 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */ 1798 }, 1799 { 1800 .subvendor = 0x1028, 1801 .subdevice = 0x0191, 1802 .name = "Dell Inspiron 8600", 1803 .type = AC97_TUNE_HP_ONLY 1804 }, 1805 { 1806 .subvendor = 0x103c, 1807 .subdevice = 0x006d, 1808 .name = "HP zv5000", 1809 .type = AC97_TUNE_MUTE_LED /*AD1981B*/ 1810 }, 1811 { 1812 .subvendor = 0x103c, 1813 .subdevice = 0x00c3, 1814 .name = "HP xw6000", 1815 .type = AC97_TUNE_HP_ONLY 1816 }, 1817 { 1818 .subvendor = 0x103c, 1819 .subdevice = 0x088c, 1820 .name = "HP nc8000", 1821 .type = AC97_TUNE_HP_MUTE_LED 1822 }, 1823 { 1824 .subvendor = 0x103c, 1825 .subdevice = 0x0890, 1826 .name = "HP nc6000", 1827 .type = AC97_TUNE_MUTE_LED 1828 }, 1829 { 1830 .subvendor = 0x103c, 1831 .subdevice = 0x129d, 1832 .name = "HP xw8000", 1833 .type = AC97_TUNE_HP_ONLY 1834 }, 1835 { 1836 .subvendor = 0x103c, 1837 .subdevice = 0x0938, 1838 .name = "HP nc4200", 1839 .type = AC97_TUNE_HP_MUTE_LED 1840 }, 1841 { 1842 .subvendor = 0x103c, 1843 .subdevice = 0x099c, 1844 .name = "HP nx6110/nc6120", 1845 .type = AC97_TUNE_HP_MUTE_LED 1846 }, 1847 { 1848 .subvendor = 0x103c, 1849 .subdevice = 0x0944, 1850 .name = "HP nc6220", 1851 .type = AC97_TUNE_HP_MUTE_LED 1852 }, 1853 { 1854 .subvendor = 0x103c, 1855 .subdevice = 0x0934, 1856 .name = "HP nc8220", 1857 .type = AC97_TUNE_HP_MUTE_LED 1858 }, 1859 { 1860 .subvendor = 0x103c, 1861 .subdevice = 0x12f1, 1862 .name = "HP xw8200", /* AD1981B*/ 1863 .type = AC97_TUNE_HP_ONLY 1864 }, 1865 { 1866 .subvendor = 0x103c, 1867 .subdevice = 0x12f2, 1868 .name = "HP xw6200", 1869 .type = AC97_TUNE_HP_ONLY 1870 }, 1871 { 1872 .subvendor = 0x103c, 1873 .subdevice = 0x3008, 1874 .name = "HP xw4200", /* AD1981B*/ 1875 .type = AC97_TUNE_HP_ONLY 1876 }, 1877 { 1878 .subvendor = 0x104d, 1879 .subdevice = 0x8144, 1880 .name = "Sony", 1881 .type = AC97_TUNE_INV_EAPD 1882 }, 1883 { 1884 .subvendor = 0x104d, 1885 .subdevice = 0x8197, 1886 .name = "Sony S1XP", 1887 .type = AC97_TUNE_INV_EAPD 1888 }, 1889 { 1890 .subvendor = 0x104d, 1891 .subdevice = 0x81c0, 1892 .name = "Sony VAIO VGN-T350P", /*AD1981B*/ 1893 .type = AC97_TUNE_INV_EAPD 1894 }, 1895 { 1896 .subvendor = 0x104d, 1897 .subdevice = 0x81c5, 1898 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/ 1899 .type = AC97_TUNE_INV_EAPD 1900 }, 1901 { 1902 .subvendor = 0x1043, 1903 .subdevice = 0x80f3, 1904 .name = "ASUS ICH5/AD1985", 1905 .type = AC97_TUNE_AD_SHARING 1906 }, 1907 { 1908 .subvendor = 0x10cf, 1909 .subdevice = 0x11c3, 1910 .name = "Fujitsu-Siemens E4010", 1911 .type = AC97_TUNE_HP_ONLY 1912 }, 1913 { 1914 .subvendor = 0x10cf, 1915 .subdevice = 0x1225, 1916 .name = "Fujitsu-Siemens T3010", 1917 .type = AC97_TUNE_HP_ONLY 1918 }, 1919 { 1920 .subvendor = 0x10cf, 1921 .subdevice = 0x1253, 1922 .name = "Fujitsu S6210", /* STAC9750/51 */ 1923 .type = AC97_TUNE_HP_ONLY 1924 }, 1925 { 1926 .subvendor = 0x10cf, 1927 .subdevice = 0x127d, 1928 .name = "Fujitsu Lifebook P7010", 1929 .type = AC97_TUNE_HP_ONLY 1930 }, 1931 { 1932 .subvendor = 0x10cf, 1933 .subdevice = 0x127e, 1934 .name = "Fujitsu Lifebook C1211D", 1935 .type = AC97_TUNE_HP_ONLY 1936 }, 1937 { 1938 .subvendor = 0x10cf, 1939 .subdevice = 0x12ec, 1940 .name = "Fujitsu-Siemens 4010", 1941 .type = AC97_TUNE_HP_ONLY 1942 }, 1943 { 1944 .subvendor = 0x10cf, 1945 .subdevice = 0x12f2, 1946 .name = "Fujitsu-Siemens Celsius H320", 1947 .type = AC97_TUNE_SWAP_HP 1948 }, 1949 { 1950 .subvendor = 0x10f1, 1951 .subdevice = 0x2665, 1952 .name = "Fujitsu-Siemens Celsius", /* AD1981? */ 1953 .type = AC97_TUNE_HP_ONLY 1954 }, 1955 { 1956 .subvendor = 0x10f1, 1957 .subdevice = 0x2885, 1958 .name = "AMD64 Mobo", /* ALC650 */ 1959 .type = AC97_TUNE_HP_ONLY 1960 }, 1961 { 1962 .subvendor = 0x10f1, 1963 .subdevice = 0x2895, 1964 .name = "Tyan Thunder K8WE", 1965 .type = AC97_TUNE_HP_ONLY 1966 }, 1967 { 1968 .subvendor = 0x10f7, 1969 .subdevice = 0x834c, 1970 .name = "Panasonic CF-R4", 1971 .type = AC97_TUNE_HP_ONLY, 1972 }, 1973 { 1974 .subvendor = 0x110a, 1975 .subdevice = 0x0056, 1976 .name = "Fujitsu-Siemens Scenic", /* AD1981? */ 1977 .type = AC97_TUNE_HP_ONLY 1978 }, 1979 { 1980 .subvendor = 0x11d4, 1981 .subdevice = 0x5375, 1982 .name = "ADI AD1985 (discrete)", 1983 .type = AC97_TUNE_HP_ONLY 1984 }, 1985 { 1986 .subvendor = 0x1462, 1987 .subdevice = 0x5470, 1988 .name = "MSI P4 ATX 645 Ultra", 1989 .type = AC97_TUNE_HP_ONLY 1990 }, 1991 { 1992 .subvendor = 0x161f, 1993 .subdevice = 0x203a, 1994 .name = "Gateway 4525GZ", /* AD1981B */ 1995 .type = AC97_TUNE_INV_EAPD 1996 }, 1997 { 1998 .subvendor = 0x1734, 1999 .subdevice = 0x0088, 2000 .name = "Fujitsu-Siemens D1522", /* AD1981 */ 2001 .type = AC97_TUNE_HP_ONLY 2002 }, 2003 { 2004 .subvendor = 0x8086, 2005 .subdevice = 0x2000, 2006 .mask = 0xfff0, 2007 .name = "Intel ICH5/AD1985", 2008 .type = AC97_TUNE_AD_SHARING 2009 }, 2010 { 2011 .subvendor = 0x8086, 2012 .subdevice = 0x4000, 2013 .mask = 0xfff0, 2014 .name = "Intel ICH5/AD1985", 2015 .type = AC97_TUNE_AD_SHARING 2016 }, 2017 { 2018 .subvendor = 0x8086, 2019 .subdevice = 0x4856, 2020 .name = "Intel D845WN (82801BA)", 2021 .type = AC97_TUNE_SWAP_HP 2022 }, 2023 { 2024 .subvendor = 0x8086, 2025 .subdevice = 0x4d44, 2026 .name = "Intel D850EMV2", /* AD1885 */ 2027 .type = AC97_TUNE_HP_ONLY 2028 }, 2029 { 2030 .subvendor = 0x8086, 2031 .subdevice = 0x4d56, 2032 .name = "Intel ICH/AD1885", 2033 .type = AC97_TUNE_HP_ONLY 2034 }, 2035 { 2036 .subvendor = 0x8086, 2037 .subdevice = 0x6000, 2038 .mask = 0xfff0, 2039 .name = "Intel ICH5/AD1985", 2040 .type = AC97_TUNE_AD_SHARING 2041 }, 2042 { 2043 .subvendor = 0x8086, 2044 .subdevice = 0xe000, 2045 .mask = 0xfff0, 2046 .name = "Intel ICH5/AD1985", 2047 .type = AC97_TUNE_AD_SHARING 2048 }, 2049 { } /* terminator */ 2050}; 2051 2052static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock, 2053 const char *quirk_override) 2054{ 2055 struct snd_ac97_bus *pbus; 2056 struct snd_ac97_template ac97; 2057 int err; 2058 unsigned int i, codecs; 2059 unsigned int glob_sta = 0; 2060 struct snd_ac97_bus_ops *ops; 2061 static struct snd_ac97_bus_ops standard_bus_ops = { 2062 .write = snd_intel8x0_codec_write, 2063 .read = snd_intel8x0_codec_read, 2064 }; 2065 static struct snd_ac97_bus_ops ali_bus_ops = { 2066 .write = snd_intel8x0_ali_codec_write, 2067 .read = snd_intel8x0_ali_codec_read, 2068 }; 2069 2070 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */ 2071 if (!spdif_aclink) { 2072 switch (chip->device_type) { 2073 case DEVICE_NFORCE: 2074 chip->spdif_idx = NVD_SPBAR; 2075 break; 2076 case DEVICE_ALI: 2077 chip->spdif_idx = ALID_AC97SPDIFOUT; 2078 break; 2079 case DEVICE_INTEL_ICH4: 2080 chip->spdif_idx = ICHD_SPBAR; 2081 break; 2082 }; 2083 } 2084 2085 chip->in_ac97_init = 1; 2086 2087 memset(&ac97, 0, sizeof(ac97)); 2088 ac97.private_data = chip; 2089 ac97.private_free = snd_intel8x0_mixer_free_ac97; 2090 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE; 2091 if (chip->xbox) 2092 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR; 2093 if (chip->device_type != DEVICE_ALI) { 2094 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 2095 ops = &standard_bus_ops; 2096 chip->in_sdin_init = 1; 2097 codecs = 0; 2098 for (i = 0; i < chip->max_codecs; i++) { 2099 if (! (glob_sta & chip->codec_bit[i])) 2100 continue; 2101 if (chip->device_type == DEVICE_INTEL_ICH4) { 2102 snd_intel8x0_codec_read_test(chip, codecs); 2103 chip->ac97_sdin[codecs] = 2104 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK; 2105 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3)) 2106 chip->ac97_sdin[codecs] = 0; 2107 } else 2108 chip->ac97_sdin[codecs] = i; 2109 codecs++; 2110 } 2111 chip->in_sdin_init = 0; 2112 if (! codecs) 2113 codecs = 1; 2114 } else { 2115 ops = &ali_bus_ops; 2116 codecs = 1; 2117 /* detect the secondary codec */ 2118 for (i = 0; i < 100; i++) { 2119 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR)); 2120 if (reg & 0x40) { 2121 codecs = 2; 2122 break; 2123 } 2124 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40); 2125 udelay(1); 2126 } 2127 } 2128 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0) 2129 goto __err; 2130 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus; 2131 if (ac97_clock >= 8000 && ac97_clock <= 48000) 2132 pbus->clock = ac97_clock; 2133 if (chip->device_type == DEVICE_ALI) 2134 pbus->no_vra = 1; 2135 else 2136 pbus->dra = 1; 2137 chip->ac97_bus = pbus; 2138 chip->ncodecs = codecs; 2139 2140 ac97.pci = chip->pci; 2141 for (i = 0; i < codecs; i++) { 2142 ac97.num = i; 2143 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) { 2144 if (err != -EACCES) 2145 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i); 2146 if (i == 0) 2147 goto __err; 2148 } 2149 } 2150 /* tune up the primary codec */ 2151 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); 2152 /* enable separate SDINs for ICH4 */ 2153 if (chip->device_type == DEVICE_INTEL_ICH4) 2154 pbus->isdin = 1; 2155 /* find the available PCM streams */ 2156 i = ARRAY_SIZE(ac97_pcm_defs); 2157 if (chip->device_type != DEVICE_INTEL_ICH4) 2158 i -= 2; /* do not allocate PCM2IN and MIC2 */ 2159 if (chip->spdif_idx < 0) 2160 i--; /* do not allocate S/PDIF */ 2161 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs); 2162 if (err < 0) 2163 goto __err; 2164 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0]; 2165 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1]; 2166 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2]; 2167 if (chip->spdif_idx >= 0) 2168 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3]; 2169 if (chip->device_type == DEVICE_INTEL_ICH4) { 2170 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4]; 2171 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5]; 2172 } 2173 /* enable separate SDINs for ICH4 */ 2174 if (chip->device_type == DEVICE_INTEL_ICH4) { 2175 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm; 2176 u8 tmp = igetbyte(chip, ICHREG(SDM)); 2177 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK); 2178 if (pcm) { 2179 tmp |= ICH_SE; /* steer enable for multiple SDINs */ 2180 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT; 2181 for (i = 1; i < 4; i++) { 2182 if (pcm->r[0].codec[i]) { 2183 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT; 2184 break; 2185 } 2186 } 2187 } else { 2188 tmp &= ~ICH_SE; /* steer disable */ 2189 } 2190 iputbyte(chip, ICHREG(SDM), tmp); 2191 } 2192 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { 2193 chip->multi4 = 1; 2194 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) { 2195 chip->multi6 = 1; 2196 if (chip->ac97[0]->flags & AC97_HAS_8CH) 2197 chip->multi8 = 1; 2198 } 2199 } 2200 if (pbus->pcms[0].r[1].rslots[0]) { 2201 chip->dra = 1; 2202 } 2203 if (chip->device_type == DEVICE_INTEL_ICH4) { 2204 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20) 2205 chip->smp20bit = 1; 2206 } 2207 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2208 /* 48kHz only */ 2209 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000; 2210 } 2211 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { 2212 /* use slot 10/11 for SPDIF */ 2213 u32 val; 2214 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK; 2215 val |= ICH_PCM_SPDIF_1011; 2216 iputdword(chip, ICHREG(GLOB_CNT), val); 2217 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4); 2218 } 2219 chip->in_ac97_init = 0; 2220 return 0; 2221 2222 __err: 2223 /* clear the cold-reset bit for the next chance */ 2224 if (chip->device_type != DEVICE_ALI) 2225 iputdword(chip, ICHREG(GLOB_CNT), 2226 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); 2227 return err; 2228} 2229 2230 2231/* 2232 * 2233 */ 2234 2235static void do_ali_reset(struct intel8x0 *chip) 2236{ 2237 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET); 2238 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383); 2239 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383); 2240 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383); 2241 iputdword(chip, ICHREG(ALI_INTERFACECR), 2242 ICH_ALI_IF_PI|ICH_ALI_IF_PO); 2243 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000); 2244 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000); 2245} 2246 2247#ifdef CONFIG_SND_AC97_POWER_SAVE 2248static struct snd_pci_quirk ich_chip_reset_mode[] = { 2249 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1), 2250 { } /* end */ 2251}; 2252 2253static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip) 2254{ 2255 unsigned int cnt; 2256 /* ACLink on, 2 channels */ 2257 2258 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode)) 2259 return -EIO; 2260 2261 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2262 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); 2263 2264 /* do cold reset - the full ac97 powerdown may leave the controller 2265 * in a warm state but actually it cannot communicate with the codec. 2266 */ 2267 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD); 2268 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2269 udelay(10); 2270 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD); 2271 msleep(1); 2272 return 0; 2273} 2274#define snd_intel8x0_ich_chip_can_cold_reset(chip) \ 2275 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode)) 2276#else 2277#define snd_intel8x0_ich_chip_cold_reset(chip) 0 2278#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0) 2279#endif 2280 2281static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip) 2282{ 2283 unsigned long end_time; 2284 unsigned int cnt; 2285 /* ACLink on, 2 channels */ 2286 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2287 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); 2288 /* finish cold or do warm reset */ 2289 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; 2290 iputdword(chip, ICHREG(GLOB_CNT), cnt); 2291 end_time = (jiffies + (HZ / 4)) + 1; 2292 do { 2293 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) 2294 return 0; 2295 schedule_timeout_uninterruptible(1); 2296 } while (time_after_eq(end_time, jiffies)); 2297 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n", 2298 igetdword(chip, ICHREG(GLOB_CNT))); 2299 return -EIO; 2300} 2301 2302static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing) 2303{ 2304 unsigned long end_time; 2305 unsigned int status, nstatus; 2306 unsigned int cnt; 2307 int err; 2308 2309 /* put logic to right state */ 2310 /* first clear status bits */ 2311 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT; 2312 if (chip->device_type == DEVICE_NFORCE) 2313 status |= ICH_NVSPINT; 2314 cnt = igetdword(chip, ICHREG(GLOB_STA)); 2315 iputdword(chip, ICHREG(GLOB_STA), cnt & status); 2316 2317 if (snd_intel8x0_ich_chip_can_cold_reset(chip)) 2318 err = snd_intel8x0_ich_chip_cold_reset(chip); 2319 else 2320 err = snd_intel8x0_ich_chip_reset(chip); 2321 if (err < 0) 2322 return err; 2323 2324 if (probing) { 2325 /* wait for any codec ready status. 2326 * Once it becomes ready it should remain ready 2327 * as long as we do not disable the ac97 link. 2328 */ 2329 end_time = jiffies + HZ; 2330 do { 2331 status = igetdword(chip, ICHREG(GLOB_STA)) & 2332 chip->codec_isr_bits; 2333 if (status) 2334 break; 2335 schedule_timeout_uninterruptible(1); 2336 } while (time_after_eq(end_time, jiffies)); 2337 if (! status) { 2338 /* no codec is found */ 2339 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", 2340 igetdword(chip, ICHREG(GLOB_STA))); 2341 return -EIO; 2342 } 2343 2344 /* wait for other codecs ready status. */ 2345 end_time = jiffies + HZ / 4; 2346 while (status != chip->codec_isr_bits && 2347 time_after_eq(end_time, jiffies)) { 2348 schedule_timeout_uninterruptible(1); 2349 status |= igetdword(chip, ICHREG(GLOB_STA)) & 2350 chip->codec_isr_bits; 2351 } 2352 2353 } else { 2354 /* resume phase */ 2355 int i; 2356 status = 0; 2357 for (i = 0; i < chip->ncodecs; i++) 2358 if (chip->ac97[i]) 2359 status |= chip->codec_bit[chip->ac97_sdin[i]]; 2360 /* wait until all the probed codecs are ready */ 2361 end_time = jiffies + HZ; 2362 do { 2363 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & 2364 chip->codec_isr_bits; 2365 if (status == nstatus) 2366 break; 2367 schedule_timeout_uninterruptible(1); 2368 } while (time_after_eq(end_time, jiffies)); 2369 } 2370 2371 if (chip->device_type == DEVICE_SIS) { 2372 /* unmute the output on SIS7012 */ 2373 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); 2374 } 2375 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2376 /* enable SPDIF interrupt */ 2377 unsigned int val; 2378 pci_read_config_dword(chip->pci, 0x4c, &val); 2379 val |= 0x1000000; 2380 pci_write_config_dword(chip->pci, 0x4c, val); 2381 } 2382 return 0; 2383} 2384 2385static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing) 2386{ 2387 u32 reg; 2388 int i = 0; 2389 2390 reg = igetdword(chip, ICHREG(ALI_SCR)); 2391 if ((reg & 2) == 0) /* Cold required */ 2392 reg |= 2; 2393 else 2394 reg |= 1; /* Warm */ 2395 reg &= ~0x80000000; /* ACLink on */ 2396 iputdword(chip, ICHREG(ALI_SCR), reg); 2397 2398 for (i = 0; i < HZ / 2; i++) { 2399 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO)) 2400 goto __ok; 2401 schedule_timeout_uninterruptible(1); 2402 } 2403 snd_printk(KERN_ERR "AC'97 reset failed.\n"); 2404 if (probing) 2405 return -EIO; 2406 2407 __ok: 2408 for (i = 0; i < HZ / 2; i++) { 2409 reg = igetdword(chip, ICHREG(ALI_RTSR)); 2410 if (reg & 0x80) /* primary codec */ 2411 break; 2412 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80); 2413 schedule_timeout_uninterruptible(1); 2414 } 2415 2416 do_ali_reset(chip); 2417 return 0; 2418} 2419 2420static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing) 2421{ 2422 unsigned int i, timeout; 2423 int err; 2424 2425 if (chip->device_type != DEVICE_ALI) { 2426 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0) 2427 return err; 2428 iagetword(chip, 0); /* clear semaphore flag */ 2429 } else { 2430 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0) 2431 return err; 2432 } 2433 2434 /* disable interrupts */ 2435 for (i = 0; i < chip->bdbars_count; i++) 2436 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2437 /* reset channels */ 2438 for (i = 0; i < chip->bdbars_count; i++) 2439 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2440 for (i = 0; i < chip->bdbars_count; i++) { 2441 timeout = 100000; 2442 while (--timeout != 0) { 2443 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0) 2444 break; 2445 } 2446 if (timeout == 0) 2447 printk(KERN_ERR "intel8x0: reset of registers failed?\n"); 2448 } 2449 /* initialize Buffer Descriptor Lists */ 2450 for (i = 0; i < chip->bdbars_count; i++) 2451 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, 2452 chip->ichd[i].bdbar_addr); 2453 return 0; 2454} 2455 2456static int snd_intel8x0_free(struct intel8x0 *chip) 2457{ 2458 unsigned int i; 2459 2460 if (chip->irq < 0) 2461 goto __hw_end; 2462 /* disable interrupts */ 2463 for (i = 0; i < chip->bdbars_count; i++) 2464 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2465 /* reset channels */ 2466 for (i = 0; i < chip->bdbars_count; i++) 2467 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2468 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2469 /* stop the spdif interrupt */ 2470 unsigned int val; 2471 pci_read_config_dword(chip->pci, 0x4c, &val); 2472 val &= ~0x1000000; 2473 pci_write_config_dword(chip->pci, 0x4c, val); 2474 } 2475 /* --- */ 2476 2477 __hw_end: 2478 if (chip->irq >= 0) 2479 free_irq(chip->irq, chip); 2480 if (chip->bdbars.area) { 2481 if (chip->fix_nocache) 2482 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0); 2483 snd_dma_free_pages(&chip->bdbars); 2484 } 2485 if (chip->addr) 2486 pci_iounmap(chip->pci, chip->addr); 2487 if (chip->bmaddr) 2488 pci_iounmap(chip->pci, chip->bmaddr); 2489 pci_release_regions(chip->pci); 2490 pci_disable_device(chip->pci); 2491 kfree(chip); 2492 return 0; 2493} 2494 2495#ifdef CONFIG_PM 2496/* 2497 * power management 2498 */ 2499static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state) 2500{ 2501 struct snd_card *card = pci_get_drvdata(pci); 2502 struct intel8x0 *chip = card->private_data; 2503 int i; 2504 2505 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2506 for (i = 0; i < chip->pcm_devs; i++) 2507 snd_pcm_suspend_all(chip->pcm[i]); 2508 /* clear nocache */ 2509 if (chip->fix_nocache) { 2510 for (i = 0; i < chip->bdbars_count; i++) { 2511 struct ichdev *ichdev = &chip->ichd[i]; 2512 if (ichdev->substream && ichdev->page_attr_changed) { 2513 struct snd_pcm_runtime *runtime = ichdev->substream->runtime; 2514 if (runtime->dma_area) 2515 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); 2516 } 2517 } 2518 } 2519 for (i = 0; i < chip->ncodecs; i++) 2520 snd_ac97_suspend(chip->ac97[i]); 2521 if (chip->device_type == DEVICE_INTEL_ICH4) 2522 chip->sdm_saved = igetbyte(chip, ICHREG(SDM)); 2523 2524 if (chip->irq >= 0) { 2525 free_irq(chip->irq, chip); 2526 chip->irq = -1; 2527 } 2528 pci_disable_device(pci); 2529 pci_save_state(pci); 2530 /* The call below may disable built-in speaker on some laptops 2531 * after S2RAM. So, don't touch it. 2532 */ 2533 /* pci_set_power_state(pci, pci_choose_state(pci, state)); */ 2534 return 0; 2535} 2536 2537static int intel8x0_resume(struct pci_dev *pci) 2538{ 2539 struct snd_card *card = pci_get_drvdata(pci); 2540 struct intel8x0 *chip = card->private_data; 2541 int i; 2542 2543 pci_set_power_state(pci, PCI_D0); 2544 pci_restore_state(pci); 2545 if (pci_enable_device(pci) < 0) { 2546 printk(KERN_ERR "intel8x0: pci_enable_device failed, " 2547 "disabling device\n"); 2548 snd_card_disconnect(card); 2549 return -EIO; 2550 } 2551 pci_set_master(pci); 2552 snd_intel8x0_chip_init(chip, 0); 2553 if (request_irq(pci->irq, snd_intel8x0_interrupt, 2554 IRQF_SHARED, card->shortname, chip)) { 2555 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, " 2556 "disabling device\n", pci->irq); 2557 snd_card_disconnect(card); 2558 return -EIO; 2559 } 2560 chip->irq = pci->irq; 2561 synchronize_irq(chip->irq); 2562 2563 /* re-initialize mixer stuff */ 2564 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { 2565 /* enable separate SDINs for ICH4 */ 2566 iputbyte(chip, ICHREG(SDM), chip->sdm_saved); 2567 /* use slot 10/11 for SPDIF */ 2568 iputdword(chip, ICHREG(GLOB_CNT), 2569 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) | 2570 ICH_PCM_SPDIF_1011); 2571 } 2572 2573 /* refill nocache */ 2574 if (chip->fix_nocache) 2575 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); 2576 2577 for (i = 0; i < chip->ncodecs; i++) 2578 snd_ac97_resume(chip->ac97[i]); 2579 2580 /* refill nocache */ 2581 if (chip->fix_nocache) { 2582 for (i = 0; i < chip->bdbars_count; i++) { 2583 struct ichdev *ichdev = &chip->ichd[i]; 2584 if (ichdev->substream && ichdev->page_attr_changed) { 2585 struct snd_pcm_runtime *runtime = ichdev->substream->runtime; 2586 if (runtime->dma_area) 2587 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); 2588 } 2589 } 2590 } 2591 2592 /* resume status */ 2593 for (i = 0; i < chip->bdbars_count; i++) { 2594 struct ichdev *ichdev = &chip->ichd[i]; 2595 unsigned long port = ichdev->reg_offset; 2596 if (! ichdev->substream || ! ichdev->suspended) 2597 continue; 2598 if (ichdev->ichd == ICHD_PCMOUT) 2599 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime); 2600 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 2601 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 2602 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ); 2603 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 2604 } 2605 2606 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2607 return 0; 2608} 2609#endif /* CONFIG_PM */ 2610 2611#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */ 2612 2613static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip) 2614{ 2615 struct snd_pcm_substream *subs; 2616 struct ichdev *ichdev; 2617 unsigned long port; 2618 unsigned long pos, pos1, t; 2619 int civ, timeout = 1000, attempt = 1; 2620 struct timespec start_time, stop_time; 2621 2622 if (chip->ac97_bus->clock != 48000) 2623 return; /* specified in module option */ 2624 2625 __again: 2626 subs = chip->pcm[0]->streams[0].substream; 2627 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) { 2628 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n"); 2629 return; 2630 } 2631 ichdev = &chip->ichd[ICHD_PCMOUT]; 2632 ichdev->physbuf = subs->dma_buffer.addr; 2633 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE; 2634 ichdev->substream = NULL; /* don't process interrupts */ 2635 2636 /* set rate */ 2637 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) { 2638 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock); 2639 return; 2640 } 2641 snd_intel8x0_setup_periods(chip, ichdev); 2642 port = ichdev->reg_offset; 2643 spin_lock_irq(&chip->reg_lock); 2644 chip->in_measurement = 1; 2645 /* trigger */ 2646 if (chip->device_type != DEVICE_ALI) 2647 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM); 2648 else { 2649 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 2650 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot); 2651 } 2652 do_posix_clock_monotonic_gettime(&start_time); 2653 spin_unlock_irq(&chip->reg_lock); 2654 msleep(50); 2655 spin_lock_irq(&chip->reg_lock); 2656 /* check the position */ 2657 do { 2658 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); 2659 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); 2660 if (pos1 == 0) { 2661 udelay(10); 2662 continue; 2663 } 2664 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) && 2665 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) 2666 break; 2667 } while (timeout--); 2668 if (pos1 == 0) { /* oops, this value is not reliable */ 2669 pos = 0; 2670 } else { 2671 pos = ichdev->fragsize1; 2672 pos -= pos1 << ichdev->pos_shift; 2673 pos += ichdev->position; 2674 } 2675 chip->in_measurement = 0; 2676 do_posix_clock_monotonic_gettime(&stop_time); 2677 /* stop */ 2678 if (chip->device_type == DEVICE_ALI) { 2679 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16)); 2680 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2681 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 2682 ; 2683 } else { 2684 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2685 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) 2686 ; 2687 } 2688 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 2689 spin_unlock_irq(&chip->reg_lock); 2690 2691 if (pos == 0) { 2692 snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n"); 2693 __retry: 2694 if (attempt < 3) { 2695 msleep(300); 2696 attempt++; 2697 goto __again; 2698 } 2699 goto __end; 2700 } 2701 2702 pos /= 4; 2703 t = stop_time.tv_sec - start_time.tv_sec; 2704 t *= 1000000; 2705 t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000; 2706 printk(KERN_INFO "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos); 2707 if (t == 0) { 2708 snd_printk(KERN_ERR "intel8x0: ?? calculation error..\n"); 2709 goto __retry; 2710 } 2711 pos *= 1000; 2712 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t; 2713 if (pos < 40000 || pos >= 60000) { 2714 /* abnormal value. hw problem? */ 2715 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos); 2716 goto __retry; 2717 } else if (pos > 40500 && pos < 41500) 2718 /* first exception - 41000Hz reference clock */ 2719 chip->ac97_bus->clock = 41000; 2720 else if (pos > 43600 && pos < 44600) 2721 /* second exception - 44100HZ reference clock */ 2722 chip->ac97_bus->clock = 44100; 2723 else if (pos < 47500 || pos > 48500) 2724 /* not 48000Hz, tuning the clock.. */ 2725 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos; 2726 __end: 2727 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock); 2728 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0); 2729} 2730 2731static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = { 2732 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000), 2733 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100), 2734 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000), 2735 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000), 2736 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000), 2737 { } /* terminator */ 2738}; 2739 2740static int __devinit intel8x0_in_clock_list(struct intel8x0 *chip) 2741{ 2742 struct pci_dev *pci = chip->pci; 2743 const struct snd_pci_quirk *wl; 2744 2745 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list); 2746 if (!wl) 2747 return 0; 2748 printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n", 2749 pci->subsystem_vendor, pci->subsystem_device, wl->value); 2750 chip->ac97_bus->clock = wl->value; 2751 return 1; 2752} 2753 2754#ifdef CONFIG_PROC_FS 2755static void snd_intel8x0_proc_read(struct snd_info_entry * entry, 2756 struct snd_info_buffer *buffer) 2757{ 2758 struct intel8x0 *chip = entry->private_data; 2759 unsigned int tmp; 2760 2761 snd_iprintf(buffer, "Intel8x0\n\n"); 2762 if (chip->device_type == DEVICE_ALI) 2763 return; 2764 tmp = igetdword(chip, ICHREG(GLOB_STA)); 2765 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT))); 2766 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); 2767 if (chip->device_type == DEVICE_INTEL_ICH4) 2768 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM))); 2769 snd_iprintf(buffer, "AC'97 codecs ready :"); 2770 if (tmp & chip->codec_isr_bits) { 2771 int i; 2772 static const char *codecs[3] = { 2773 "primary", "secondary", "tertiary" 2774 }; 2775 for (i = 0; i < chip->max_codecs; i++) 2776 if (tmp & chip->codec_bit[i]) 2777 snd_iprintf(buffer, " %s", codecs[i]); 2778 } else 2779 snd_iprintf(buffer, " none"); 2780 snd_iprintf(buffer, "\n"); 2781 if (chip->device_type == DEVICE_INTEL_ICH4 || 2782 chip->device_type == DEVICE_SIS) 2783 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n", 2784 chip->ac97_sdin[0], 2785 chip->ac97_sdin[1], 2786 chip->ac97_sdin[2]); 2787} 2788 2789static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip) 2790{ 2791 struct snd_info_entry *entry; 2792 2793 if (! snd_card_proc_new(chip->card, "intel8x0", &entry)) 2794 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read); 2795} 2796#else 2797#define snd_intel8x0_proc_init(x) 2798#endif 2799 2800static int snd_intel8x0_dev_free(struct snd_device *device) 2801{ 2802 struct intel8x0 *chip = device->device_data; 2803 return snd_intel8x0_free(chip); 2804} 2805 2806struct ich_reg_info { 2807 unsigned int int_sta_mask; 2808 unsigned int offset; 2809}; 2810 2811static unsigned int ich_codec_bits[3] = { 2812 ICH_PCR, ICH_SCR, ICH_TCR 2813}; 2814static unsigned int sis_codec_bits[3] = { 2815 ICH_PCR, ICH_SCR, ICH_SIS_TCR 2816}; 2817 2818static int __devinit snd_intel8x0_create(struct snd_card *card, 2819 struct pci_dev *pci, 2820 unsigned long device_type, 2821 struct intel8x0 ** r_intel8x0) 2822{ 2823 struct intel8x0 *chip; 2824 int err; 2825 unsigned int i; 2826 unsigned int int_sta_masks; 2827 struct ichdev *ichdev; 2828 static struct snd_device_ops ops = { 2829 .dev_free = snd_intel8x0_dev_free, 2830 }; 2831 2832 static unsigned int bdbars[] = { 2833 3, /* DEVICE_INTEL */ 2834 6, /* DEVICE_INTEL_ICH4 */ 2835 3, /* DEVICE_SIS */ 2836 6, /* DEVICE_ALI */ 2837 4, /* DEVICE_NFORCE */ 2838 }; 2839 static struct ich_reg_info intel_regs[6] = { 2840 { ICH_PIINT, 0 }, 2841 { ICH_POINT, 0x10 }, 2842 { ICH_MCINT, 0x20 }, 2843 { ICH_M2INT, 0x40 }, 2844 { ICH_P2INT, 0x50 }, 2845 { ICH_SPINT, 0x60 }, 2846 }; 2847 static struct ich_reg_info nforce_regs[4] = { 2848 { ICH_PIINT, 0 }, 2849 { ICH_POINT, 0x10 }, 2850 { ICH_MCINT, 0x20 }, 2851 { ICH_NVSPINT, 0x70 }, 2852 }; 2853 static struct ich_reg_info ali_regs[6] = { 2854 { ALI_INT_PCMIN, 0x40 }, 2855 { ALI_INT_PCMOUT, 0x50 }, 2856 { ALI_INT_MICIN, 0x60 }, 2857 { ALI_INT_CODECSPDIFOUT, 0x70 }, 2858 { ALI_INT_SPDIFIN, 0xa0 }, 2859 { ALI_INT_SPDIFOUT, 0xb0 }, 2860 }; 2861 struct ich_reg_info *tbl; 2862 2863 *r_intel8x0 = NULL; 2864 2865 if ((err = pci_enable_device(pci)) < 0) 2866 return err; 2867 2868 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2869 if (chip == NULL) { 2870 pci_disable_device(pci); 2871 return -ENOMEM; 2872 } 2873 spin_lock_init(&chip->reg_lock); 2874 chip->device_type = device_type; 2875 chip->card = card; 2876 chip->pci = pci; 2877 chip->irq = -1; 2878 2879 /* module parameters */ 2880 chip->buggy_irq = buggy_irq; 2881 chip->buggy_semaphore = buggy_semaphore; 2882 if (xbox) 2883 chip->xbox = 1; 2884 2885 if (pci->vendor == PCI_VENDOR_ID_INTEL && 2886 pci->device == PCI_DEVICE_ID_INTEL_440MX) 2887 chip->fix_nocache = 1; 2888 2889 if ((err = pci_request_regions(pci, card->shortname)) < 0) { 2890 kfree(chip); 2891 pci_disable_device(pci); 2892 return err; 2893 } 2894 2895 if (device_type == DEVICE_ALI) { 2896 /* ALI5455 has no ac97 region */ 2897 chip->bmaddr = pci_iomap(pci, 0, 0); 2898 goto port_inited; 2899 } 2900 2901 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */ 2902 chip->addr = pci_iomap(pci, 2, 0); 2903 else 2904 chip->addr = pci_iomap(pci, 0, 0); 2905 if (!chip->addr) { 2906 snd_printk(KERN_ERR "AC'97 space ioremap problem\n"); 2907 snd_intel8x0_free(chip); 2908 return -EIO; 2909 } 2910 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */ 2911 chip->bmaddr = pci_iomap(pci, 3, 0); 2912 else 2913 chip->bmaddr = pci_iomap(pci, 1, 0); 2914 if (!chip->bmaddr) { 2915 snd_printk(KERN_ERR "Controller space ioremap problem\n"); 2916 snd_intel8x0_free(chip); 2917 return -EIO; 2918 } 2919 2920 port_inited: 2921 chip->bdbars_count = bdbars[device_type]; 2922 2923 /* initialize offsets */ 2924 switch (device_type) { 2925 case DEVICE_NFORCE: 2926 tbl = nforce_regs; 2927 break; 2928 case DEVICE_ALI: 2929 tbl = ali_regs; 2930 break; 2931 default: 2932 tbl = intel_regs; 2933 break; 2934 } 2935 for (i = 0; i < chip->bdbars_count; i++) { 2936 ichdev = &chip->ichd[i]; 2937 ichdev->ichd = i; 2938 ichdev->reg_offset = tbl[i].offset; 2939 ichdev->int_sta_mask = tbl[i].int_sta_mask; 2940 if (device_type == DEVICE_SIS) { 2941 /* SiS 7012 swaps the registers */ 2942 ichdev->roff_sr = ICH_REG_OFF_PICB; 2943 ichdev->roff_picb = ICH_REG_OFF_SR; 2944 } else { 2945 ichdev->roff_sr = ICH_REG_OFF_SR; 2946 ichdev->roff_picb = ICH_REG_OFF_PICB; 2947 } 2948 if (device_type == DEVICE_ALI) 2949 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; 2950 /* SIS7012 handles the pcm data in bytes, others are in samples */ 2951 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; 2952 } 2953 2954 /* allocate buffer descriptor lists */ 2955 /* the start of each lists must be aligned to 8 bytes */ 2956 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 2957 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, 2958 &chip->bdbars) < 0) { 2959 snd_intel8x0_free(chip); 2960 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n"); 2961 return -ENOMEM; 2962 } 2963 /* tables must be aligned to 8 bytes here, but the kernel pages 2964 are much bigger, so we don't care (on i386) */ 2965 if (chip->fix_nocache) 2966 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); 2967 int_sta_masks = 0; 2968 for (i = 0; i < chip->bdbars_count; i++) { 2969 ichdev = &chip->ichd[i]; 2970 ichdev->bdbar = ((u32 *)chip->bdbars.area) + 2971 (i * ICH_MAX_FRAGS * 2); 2972 ichdev->bdbar_addr = chip->bdbars.addr + 2973 (i * sizeof(u32) * ICH_MAX_FRAGS * 2); 2974 int_sta_masks |= ichdev->int_sta_mask; 2975 } 2976 chip->int_sta_reg = device_type == DEVICE_ALI ? 2977 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA; 2978 chip->int_sta_mask = int_sta_masks; 2979 2980 pci_set_master(pci); 2981 2982 switch(chip->device_type) { 2983 case DEVICE_INTEL_ICH4: 2984 /* ICH4 can have three codecs */ 2985 chip->max_codecs = 3; 2986 chip->codec_bit = ich_codec_bits; 2987 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI; 2988 break; 2989 case DEVICE_SIS: 2990 /* recent SIS7012 can have three codecs */ 2991 chip->max_codecs = 3; 2992 chip->codec_bit = sis_codec_bits; 2993 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI; 2994 break; 2995 default: 2996 /* others up to two codecs */ 2997 chip->max_codecs = 2; 2998 chip->codec_bit = ich_codec_bits; 2999 chip->codec_ready_bits = ICH_PRI | ICH_SRI; 3000 break; 3001 } 3002 for (i = 0; i < chip->max_codecs; i++) 3003 chip->codec_isr_bits |= chip->codec_bit[i]; 3004 3005 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) { 3006 snd_intel8x0_free(chip); 3007 return err; 3008 } 3009 3010 /* request irq after initializaing int_sta_mask, etc */ 3011 if (request_irq(pci->irq, snd_intel8x0_interrupt, 3012 IRQF_SHARED, card->shortname, chip)) { 3013 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 3014 snd_intel8x0_free(chip); 3015 return -EBUSY; 3016 } 3017 chip->irq = pci->irq; 3018 3019 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 3020 snd_intel8x0_free(chip); 3021 return err; 3022 } 3023 3024 snd_card_set_dev(card, &pci->dev); 3025 3026 *r_intel8x0 = chip; 3027 return 0; 3028} 3029 3030static struct shortname_table { 3031 unsigned int id; 3032 const char *s; 3033} shortnames[] __devinitdata = { 3034 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" }, 3035 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" }, 3036 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" }, 3037 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" }, 3038 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" }, 3039 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" }, 3040 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" }, 3041 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" }, 3042 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" }, 3043 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" }, 3044 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" }, 3045 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" }, 3046 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" }, 3047 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" }, 3048 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" }, 3049 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" }, 3050 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" }, 3051 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" }, 3052 { 0x003a, "NVidia MCP04" }, 3053 { 0x746d, "AMD AMD8111" }, 3054 { 0x7445, "AMD AMD768" }, 3055 { 0x5455, "ALi M5455" }, 3056 { 0, NULL }, 3057}; 3058 3059static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = { 3060 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1), 3061 { } /* end */ 3062}; 3063 3064/* look up white/black list for SPDIF over ac-link */ 3065static int __devinit check_default_spdif_aclink(struct pci_dev *pci) 3066{ 3067 const struct snd_pci_quirk *w; 3068 3069 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults); 3070 if (w) { 3071 if (w->value) 3072 snd_printdd(KERN_INFO "intel8x0: Using SPDIF over " 3073 "AC-Link for %s\n", w->name); 3074 else 3075 snd_printdd(KERN_INFO "intel8x0: Using integrated " 3076 "SPDIF DMA for %s\n", w->name); 3077 return w->value; 3078 } 3079 return 0; 3080} 3081 3082static int __devinit snd_intel8x0_probe(struct pci_dev *pci, 3083 const struct pci_device_id *pci_id) 3084{ 3085 struct snd_card *card; 3086 struct intel8x0 *chip; 3087 int err; 3088 struct shortname_table *name; 3089 3090 err = snd_card_create(index, id, THIS_MODULE, 0, &card); 3091 if (err < 0) 3092 return err; 3093 3094 if (spdif_aclink < 0) 3095 spdif_aclink = check_default_spdif_aclink(pci); 3096 3097 strcpy(card->driver, "ICH"); 3098 if (!spdif_aclink) { 3099 switch (pci_id->driver_data) { 3100 case DEVICE_NFORCE: 3101 strcpy(card->driver, "NFORCE"); 3102 break; 3103 case DEVICE_INTEL_ICH4: 3104 strcpy(card->driver, "ICH4"); 3105 } 3106 } 3107 3108 strcpy(card->shortname, "Intel ICH"); 3109 for (name = shortnames; name->id; name++) { 3110 if (pci->device == name->id) { 3111 strcpy(card->shortname, name->s); 3112 break; 3113 } 3114 } 3115 3116 if (buggy_irq < 0) { 3117 /* some Nforce[2] and ICH boards have problems with IRQ handling. 3118 * Needs to return IRQ_HANDLED for unknown irqs. 3119 */ 3120 if (pci_id->driver_data == DEVICE_NFORCE) 3121 buggy_irq = 1; 3122 else 3123 buggy_irq = 0; 3124 } 3125 3126 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, 3127 &chip)) < 0) { 3128 snd_card_free(card); 3129 return err; 3130 } 3131 card->private_data = chip; 3132 3133 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) { 3134 snd_card_free(card); 3135 return err; 3136 } 3137 if ((err = snd_intel8x0_pcm(chip)) < 0) { 3138 snd_card_free(card); 3139 return err; 3140 } 3141 3142 snd_intel8x0_proc_init(chip); 3143 3144 snprintf(card->longname, sizeof(card->longname), 3145 "%s with %s at irq %i", card->shortname, 3146 snd_ac97_get_short_name(chip->ac97[0]), chip->irq); 3147 3148 if (ac97_clock == 0 || ac97_clock == 1) { 3149 if (ac97_clock == 0) { 3150 if (intel8x0_in_clock_list(chip) == 0) 3151 intel8x0_measure_ac97_clock(chip); 3152 } else { 3153 intel8x0_measure_ac97_clock(chip); 3154 } 3155 } 3156 3157 if ((err = snd_card_register(card)) < 0) { 3158 snd_card_free(card); 3159 return err; 3160 } 3161 pci_set_drvdata(pci, card); 3162 return 0; 3163} 3164 3165static void __devexit snd_intel8x0_remove(struct pci_dev *pci) 3166{ 3167 snd_card_free(pci_get_drvdata(pci)); 3168 pci_set_drvdata(pci, NULL); 3169} 3170 3171static struct pci_driver driver = { 3172 .name = "Intel ICH", 3173 .id_table = snd_intel8x0_ids, 3174 .probe = snd_intel8x0_probe, 3175 .remove = __devexit_p(snd_intel8x0_remove), 3176#ifdef CONFIG_PM 3177 .suspend = intel8x0_suspend, 3178 .resume = intel8x0_resume, 3179#endif 3180}; 3181 3182 3183static int __init alsa_card_intel8x0_init(void) 3184{ 3185 return pci_register_driver(&driver); 3186} 3187 3188static void __exit alsa_card_intel8x0_exit(void) 3189{ 3190 pci_unregister_driver(&driver); 3191} 3192 3193module_init(alsa_card_intel8x0_init) 3194module_exit(alsa_card_intel8x0_exit) 3195