1/* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37#include <asm/io.h> 38#include <linux/delay.h> 39#include <linux/interrupt.h> 40#include <linux/kernel.h> 41#include <linux/module.h> 42#include <linux/dma-mapping.h> 43#include <linux/moduleparam.h> 44#include <linux/init.h> 45#include <linux/slab.h> 46#include <linux/pci.h> 47#include <linux/mutex.h> 48#include <linux/reboot.h> 49#include <sound/core.h> 50#include <sound/initval.h> 51#include "hda_codec.h" 52 53 54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 56static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 57static char *model[SNDRV_CARDS]; 58static int position_fix[SNDRV_CARDS]; 59static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 60static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 61static int probe_only[SNDRV_CARDS]; 62static int single_cmd; 63static int enable_msi = -1; 64#ifdef CONFIG_SND_HDA_PATCH_LOADER 65static char *patch[SNDRV_CARDS]; 66#endif 67#ifdef CONFIG_SND_HDA_INPUT_BEEP 68static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 69 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 70#endif 71 72module_param_array(index, int, NULL, 0444); 73MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 74module_param_array(id, charp, NULL, 0444); 75MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 76module_param_array(enable, bool, NULL, 0444); 77MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 78module_param_array(model, charp, NULL, 0444); 79MODULE_PARM_DESC(model, "Use the given board model."); 80module_param_array(position_fix, int, NULL, 0444); 81MODULE_PARM_DESC(position_fix, "Fix DMA pointer " 82 "(0 = auto, 1 = none, 2 = POSBUF)."); 83module_param_array(bdl_pos_adj, int, NULL, 0644); 84MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 85module_param_array(probe_mask, int, NULL, 0444); 86MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 87module_param_array(probe_only, int, NULL, 0444); 88MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 89module_param(single_cmd, bool, 0444); 90MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 91 "(for debugging only)."); 92module_param(enable_msi, int, 0444); 93MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 94#ifdef CONFIG_SND_HDA_PATCH_LOADER 95module_param_array(patch, charp, NULL, 0444); 96MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 97#endif 98#ifdef CONFIG_SND_HDA_INPUT_BEEP 99module_param_array(beep_mode, int, NULL, 0444); 100MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 101 "(0=off, 1=on, 2=mute switch on/off) (default=1)."); 102#endif 103 104#ifdef CONFIG_SND_HDA_POWER_SAVE 105static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 106module_param(power_save, int, 0644); 107MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 108 "(in second, 0 = disable)."); 109 110/* reset the HD-audio controller in power save mode. 111 * this may give more power-saving, but will take longer time to 112 * wake up. 113 */ 114static int power_save_controller = 1; 115module_param(power_save_controller, bool, 0644); 116MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 117#endif 118 119MODULE_LICENSE("GPL"); 120MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 121 "{Intel, ICH6M}," 122 "{Intel, ICH7}," 123 "{Intel, ESB2}," 124 "{Intel, ICH8}," 125 "{Intel, ICH9}," 126 "{Intel, ICH10}," 127 "{Intel, PCH}," 128 "{Intel, CPT}," 129 "{Intel, PBG}," 130 "{Intel, SCH}," 131 "{ATI, SB450}," 132 "{ATI, SB600}," 133 "{ATI, RS600}," 134 "{ATI, RS690}," 135 "{ATI, RS780}," 136 "{ATI, R600}," 137 "{ATI, RV630}," 138 "{ATI, RV610}," 139 "{ATI, RV670}," 140 "{ATI, RV635}," 141 "{ATI, RV620}," 142 "{ATI, RV770}," 143 "{VIA, VT8251}," 144 "{VIA, VT8237A}," 145 "{SiS, SIS966}," 146 "{ULI, M5461}}"); 147MODULE_DESCRIPTION("Intel HDA driver"); 148 149#ifdef CONFIG_SND_VERBOSE_PRINTK 150#define SFX /* nop */ 151#else 152#define SFX "hda-intel: " 153#endif 154 155/* 156 * registers 157 */ 158#define ICH6_REG_GCAP 0x00 159#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */ 160#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */ 161#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */ 162#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */ 163#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */ 164#define ICH6_REG_VMIN 0x02 165#define ICH6_REG_VMAJ 0x03 166#define ICH6_REG_OUTPAY 0x04 167#define ICH6_REG_INPAY 0x06 168#define ICH6_REG_GCTL 0x08 169#define ICH6_GCTL_RESET (1 << 0) /* controller reset */ 170#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */ 171#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ 172#define ICH6_REG_WAKEEN 0x0c 173#define ICH6_REG_STATESTS 0x0e 174#define ICH6_REG_GSTS 0x10 175#define ICH6_GSTS_FSTS (1 << 1) /* flush status */ 176#define ICH6_REG_INTCTL 0x20 177#define ICH6_REG_INTSTS 0x24 178#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */ 179#define ICH6_REG_SYNC 0x34 180#define ICH6_REG_CORBLBASE 0x40 181#define ICH6_REG_CORBUBASE 0x44 182#define ICH6_REG_CORBWP 0x48 183#define ICH6_REG_CORBRP 0x4a 184#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */ 185#define ICH6_REG_CORBCTL 0x4c 186#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */ 187#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ 188#define ICH6_REG_CORBSTS 0x4d 189#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */ 190#define ICH6_REG_CORBSIZE 0x4e 191 192#define ICH6_REG_RIRBLBASE 0x50 193#define ICH6_REG_RIRBUBASE 0x54 194#define ICH6_REG_RIRBWP 0x58 195#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */ 196#define ICH6_REG_RINTCNT 0x5a 197#define ICH6_REG_RIRBCTL 0x5c 198#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ 199#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */ 200#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ 201#define ICH6_REG_RIRBSTS 0x5d 202#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */ 203#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */ 204#define ICH6_REG_RIRBSIZE 0x5e 205 206#define ICH6_REG_IC 0x60 207#define ICH6_REG_IR 0x64 208#define ICH6_REG_IRS 0x68 209#define ICH6_IRS_VALID (1<<1) 210#define ICH6_IRS_BUSY (1<<0) 211 212#define ICH6_REG_DPLBASE 0x70 213#define ICH6_REG_DPUBASE 0x74 214#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ 215 216/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 217enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; 218 219/* stream register offsets from stream base */ 220#define ICH6_REG_SD_CTL 0x00 221#define ICH6_REG_SD_STS 0x03 222#define ICH6_REG_SD_LPIB 0x04 223#define ICH6_REG_SD_CBL 0x08 224#define ICH6_REG_SD_LVI 0x0c 225#define ICH6_REG_SD_FIFOW 0x0e 226#define ICH6_REG_SD_FIFOSIZE 0x10 227#define ICH6_REG_SD_FORMAT 0x12 228#define ICH6_REG_SD_BDLPL 0x18 229#define ICH6_REG_SD_BDLPU 0x1c 230 231/* PCI space */ 232#define ICH6_PCIREG_TCSEL 0x44 233 234/* 235 * other constants 236 */ 237 238/* max number of SDs */ 239/* ICH, ATI and VIA have 4 playback and 4 capture */ 240#define ICH6_NUM_CAPTURE 4 241#define ICH6_NUM_PLAYBACK 4 242 243/* ULI has 6 playback and 5 capture */ 244#define ULI_NUM_CAPTURE 5 245#define ULI_NUM_PLAYBACK 6 246 247/* ATI HDMI has 1 playback and 0 capture */ 248#define ATIHDMI_NUM_CAPTURE 0 249#define ATIHDMI_NUM_PLAYBACK 1 250 251/* TERA has 4 playback and 3 capture */ 252#define TERA_NUM_CAPTURE 3 253#define TERA_NUM_PLAYBACK 4 254 255/* this number is statically defined for simplicity */ 256#define MAX_AZX_DEV 16 257 258/* max number of fragments - we may use more if allocating more pages for BDL */ 259#define BDL_SIZE 4096 260#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) 261#define AZX_MAX_FRAG 32 262/* max buffer size - no h/w limit, you can increase as you like */ 263#define AZX_MAX_BUF_SIZE (1024*1024*1024) 264 265/* RIRB int mask: overrun[2], response[0] */ 266#define RIRB_INT_RESPONSE 0x01 267#define RIRB_INT_OVERRUN 0x04 268#define RIRB_INT_MASK 0x05 269 270/* STATESTS int mask: S3,SD2,SD1,SD0 */ 271#define AZX_MAX_CODECS 8 272#define AZX_DEFAULT_CODECS 4 273#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1) 274 275/* SD_CTL bits */ 276#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ 277#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ 278#define SD_CTL_STRIPE (3 << 16) /* stripe control */ 279#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ 280#define SD_CTL_DIR (1 << 19) /* bi-directional stream */ 281#define SD_CTL_STREAM_TAG_MASK (0xf << 20) 282#define SD_CTL_STREAM_TAG_SHIFT 20 283 284/* SD_CTL and SD_STS */ 285#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ 286#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ 287#define SD_INT_COMPLETE 0x04 /* completion interrupt */ 288#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ 289 SD_INT_COMPLETE) 290 291/* SD_STS */ 292#define SD_STS_FIFO_READY 0x20 /* FIFO ready */ 293 294/* INTCTL and INTSTS */ 295#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ 296#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ 297#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ 298 299/* below are so far hardcoded - should read registers in future */ 300#define ICH6_MAX_CORB_ENTRIES 256 301#define ICH6_MAX_RIRB_ENTRIES 256 302 303/* position fix mode */ 304enum { 305 POS_FIX_AUTO, 306 POS_FIX_LPIB, 307 POS_FIX_POSBUF, 308}; 309 310/* Defines for ATI HD Audio support in SB450 south bridge */ 311#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 312#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 313 314/* Defines for Nvidia HDA support */ 315#define NVIDIA_HDA_TRANSREG_ADDR 0x4e 316#define NVIDIA_HDA_ENABLE_COHBITS 0x0f 317#define NVIDIA_HDA_ISTRM_COH 0x4d 318#define NVIDIA_HDA_OSTRM_COH 0x4c 319#define NVIDIA_HDA_ENABLE_COHBIT 0x01 320 321/* Defines for Intel SCH HDA snoop control */ 322#define INTEL_SCH_HDA_DEVC 0x78 323#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 324 325/* Define IN stream 0 FIFO size offset in VIA controller */ 326#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 327/* Define VIA HD Audio Device ID*/ 328#define VIA_HDAC_DEVICE_ID 0x3288 329 330/* HD Audio class code */ 331#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 332 333/* 334 */ 335 336struct azx_dev { 337 struct snd_dma_buffer bdl; /* BDL buffer */ 338 u32 *posbuf; /* position buffer pointer */ 339 340 unsigned int bufsize; /* size of the play buffer in bytes */ 341 unsigned int period_bytes; /* size of the period in bytes */ 342 unsigned int frags; /* number for period in the play buffer */ 343 unsigned int fifo_size; /* FIFO size */ 344 unsigned long start_wallclk; /* start + minimum wallclk */ 345 unsigned long period_wallclk; /* wallclk for period */ 346 347 void __iomem *sd_addr; /* stream descriptor pointer */ 348 349 u32 sd_int_sta_mask; /* stream int status mask */ 350 351 /* pcm support */ 352 struct snd_pcm_substream *substream; /* assigned substream, 353 * set in PCM open 354 */ 355 unsigned int format_val; /* format value to be set in the 356 * controller and the codec 357 */ 358 unsigned char stream_tag; /* assigned stream */ 359 unsigned char index; /* stream index */ 360 int device; /* last device number assigned to */ 361 362 unsigned int opened :1; 363 unsigned int running :1; 364 unsigned int irq_pending :1; 365 /* 366 * For VIA: 367 * A flag to ensure DMA position is 0 368 * when link position is not greater than FIFO size 369 */ 370 unsigned int insufficient :1; 371}; 372 373/* CORB/RIRB */ 374struct azx_rb { 375 u32 *buf; /* CORB/RIRB buffer 376 * Each CORB entry is 4byte, RIRB is 8byte 377 */ 378 dma_addr_t addr; /* physical address of CORB/RIRB buffer */ 379 /* for RIRB */ 380 unsigned short rp, wp; /* read/write pointers */ 381 int cmds[AZX_MAX_CODECS]; /* number of pending requests */ 382 u32 res[AZX_MAX_CODECS]; /* last read value */ 383}; 384 385struct azx { 386 struct snd_card *card; 387 struct pci_dev *pci; 388 int dev_index; 389 390 /* chip type specific */ 391 int driver_type; 392 int playback_streams; 393 int playback_index_offset; 394 int capture_streams; 395 int capture_index_offset; 396 int num_streams; 397 398 /* pci resources */ 399 unsigned long addr; 400 void __iomem *remap_addr; 401 int irq; 402 403 /* locks */ 404 spinlock_t reg_lock; 405 struct mutex open_mutex; 406 407 /* streams (x num_streams) */ 408 struct azx_dev *azx_dev; 409 410 /* PCM */ 411 struct snd_pcm *pcm[HDA_MAX_PCMS]; 412 413 /* HD codec */ 414 unsigned short codec_mask; 415 int codec_probe_mask; /* copied from probe_mask option */ 416 struct hda_bus *bus; 417 unsigned int beep_mode; 418 419 /* CORB/RIRB */ 420 struct azx_rb corb; 421 struct azx_rb rirb; 422 423 /* CORB/RIRB and position buffers */ 424 struct snd_dma_buffer rb; 425 struct snd_dma_buffer posbuf; 426 427 /* flags */ 428 int position_fix[2]; /* for both playback/capture streams */ 429 int poll_count; 430 unsigned int running :1; 431 unsigned int initialized :1; 432 unsigned int single_cmd :1; 433 unsigned int polling_mode :1; 434 unsigned int msi :1; 435 unsigned int irq_pending_warned :1; 436 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */ 437 unsigned int probing :1; /* codec probing phase */ 438 439 /* for debugging */ 440 unsigned int last_cmd[AZX_MAX_CODECS]; 441 442 /* for pending irqs */ 443 struct work_struct irq_pending_work; 444 445 /* reboot notifier (for mysterious hangup problem at power-down) */ 446 struct notifier_block reboot_notifier; 447}; 448 449/* driver types */ 450enum { 451 AZX_DRIVER_ICH, 452 AZX_DRIVER_PCH, 453 AZX_DRIVER_SCH, 454 AZX_DRIVER_ATI, 455 AZX_DRIVER_ATIHDMI, 456 AZX_DRIVER_VIA, 457 AZX_DRIVER_SIS, 458 AZX_DRIVER_ULI, 459 AZX_DRIVER_NVIDIA, 460 AZX_DRIVER_TERA, 461 AZX_DRIVER_CTX, 462 AZX_DRIVER_GENERIC, 463 AZX_NUM_DRIVERS, /* keep this as last entry */ 464}; 465 466static char *driver_short_names[] __devinitdata = { 467 [AZX_DRIVER_ICH] = "HDA Intel", 468 [AZX_DRIVER_PCH] = "HDA Intel PCH", 469 [AZX_DRIVER_SCH] = "HDA Intel MID", 470 [AZX_DRIVER_ATI] = "HDA ATI SB", 471 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 472 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 473 [AZX_DRIVER_SIS] = "HDA SIS966", 474 [AZX_DRIVER_ULI] = "HDA ULI M5461", 475 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 476 [AZX_DRIVER_TERA] = "HDA Teradici", 477 [AZX_DRIVER_CTX] = "HDA Creative", 478 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 479}; 480 481/* 482 * macros for easy use 483 */ 484#define azx_writel(chip,reg,value) \ 485 writel(value, (chip)->remap_addr + ICH6_REG_##reg) 486#define azx_readl(chip,reg) \ 487 readl((chip)->remap_addr + ICH6_REG_##reg) 488#define azx_writew(chip,reg,value) \ 489 writew(value, (chip)->remap_addr + ICH6_REG_##reg) 490#define azx_readw(chip,reg) \ 491 readw((chip)->remap_addr + ICH6_REG_##reg) 492#define azx_writeb(chip,reg,value) \ 493 writeb(value, (chip)->remap_addr + ICH6_REG_##reg) 494#define azx_readb(chip,reg) \ 495 readb((chip)->remap_addr + ICH6_REG_##reg) 496 497#define azx_sd_writel(dev,reg,value) \ 498 writel(value, (dev)->sd_addr + ICH6_REG_##reg) 499#define azx_sd_readl(dev,reg) \ 500 readl((dev)->sd_addr + ICH6_REG_##reg) 501#define azx_sd_writew(dev,reg,value) \ 502 writew(value, (dev)->sd_addr + ICH6_REG_##reg) 503#define azx_sd_readw(dev,reg) \ 504 readw((dev)->sd_addr + ICH6_REG_##reg) 505#define azx_sd_writeb(dev,reg,value) \ 506 writeb(value, (dev)->sd_addr + ICH6_REG_##reg) 507#define azx_sd_readb(dev,reg) \ 508 readb((dev)->sd_addr + ICH6_REG_##reg) 509 510/* for pcm support */ 511#define get_azx_dev(substream) (substream->runtime->private_data) 512 513static int azx_acquire_irq(struct azx *chip, int do_disconnect); 514static int azx_send_cmd(struct hda_bus *bus, unsigned int val); 515/* 516 * Interface for HD codec 517 */ 518 519/* 520 * CORB / RIRB interface 521 */ 522static int azx_alloc_cmd_io(struct azx *chip) 523{ 524 int err; 525 526 /* single page (at least 4096 bytes) must suffice for both ringbuffes */ 527 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 528 snd_dma_pci_data(chip->pci), 529 PAGE_SIZE, &chip->rb); 530 if (err < 0) { 531 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n"); 532 return err; 533 } 534 return 0; 535} 536 537static void azx_init_cmd_io(struct azx *chip) 538{ 539 spin_lock_irq(&chip->reg_lock); 540 /* CORB set up */ 541 chip->corb.addr = chip->rb.addr; 542 chip->corb.buf = (u32 *)chip->rb.area; 543 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); 544 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); 545 546 /* set the corb size to 256 entries (ULI requires explicitly) */ 547 azx_writeb(chip, CORBSIZE, 0x02); 548 /* set the corb write pointer to 0 */ 549 azx_writew(chip, CORBWP, 0); 550 /* reset the corb hw read pointer */ 551 azx_writew(chip, CORBRP, ICH6_CORBRP_RST); 552 /* enable corb dma */ 553 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); 554 555 /* RIRB set up */ 556 chip->rirb.addr = chip->rb.addr + 2048; 557 chip->rirb.buf = (u32 *)(chip->rb.area + 2048); 558 chip->rirb.wp = chip->rirb.rp = 0; 559 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); 560 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); 561 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); 562 563 /* set the rirb size to 256 entries (ULI requires explicitly) */ 564 azx_writeb(chip, RIRBSIZE, 0x02); 565 /* reset the rirb hw write pointer */ 566 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST); 567 /* set N=1, get RIRB response interrupt for new entry */ 568 if (chip->driver_type == AZX_DRIVER_CTX) 569 azx_writew(chip, RINTCNT, 0xc0); 570 else 571 azx_writew(chip, RINTCNT, 1); 572 /* enable rirb dma and response irq */ 573 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); 574 spin_unlock_irq(&chip->reg_lock); 575} 576 577static void azx_free_cmd_io(struct azx *chip) 578{ 579 spin_lock_irq(&chip->reg_lock); 580 /* disable ringbuffer DMAs */ 581 azx_writeb(chip, RIRBCTL, 0); 582 azx_writeb(chip, CORBCTL, 0); 583 spin_unlock_irq(&chip->reg_lock); 584} 585 586static unsigned int azx_command_addr(u32 cmd) 587{ 588 unsigned int addr = cmd >> 28; 589 590 if (addr >= AZX_MAX_CODECS) { 591 snd_BUG(); 592 addr = 0; 593 } 594 595 return addr; 596} 597 598static unsigned int azx_response_addr(u32 res) 599{ 600 unsigned int addr = res & 0xf; 601 602 if (addr >= AZX_MAX_CODECS) { 603 snd_BUG(); 604 addr = 0; 605 } 606 607 return addr; 608} 609 610/* send a command */ 611static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) 612{ 613 struct azx *chip = bus->private_data; 614 unsigned int addr = azx_command_addr(val); 615 unsigned int wp; 616 617 spin_lock_irq(&chip->reg_lock); 618 619 /* add command to corb */ 620 wp = azx_readb(chip, CORBWP); 621 wp++; 622 wp %= ICH6_MAX_CORB_ENTRIES; 623 624 chip->rirb.cmds[addr]++; 625 chip->corb.buf[wp] = cpu_to_le32(val); 626 azx_writel(chip, CORBWP, wp); 627 628 spin_unlock_irq(&chip->reg_lock); 629 630 return 0; 631} 632 633#define ICH6_RIRB_EX_UNSOL_EV (1<<4) 634 635/* retrieve RIRB entry - called from interrupt handler */ 636static void azx_update_rirb(struct azx *chip) 637{ 638 unsigned int rp, wp; 639 unsigned int addr; 640 u32 res, res_ex; 641 642 wp = azx_readb(chip, RIRBWP); 643 if (wp == chip->rirb.wp) 644 return; 645 chip->rirb.wp = wp; 646 647 while (chip->rirb.rp != wp) { 648 chip->rirb.rp++; 649 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; 650 651 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ 652 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); 653 res = le32_to_cpu(chip->rirb.buf[rp]); 654 addr = azx_response_addr(res_ex); 655 if (res_ex & ICH6_RIRB_EX_UNSOL_EV) 656 snd_hda_queue_unsol_event(chip->bus, res, res_ex); 657 else if (chip->rirb.cmds[addr]) { 658 chip->rirb.res[addr] = res; 659 smp_wmb(); 660 chip->rirb.cmds[addr]--; 661 } else 662 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, " 663 "last cmd=%#08x\n", 664 res, res_ex, 665 chip->last_cmd[addr]); 666 } 667} 668 669/* receive a response */ 670static unsigned int azx_rirb_get_response(struct hda_bus *bus, 671 unsigned int addr) 672{ 673 struct azx *chip = bus->private_data; 674 unsigned long timeout; 675 int do_poll = 0; 676 677 again: 678 timeout = jiffies + msecs_to_jiffies(1000); 679 for (;;) { 680 if (chip->polling_mode || do_poll) { 681 spin_lock_irq(&chip->reg_lock); 682 azx_update_rirb(chip); 683 spin_unlock_irq(&chip->reg_lock); 684 } 685 if (!chip->rirb.cmds[addr]) { 686 smp_rmb(); 687 bus->rirb_error = 0; 688 689 if (!do_poll) 690 chip->poll_count = 0; 691 return chip->rirb.res[addr]; /* the last value */ 692 } 693 if (time_after(jiffies, timeout)) 694 break; 695 if (bus->needs_damn_long_delay) 696 msleep(2); 697 else { 698 udelay(10); 699 cond_resched(); 700 } 701 } 702 703 if (!chip->polling_mode && chip->poll_count < 2) { 704 snd_printdd(SFX "azx_get_response timeout, " 705 "polling the codec once: last cmd=0x%08x\n", 706 chip->last_cmd[addr]); 707 do_poll = 1; 708 chip->poll_count++; 709 goto again; 710 } 711 712 713 if (!chip->polling_mode) { 714 snd_printk(KERN_WARNING SFX "azx_get_response timeout, " 715 "switching to polling mode: last cmd=0x%08x\n", 716 chip->last_cmd[addr]); 717 chip->polling_mode = 1; 718 goto again; 719 } 720 721 if (chip->msi) { 722 snd_printk(KERN_WARNING SFX "No response from codec, " 723 "disabling MSI: last cmd=0x%08x\n", 724 chip->last_cmd[addr]); 725 free_irq(chip->irq, chip); 726 chip->irq = -1; 727 pci_disable_msi(chip->pci); 728 chip->msi = 0; 729 if (azx_acquire_irq(chip, 1) < 0) { 730 bus->rirb_error = 1; 731 return -1; 732 } 733 goto again; 734 } 735 736 if (chip->probing) { 737 /* If this critical timeout happens during the codec probing 738 * phase, this is likely an access to a non-existing codec 739 * slot. Better to return an error and reset the system. 740 */ 741 return -1; 742 } 743 744 /* a fatal communication error; need either to reset or to fallback 745 * to the single_cmd mode 746 */ 747 bus->rirb_error = 1; 748 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) { 749 bus->response_reset = 1; 750 return -1; /* give a chance to retry */ 751 } 752 753 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " 754 "switching to single_cmd mode: last cmd=0x%08x\n", 755 chip->last_cmd[addr]); 756 chip->single_cmd = 1; 757 bus->response_reset = 0; 758 /* release CORB/RIRB */ 759 azx_free_cmd_io(chip); 760 /* disable unsolicited responses */ 761 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL); 762 return -1; 763} 764 765/* 766 * Use the single immediate command instead of CORB/RIRB for simplicity 767 * 768 * Note: according to Intel, this is not preferred use. The command was 769 * intended for the BIOS only, and may get confused with unsolicited 770 * responses. So, we shouldn't use it for normal operation from the 771 * driver. 772 * I left the codes, however, for debugging/testing purposes. 773 */ 774 775/* receive a response */ 776static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) 777{ 778 int timeout = 50; 779 780 while (timeout--) { 781 /* check IRV busy bit */ 782 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { 783 /* reuse rirb.res as the response return value */ 784 chip->rirb.res[addr] = azx_readl(chip, IR); 785 return 0; 786 } 787 udelay(1); 788 } 789 if (printk_ratelimit()) 790 snd_printd(SFX "get_response timeout: IRS=0x%x\n", 791 azx_readw(chip, IRS)); 792 chip->rirb.res[addr] = -1; 793 return -EIO; 794} 795 796/* send a command */ 797static int azx_single_send_cmd(struct hda_bus *bus, u32 val) 798{ 799 struct azx *chip = bus->private_data; 800 unsigned int addr = azx_command_addr(val); 801 int timeout = 50; 802 803 bus->rirb_error = 0; 804 while (timeout--) { 805 /* check ICB busy bit */ 806 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { 807 /* Clear IRV valid bit */ 808 azx_writew(chip, IRS, azx_readw(chip, IRS) | 809 ICH6_IRS_VALID); 810 azx_writel(chip, IC, val); 811 azx_writew(chip, IRS, azx_readw(chip, IRS) | 812 ICH6_IRS_BUSY); 813 return azx_single_wait_for_response(chip, addr); 814 } 815 udelay(1); 816 } 817 if (printk_ratelimit()) 818 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", 819 azx_readw(chip, IRS), val); 820 return -EIO; 821} 822 823/* receive a response */ 824static unsigned int azx_single_get_response(struct hda_bus *bus, 825 unsigned int addr) 826{ 827 struct azx *chip = bus->private_data; 828 return chip->rirb.res[addr]; 829} 830 831/* 832 * The below are the main callbacks from hda_codec. 833 * 834 * They are just the skeleton to call sub-callbacks according to the 835 * current setting of chip->single_cmd. 836 */ 837 838/* send a command */ 839static int azx_send_cmd(struct hda_bus *bus, unsigned int val) 840{ 841 struct azx *chip = bus->private_data; 842 843 chip->last_cmd[azx_command_addr(val)] = val; 844 if (chip->single_cmd) 845 return azx_single_send_cmd(bus, val); 846 else 847 return azx_corb_send_cmd(bus, val); 848} 849 850/* get a response */ 851static unsigned int azx_get_response(struct hda_bus *bus, 852 unsigned int addr) 853{ 854 struct azx *chip = bus->private_data; 855 if (chip->single_cmd) 856 return azx_single_get_response(bus, addr); 857 else 858 return azx_rirb_get_response(bus, addr); 859} 860 861#ifdef CONFIG_SND_HDA_POWER_SAVE 862static void azx_power_notify(struct hda_bus *bus); 863#endif 864 865/* reset codec link */ 866static int azx_reset(struct azx *chip, int full_reset) 867{ 868 int count; 869 870 if (!full_reset) 871 goto __skip; 872 873 /* clear STATESTS */ 874 azx_writeb(chip, STATESTS, STATESTS_INT_MASK); 875 876 /* reset controller */ 877 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); 878 879 count = 50; 880 while (azx_readb(chip, GCTL) && --count) 881 msleep(1); 882 883 /* delay for >= 100us for codec PLL to settle per spec 884 * Rev 0.9 section 5.5.1 885 */ 886 msleep(1); 887 888 /* Bring controller out of reset */ 889 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); 890 891 count = 50; 892 while (!azx_readb(chip, GCTL) && --count) 893 msleep(1); 894 895 /* Brent Chartrand said to wait >= 540us for codecs to initialize */ 896 msleep(1); 897 898 __skip: 899 /* check to see if controller is ready */ 900 if (!azx_readb(chip, GCTL)) { 901 snd_printd(SFX "azx_reset: controller not ready!\n"); 902 return -EBUSY; 903 } 904 905 /* Accept unsolicited responses */ 906 if (!chip->single_cmd) 907 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | 908 ICH6_GCTL_UNSOL); 909 910 /* detect codecs */ 911 if (!chip->codec_mask) { 912 chip->codec_mask = azx_readw(chip, STATESTS); 913 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask); 914 } 915 916 return 0; 917} 918 919 920/* 921 * Lowlevel interface 922 */ 923 924/* enable interrupts */ 925static void azx_int_enable(struct azx *chip) 926{ 927 /* enable controller CIE and GIE */ 928 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | 929 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); 930} 931 932/* disable interrupts */ 933static void azx_int_disable(struct azx *chip) 934{ 935 int i; 936 937 /* disable interrupts in stream descriptor */ 938 for (i = 0; i < chip->num_streams; i++) { 939 struct azx_dev *azx_dev = &chip->azx_dev[i]; 940 azx_sd_writeb(azx_dev, SD_CTL, 941 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); 942 } 943 944 /* disable SIE for all streams */ 945 azx_writeb(chip, INTCTL, 0); 946 947 /* disable controller CIE and GIE */ 948 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & 949 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); 950} 951 952/* clear interrupts */ 953static void azx_int_clear(struct azx *chip) 954{ 955 int i; 956 957 /* clear stream status */ 958 for (i = 0; i < chip->num_streams; i++) { 959 struct azx_dev *azx_dev = &chip->azx_dev[i]; 960 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 961 } 962 963 /* clear STATESTS */ 964 azx_writeb(chip, STATESTS, STATESTS_INT_MASK); 965 966 /* clear rirb status */ 967 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 968 969 /* clear int status */ 970 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); 971} 972 973/* start a stream */ 974static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) 975{ 976 /* 977 * Before stream start, initialize parameter 978 */ 979 azx_dev->insufficient = 1; 980 981 /* enable SIE */ 982 azx_writel(chip, INTCTL, 983 azx_readl(chip, INTCTL) | (1 << azx_dev->index)); 984 /* set DMA start and interrupt mask */ 985 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | 986 SD_CTL_DMA_START | SD_INT_MASK); 987} 988 989/* stop DMA */ 990static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) 991{ 992 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & 993 ~(SD_CTL_DMA_START | SD_INT_MASK)); 994 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ 995} 996 997/* stop a stream */ 998static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) 999{ 1000 azx_stream_clear(chip, azx_dev); 1001 /* disable SIE */ 1002 azx_writel(chip, INTCTL, 1003 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); 1004} 1005 1006 1007/* 1008 * reset and start the controller registers 1009 */ 1010static void azx_init_chip(struct azx *chip, int full_reset) 1011{ 1012 if (chip->initialized) 1013 return; 1014 1015 /* reset controller */ 1016 azx_reset(chip, full_reset); 1017 1018 /* initialize interrupts */ 1019 azx_int_clear(chip); 1020 azx_int_enable(chip); 1021 1022 /* initialize the codec command I/O */ 1023 if (!chip->single_cmd) 1024 azx_init_cmd_io(chip); 1025 1026 /* program the position buffer */ 1027 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); 1028 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); 1029 1030 chip->initialized = 1; 1031} 1032 1033/* 1034 * initialize the PCI registers 1035 */ 1036/* update bits in a PCI register byte */ 1037static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 1038 unsigned char mask, unsigned char val) 1039{ 1040 unsigned char data; 1041 1042 pci_read_config_byte(pci, reg, &data); 1043 data &= ~mask; 1044 data |= (val & mask); 1045 pci_write_config_byte(pci, reg, data); 1046} 1047 1048static void azx_init_pci(struct azx *chip) 1049{ 1050 unsigned short snoop; 1051 1052 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 1053 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 1054 * Ensuring these bits are 0 clears playback static on some HD Audio 1055 * codecs 1056 */ 1057 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0); 1058 1059 switch (chip->driver_type) { 1060 case AZX_DRIVER_ATI: 1061 /* For ATI SB450 azalia HD audio, we need to enable snoop */ 1062 update_pci_byte(chip->pci, 1063 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 1064 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP); 1065 break; 1066 case AZX_DRIVER_NVIDIA: 1067 /* For NVIDIA HDA, enable snoop */ 1068 update_pci_byte(chip->pci, 1069 NVIDIA_HDA_TRANSREG_ADDR, 1070 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 1071 update_pci_byte(chip->pci, 1072 NVIDIA_HDA_ISTRM_COH, 1073 0x01, NVIDIA_HDA_ENABLE_COHBIT); 1074 update_pci_byte(chip->pci, 1075 NVIDIA_HDA_OSTRM_COH, 1076 0x01, NVIDIA_HDA_ENABLE_COHBIT); 1077 break; 1078 case AZX_DRIVER_SCH: 1079 case AZX_DRIVER_PCH: 1080 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 1081 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) { 1082 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, 1083 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP)); 1084 pci_read_config_word(chip->pci, 1085 INTEL_SCH_HDA_DEVC, &snoop); 1086 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n", 1087 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) 1088 ? "Failed" : "OK"); 1089 } 1090 break; 1091 1092 } 1093} 1094 1095 1096static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 1097 1098/* 1099 * interrupt handler 1100 */ 1101static irqreturn_t azx_interrupt(int irq, void *dev_id) 1102{ 1103 struct azx *chip = dev_id; 1104 struct azx_dev *azx_dev; 1105 u32 status; 1106 u8 sd_status; 1107 int i, ok; 1108 1109 spin_lock(&chip->reg_lock); 1110 1111 status = azx_readl(chip, INTSTS); 1112 if (status == 0) { 1113 spin_unlock(&chip->reg_lock); 1114 return IRQ_NONE; 1115 } 1116 1117 for (i = 0; i < chip->num_streams; i++) { 1118 azx_dev = &chip->azx_dev[i]; 1119 if (status & azx_dev->sd_int_sta_mask) { 1120 sd_status = azx_sd_readb(azx_dev, SD_STS); 1121 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 1122 if (!azx_dev->substream || !azx_dev->running || 1123 !(sd_status & SD_INT_COMPLETE)) 1124 continue; 1125 /* check whether this IRQ is really acceptable */ 1126 ok = azx_position_ok(chip, azx_dev); 1127 if (ok == 1) { 1128 azx_dev->irq_pending = 0; 1129 spin_unlock(&chip->reg_lock); 1130 snd_pcm_period_elapsed(azx_dev->substream); 1131 spin_lock(&chip->reg_lock); 1132 } else if (ok == 0 && chip->bus && chip->bus->workq) { 1133 /* bogus IRQ, process it later */ 1134 azx_dev->irq_pending = 1; 1135 queue_work(chip->bus->workq, 1136 &chip->irq_pending_work); 1137 } 1138 } 1139 } 1140 1141 /* clear rirb int */ 1142 status = azx_readb(chip, RIRBSTS); 1143 if (status & RIRB_INT_MASK) { 1144 if (status & RIRB_INT_RESPONSE) { 1145 if (chip->driver_type == AZX_DRIVER_CTX) 1146 udelay(80); 1147 azx_update_rirb(chip); 1148 } 1149 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 1150 } 1151 1152 spin_unlock(&chip->reg_lock); 1153 1154 return IRQ_HANDLED; 1155} 1156 1157 1158/* 1159 * set up a BDL entry 1160 */ 1161static int setup_bdle(struct snd_pcm_substream *substream, 1162 struct azx_dev *azx_dev, u32 **bdlp, 1163 int ofs, int size, int with_ioc) 1164{ 1165 u32 *bdl = *bdlp; 1166 1167 while (size > 0) { 1168 dma_addr_t addr; 1169 int chunk; 1170 1171 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) 1172 return -EINVAL; 1173 1174 addr = snd_pcm_sgbuf_get_addr(substream, ofs); 1175 /* program the address field of the BDL entry */ 1176 bdl[0] = cpu_to_le32((u32)addr); 1177 bdl[1] = cpu_to_le32(upper_32_bits(addr)); 1178 /* program the size field of the BDL entry */ 1179 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size); 1180 bdl[2] = cpu_to_le32(chunk); 1181 /* program the IOC to enable interrupt 1182 * only when the whole fragment is processed 1183 */ 1184 size -= chunk; 1185 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); 1186 bdl += 4; 1187 azx_dev->frags++; 1188 ofs += chunk; 1189 } 1190 *bdlp = bdl; 1191 return ofs; 1192} 1193 1194/* 1195 * set up BDL entries 1196 */ 1197static int azx_setup_periods(struct azx *chip, 1198 struct snd_pcm_substream *substream, 1199 struct azx_dev *azx_dev) 1200{ 1201 u32 *bdl; 1202 int i, ofs, periods, period_bytes; 1203 int pos_adj; 1204 1205 /* reset BDL address */ 1206 azx_sd_writel(azx_dev, SD_BDLPL, 0); 1207 azx_sd_writel(azx_dev, SD_BDLPU, 0); 1208 1209 period_bytes = azx_dev->period_bytes; 1210 periods = azx_dev->bufsize / period_bytes; 1211 1212 /* program the initial BDL entries */ 1213 bdl = (u32 *)azx_dev->bdl.area; 1214 ofs = 0; 1215 azx_dev->frags = 0; 1216 pos_adj = bdl_pos_adj[chip->dev_index]; 1217 if (pos_adj > 0) { 1218 struct snd_pcm_runtime *runtime = substream->runtime; 1219 int pos_align = pos_adj; 1220 pos_adj = (pos_adj * runtime->rate + 47999) / 48000; 1221 if (!pos_adj) 1222 pos_adj = pos_align; 1223 else 1224 pos_adj = ((pos_adj + pos_align - 1) / pos_align) * 1225 pos_align; 1226 pos_adj = frames_to_bytes(runtime, pos_adj); 1227 if (pos_adj >= period_bytes) { 1228 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n", 1229 bdl_pos_adj[chip->dev_index]); 1230 pos_adj = 0; 1231 } else { 1232 ofs = setup_bdle(substream, azx_dev, 1233 &bdl, ofs, pos_adj, 1); 1234 if (ofs < 0) 1235 goto error; 1236 } 1237 } else 1238 pos_adj = 0; 1239 for (i = 0; i < periods; i++) { 1240 if (i == periods - 1 && pos_adj) 1241 ofs = setup_bdle(substream, azx_dev, &bdl, ofs, 1242 period_bytes - pos_adj, 0); 1243 else 1244 ofs = setup_bdle(substream, azx_dev, &bdl, ofs, 1245 period_bytes, 1); 1246 if (ofs < 0) 1247 goto error; 1248 } 1249 return 0; 1250 1251 error: 1252 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n", 1253 azx_dev->bufsize, period_bytes); 1254 return -EINVAL; 1255} 1256 1257/* reset stream */ 1258static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) 1259{ 1260 unsigned char val; 1261 int timeout; 1262 1263 azx_stream_clear(chip, azx_dev); 1264 1265 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | 1266 SD_CTL_STREAM_RESET); 1267 udelay(3); 1268 timeout = 300; 1269 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 1270 --timeout) 1271 ; 1272 val &= ~SD_CTL_STREAM_RESET; 1273 azx_sd_writeb(azx_dev, SD_CTL, val); 1274 udelay(3); 1275 1276 timeout = 300; 1277 /* waiting for hardware to report that the stream is out of reset */ 1278 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 1279 --timeout) 1280 ; 1281 1282 /* reset first position - may not be synced with hw at this time */ 1283 *azx_dev->posbuf = 0; 1284} 1285 1286/* 1287 * set up the SD for streaming 1288 */ 1289static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) 1290{ 1291 /* make sure the run bit is zero for SD */ 1292 azx_stream_clear(chip, azx_dev); 1293 /* program the stream_tag */ 1294 azx_sd_writel(azx_dev, SD_CTL, 1295 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)| 1296 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT)); 1297 1298 /* program the length of samples in cyclic buffer */ 1299 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); 1300 1301 /* program the stream format */ 1302 /* this value needs to be the same as the one programmed */ 1303 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); 1304 1305 /* program the stream LVI (last valid index) of the BDL */ 1306 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); 1307 1308 /* program the BDL address */ 1309 /* lower BDL address */ 1310 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); 1311 /* upper BDL address */ 1312 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr)); 1313 1314 /* enable the position buffer */ 1315 if (chip->position_fix[0] == POS_FIX_POSBUF || 1316 chip->position_fix[0] == POS_FIX_AUTO || 1317 chip->position_fix[1] == POS_FIX_POSBUF || 1318 chip->position_fix[1] == POS_FIX_AUTO || 1319 chip->via_dmapos_patch) { 1320 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) 1321 azx_writel(chip, DPLBASE, 1322 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); 1323 } 1324 1325 /* set the interrupt enable bits in the descriptor control register */ 1326 azx_sd_writel(azx_dev, SD_CTL, 1327 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); 1328 1329 return 0; 1330} 1331 1332/* 1333 * Probe the given codec address 1334 */ 1335static int probe_codec(struct azx *chip, int addr) 1336{ 1337 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 1338 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 1339 unsigned int res; 1340 1341 mutex_lock(&chip->bus->cmd_mutex); 1342 chip->probing = 1; 1343 azx_send_cmd(chip->bus, cmd); 1344 res = azx_get_response(chip->bus, addr); 1345 chip->probing = 0; 1346 mutex_unlock(&chip->bus->cmd_mutex); 1347 if (res == -1) 1348 return -EIO; 1349 snd_printdd(SFX "codec #%d probed OK\n", addr); 1350 return 0; 1351} 1352 1353static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, 1354 struct hda_pcm *cpcm); 1355static void azx_stop_chip(struct azx *chip); 1356 1357static void azx_bus_reset(struct hda_bus *bus) 1358{ 1359 struct azx *chip = bus->private_data; 1360 1361 bus->in_reset = 1; 1362 azx_stop_chip(chip); 1363 azx_init_chip(chip, 1); 1364#ifdef CONFIG_PM 1365 if (chip->initialized) { 1366 int i; 1367 1368 for (i = 0; i < HDA_MAX_PCMS; i++) 1369 snd_pcm_suspend_all(chip->pcm[i]); 1370 snd_hda_suspend(chip->bus); 1371 snd_hda_resume(chip->bus); 1372 } 1373#endif 1374 bus->in_reset = 0; 1375} 1376 1377/* 1378 * Codec initialization 1379 */ 1380 1381/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 1382static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = { 1383 [AZX_DRIVER_NVIDIA] = 8, 1384 [AZX_DRIVER_TERA] = 1, 1385}; 1386 1387static int __devinit azx_codec_create(struct azx *chip, const char *model) 1388{ 1389 struct hda_bus_template bus_temp; 1390 int c, codecs, err; 1391 int max_slots; 1392 1393 memset(&bus_temp, 0, sizeof(bus_temp)); 1394 bus_temp.private_data = chip; 1395 bus_temp.modelname = model; 1396 bus_temp.pci = chip->pci; 1397 bus_temp.ops.command = azx_send_cmd; 1398 bus_temp.ops.get_response = azx_get_response; 1399 bus_temp.ops.attach_pcm = azx_attach_pcm_stream; 1400 bus_temp.ops.bus_reset = azx_bus_reset; 1401#ifdef CONFIG_SND_HDA_POWER_SAVE 1402 bus_temp.power_save = &power_save; 1403 bus_temp.ops.pm_notify = azx_power_notify; 1404#endif 1405 1406 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus); 1407 if (err < 0) 1408 return err; 1409 1410 if (chip->driver_type == AZX_DRIVER_NVIDIA) 1411 chip->bus->needs_damn_long_delay = 1; 1412 1413 codecs = 0; 1414 max_slots = azx_max_codecs[chip->driver_type]; 1415 if (!max_slots) 1416 max_slots = AZX_DEFAULT_CODECS; 1417 1418 /* First try to probe all given codec slots */ 1419 for (c = 0; c < max_slots; c++) { 1420 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { 1421 if (probe_codec(chip, c) < 0) { 1422 /* Some BIOSen give you wrong codec addresses 1423 * that don't exist 1424 */ 1425 snd_printk(KERN_WARNING SFX 1426 "Codec #%d probe error; " 1427 "disabling it...\n", c); 1428 chip->codec_mask &= ~(1 << c); 1429 /* More badly, accessing to a non-existing 1430 * codec often screws up the controller chip, 1431 * and disturbs the further communications. 1432 * Thus if an error occurs during probing, 1433 * better to reset the controller chip to 1434 * get back to the sanity state. 1435 */ 1436 azx_stop_chip(chip); 1437 azx_init_chip(chip, 1); 1438 } 1439 } 1440 } 1441 1442 /* Then create codec instances */ 1443 for (c = 0; c < max_slots; c++) { 1444 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { 1445 struct hda_codec *codec; 1446 err = snd_hda_codec_new(chip->bus, c, &codec); 1447 if (err < 0) 1448 continue; 1449 codec->beep_mode = chip->beep_mode; 1450 codecs++; 1451 } 1452 } 1453 if (!codecs) { 1454 snd_printk(KERN_ERR SFX "no codecs initialized\n"); 1455 return -ENXIO; 1456 } 1457 return 0; 1458} 1459 1460/* configure each codec instance */ 1461static int __devinit azx_codec_configure(struct azx *chip) 1462{ 1463 struct hda_codec *codec; 1464 list_for_each_entry(codec, &chip->bus->codec_list, list) { 1465 snd_hda_codec_configure(codec); 1466 } 1467 return 0; 1468} 1469 1470 1471/* 1472 * PCM support 1473 */ 1474 1475/* assign a stream for the PCM */ 1476static inline struct azx_dev * 1477azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) 1478{ 1479 int dev, i, nums; 1480 struct azx_dev *res = NULL; 1481 1482 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1483 dev = chip->playback_index_offset; 1484 nums = chip->playback_streams; 1485 } else { 1486 dev = chip->capture_index_offset; 1487 nums = chip->capture_streams; 1488 } 1489 for (i = 0; i < nums; i++, dev++) 1490 if (!chip->azx_dev[dev].opened) { 1491 res = &chip->azx_dev[dev]; 1492 if (res->device == substream->pcm->device) 1493 break; 1494 } 1495 if (res) { 1496 res->opened = 1; 1497 res->device = substream->pcm->device; 1498 } 1499 return res; 1500} 1501 1502/* release the assigned stream */ 1503static inline void azx_release_device(struct azx_dev *azx_dev) 1504{ 1505 azx_dev->opened = 0; 1506} 1507 1508static struct snd_pcm_hardware azx_pcm_hw = { 1509 .info = (SNDRV_PCM_INFO_MMAP | 1510 SNDRV_PCM_INFO_INTERLEAVED | 1511 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1512 SNDRV_PCM_INFO_MMAP_VALID | 1513 /* No full-resume yet implemented */ 1514 /* SNDRV_PCM_INFO_RESUME |*/ 1515 SNDRV_PCM_INFO_PAUSE | 1516 SNDRV_PCM_INFO_SYNC_START), 1517 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1518 .rates = SNDRV_PCM_RATE_48000, 1519 .rate_min = 48000, 1520 .rate_max = 48000, 1521 .channels_min = 2, 1522 .channels_max = 2, 1523 .buffer_bytes_max = AZX_MAX_BUF_SIZE, 1524 .period_bytes_min = 128, 1525 .period_bytes_max = AZX_MAX_BUF_SIZE / 2, 1526 .periods_min = 2, 1527 .periods_max = AZX_MAX_FRAG, 1528 .fifo_size = 0, 1529}; 1530 1531struct azx_pcm { 1532 struct azx *chip; 1533 struct hda_codec *codec; 1534 struct hda_pcm_stream *hinfo[2]; 1535}; 1536 1537static int azx_pcm_open(struct snd_pcm_substream *substream) 1538{ 1539 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1540 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1541 struct azx *chip = apcm->chip; 1542 struct azx_dev *azx_dev; 1543 struct snd_pcm_runtime *runtime = substream->runtime; 1544 unsigned long flags; 1545 int err; 1546 1547 mutex_lock(&chip->open_mutex); 1548 azx_dev = azx_assign_device(chip, substream); 1549 if (azx_dev == NULL) { 1550 mutex_unlock(&chip->open_mutex); 1551 return -EBUSY; 1552 } 1553 runtime->hw = azx_pcm_hw; 1554 runtime->hw.channels_min = hinfo->channels_min; 1555 runtime->hw.channels_max = hinfo->channels_max; 1556 runtime->hw.formats = hinfo->formats; 1557 runtime->hw.rates = hinfo->rates; 1558 snd_pcm_limit_hw_rates(runtime); 1559 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 1560 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1561 128); 1562 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1563 128); 1564 snd_hda_power_up(apcm->codec); 1565 err = hinfo->ops.open(hinfo, apcm->codec, substream); 1566 if (err < 0) { 1567 azx_release_device(azx_dev); 1568 snd_hda_power_down(apcm->codec); 1569 mutex_unlock(&chip->open_mutex); 1570 return err; 1571 } 1572 snd_pcm_limit_hw_rates(runtime); 1573 /* sanity check */ 1574 if (snd_BUG_ON(!runtime->hw.channels_min) || 1575 snd_BUG_ON(!runtime->hw.channels_max) || 1576 snd_BUG_ON(!runtime->hw.formats) || 1577 snd_BUG_ON(!runtime->hw.rates)) { 1578 azx_release_device(azx_dev); 1579 hinfo->ops.close(hinfo, apcm->codec, substream); 1580 snd_hda_power_down(apcm->codec); 1581 mutex_unlock(&chip->open_mutex); 1582 return -EINVAL; 1583 } 1584 spin_lock_irqsave(&chip->reg_lock, flags); 1585 azx_dev->substream = substream; 1586 azx_dev->running = 0; 1587 spin_unlock_irqrestore(&chip->reg_lock, flags); 1588 1589 runtime->private_data = azx_dev; 1590 snd_pcm_set_sync(substream); 1591 mutex_unlock(&chip->open_mutex); 1592 return 0; 1593} 1594 1595static int azx_pcm_close(struct snd_pcm_substream *substream) 1596{ 1597 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1598 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1599 struct azx *chip = apcm->chip; 1600 struct azx_dev *azx_dev = get_azx_dev(substream); 1601 unsigned long flags; 1602 1603 mutex_lock(&chip->open_mutex); 1604 spin_lock_irqsave(&chip->reg_lock, flags); 1605 azx_dev->substream = NULL; 1606 azx_dev->running = 0; 1607 spin_unlock_irqrestore(&chip->reg_lock, flags); 1608 azx_release_device(azx_dev); 1609 hinfo->ops.close(hinfo, apcm->codec, substream); 1610 snd_hda_power_down(apcm->codec); 1611 mutex_unlock(&chip->open_mutex); 1612 return 0; 1613} 1614 1615static int azx_pcm_hw_params(struct snd_pcm_substream *substream, 1616 struct snd_pcm_hw_params *hw_params) 1617{ 1618 struct azx_dev *azx_dev = get_azx_dev(substream); 1619 1620 azx_dev->bufsize = 0; 1621 azx_dev->period_bytes = 0; 1622 azx_dev->format_val = 0; 1623 return snd_pcm_lib_malloc_pages(substream, 1624 params_buffer_bytes(hw_params)); 1625} 1626 1627static int azx_pcm_hw_free(struct snd_pcm_substream *substream) 1628{ 1629 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1630 struct azx_dev *azx_dev = get_azx_dev(substream); 1631 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1632 1633 /* reset BDL address */ 1634 azx_sd_writel(azx_dev, SD_BDLPL, 0); 1635 azx_sd_writel(azx_dev, SD_BDLPU, 0); 1636 azx_sd_writel(azx_dev, SD_CTL, 0); 1637 azx_dev->bufsize = 0; 1638 azx_dev->period_bytes = 0; 1639 azx_dev->format_val = 0; 1640 1641 snd_hda_codec_cleanup(apcm->codec, hinfo, substream); 1642 1643 return snd_pcm_lib_free_pages(substream); 1644} 1645 1646static int azx_pcm_prepare(struct snd_pcm_substream *substream) 1647{ 1648 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1649 struct azx *chip = apcm->chip; 1650 struct azx_dev *azx_dev = get_azx_dev(substream); 1651 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1652 struct snd_pcm_runtime *runtime = substream->runtime; 1653 unsigned int bufsize, period_bytes, format_val, stream_tag; 1654 int err; 1655 1656 azx_stream_reset(chip, azx_dev); 1657 format_val = snd_hda_calc_stream_format(runtime->rate, 1658 runtime->channels, 1659 runtime->format, 1660 hinfo->maxbps, 1661 apcm->codec->spdif_ctls); 1662 if (!format_val) { 1663 snd_printk(KERN_ERR SFX 1664 "invalid format_val, rate=%d, ch=%d, format=%d\n", 1665 runtime->rate, runtime->channels, runtime->format); 1666 return -EINVAL; 1667 } 1668 1669 bufsize = snd_pcm_lib_buffer_bytes(substream); 1670 period_bytes = snd_pcm_lib_period_bytes(substream); 1671 1672 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", 1673 bufsize, format_val); 1674 1675 if (bufsize != azx_dev->bufsize || 1676 period_bytes != azx_dev->period_bytes || 1677 format_val != azx_dev->format_val) { 1678 azx_dev->bufsize = bufsize; 1679 azx_dev->period_bytes = period_bytes; 1680 azx_dev->format_val = format_val; 1681 err = azx_setup_periods(chip, substream, azx_dev); 1682 if (err < 0) 1683 return err; 1684 } 1685 1686 /* wallclk has 24Mhz clock source */ 1687 azx_dev->period_wallclk = (((runtime->period_size * 24000) / 1688 runtime->rate) * 1000); 1689 azx_setup_controller(chip, azx_dev); 1690 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1691 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; 1692 else 1693 azx_dev->fifo_size = 0; 1694 1695 stream_tag = azx_dev->stream_tag; 1696 /* CA-IBG chips need the playback stream starting from 1 */ 1697 if (chip->driver_type == AZX_DRIVER_CTX && 1698 stream_tag > chip->capture_streams) 1699 stream_tag -= chip->capture_streams; 1700 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, 1701 azx_dev->format_val, substream); 1702} 1703 1704static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1705{ 1706 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1707 struct azx *chip = apcm->chip; 1708 struct azx_dev *azx_dev; 1709 struct snd_pcm_substream *s; 1710 int rstart = 0, start, nsync = 0, sbits = 0; 1711 int nwait, timeout; 1712 1713 switch (cmd) { 1714 case SNDRV_PCM_TRIGGER_START: 1715 rstart = 1; 1716 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1717 case SNDRV_PCM_TRIGGER_RESUME: 1718 start = 1; 1719 break; 1720 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1721 case SNDRV_PCM_TRIGGER_SUSPEND: 1722 case SNDRV_PCM_TRIGGER_STOP: 1723 start = 0; 1724 break; 1725 default: 1726 return -EINVAL; 1727 } 1728 1729 snd_pcm_group_for_each_entry(s, substream) { 1730 if (s->pcm->card != substream->pcm->card) 1731 continue; 1732 azx_dev = get_azx_dev(s); 1733 sbits |= 1 << azx_dev->index; 1734 nsync++; 1735 snd_pcm_trigger_done(s, substream); 1736 } 1737 1738 spin_lock(&chip->reg_lock); 1739 if (nsync > 1) { 1740 /* first, set SYNC bits of corresponding streams */ 1741 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits); 1742 } 1743 snd_pcm_group_for_each_entry(s, substream) { 1744 if (s->pcm->card != substream->pcm->card) 1745 continue; 1746 azx_dev = get_azx_dev(s); 1747 if (start) { 1748 azx_dev->start_wallclk = azx_readl(chip, WALLCLK); 1749 if (!rstart) 1750 azx_dev->start_wallclk -= 1751 azx_dev->period_wallclk; 1752 azx_stream_start(chip, azx_dev); 1753 } else { 1754 azx_stream_stop(chip, azx_dev); 1755 } 1756 azx_dev->running = start; 1757 } 1758 spin_unlock(&chip->reg_lock); 1759 if (start) { 1760 if (nsync == 1) 1761 return 0; 1762 /* wait until all FIFOs get ready */ 1763 for (timeout = 5000; timeout; timeout--) { 1764 nwait = 0; 1765 snd_pcm_group_for_each_entry(s, substream) { 1766 if (s->pcm->card != substream->pcm->card) 1767 continue; 1768 azx_dev = get_azx_dev(s); 1769 if (!(azx_sd_readb(azx_dev, SD_STS) & 1770 SD_STS_FIFO_READY)) 1771 nwait++; 1772 } 1773 if (!nwait) 1774 break; 1775 cpu_relax(); 1776 } 1777 } else { 1778 /* wait until all RUN bits are cleared */ 1779 for (timeout = 5000; timeout; timeout--) { 1780 nwait = 0; 1781 snd_pcm_group_for_each_entry(s, substream) { 1782 if (s->pcm->card != substream->pcm->card) 1783 continue; 1784 azx_dev = get_azx_dev(s); 1785 if (azx_sd_readb(azx_dev, SD_CTL) & 1786 SD_CTL_DMA_START) 1787 nwait++; 1788 } 1789 if (!nwait) 1790 break; 1791 cpu_relax(); 1792 } 1793 } 1794 if (nsync > 1) { 1795 spin_lock(&chip->reg_lock); 1796 /* reset SYNC bits */ 1797 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits); 1798 spin_unlock(&chip->reg_lock); 1799 } 1800 return 0; 1801} 1802 1803/* get the current DMA position with correction on VIA chips */ 1804static unsigned int azx_via_get_position(struct azx *chip, 1805 struct azx_dev *azx_dev) 1806{ 1807 unsigned int link_pos, mini_pos, bound_pos; 1808 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 1809 unsigned int fifo_size; 1810 1811 link_pos = azx_sd_readl(azx_dev, SD_LPIB); 1812 if (azx_dev->index >= 4) { 1813 /* Playback, no problem using link position */ 1814 return link_pos; 1815 } 1816 1817 /* Capture */ 1818 /* For new chipset, 1819 * use mod to get the DMA position just like old chipset 1820 */ 1821 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); 1822 mod_dma_pos %= azx_dev->period_bytes; 1823 1824 /* azx_dev->fifo_size can't get FIFO size of in stream. 1825 * Get from base address + offset. 1826 */ 1827 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 1828 1829 if (azx_dev->insufficient) { 1830 /* Link position never gather than FIFO size */ 1831 if (link_pos <= fifo_size) 1832 return 0; 1833 1834 azx_dev->insufficient = 0; 1835 } 1836 1837 if (link_pos <= fifo_size) 1838 mini_pos = azx_dev->bufsize + link_pos - fifo_size; 1839 else 1840 mini_pos = link_pos - fifo_size; 1841 1842 /* Find nearest previous boudary */ 1843 mod_mini_pos = mini_pos % azx_dev->period_bytes; 1844 mod_link_pos = link_pos % azx_dev->period_bytes; 1845 if (mod_link_pos >= fifo_size) 1846 bound_pos = link_pos - mod_link_pos; 1847 else if (mod_dma_pos >= mod_mini_pos) 1848 bound_pos = mini_pos - mod_mini_pos; 1849 else { 1850 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; 1851 if (bound_pos >= azx_dev->bufsize) 1852 bound_pos = 0; 1853 } 1854 1855 /* Calculate real DMA position we want */ 1856 return bound_pos + mod_dma_pos; 1857} 1858 1859static unsigned int azx_get_position(struct azx *chip, 1860 struct azx_dev *azx_dev) 1861{ 1862 unsigned int pos; 1863 1864 if (chip->via_dmapos_patch) 1865 pos = azx_via_get_position(chip, azx_dev); 1866 else { 1867 int stream = azx_dev->substream->stream; 1868 if (chip->position_fix[stream] == POS_FIX_POSBUF || 1869 chip->position_fix[stream] == POS_FIX_AUTO) { 1870 /* use the position buffer */ 1871 pos = le32_to_cpu(*azx_dev->posbuf); 1872 } else { 1873 /* read LPIB */ 1874 pos = azx_sd_readl(azx_dev, SD_LPIB); 1875 } 1876 } 1877 if (pos >= azx_dev->bufsize) 1878 pos = 0; 1879 return pos; 1880} 1881 1882static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) 1883{ 1884 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1885 struct azx *chip = apcm->chip; 1886 struct azx_dev *azx_dev = get_azx_dev(substream); 1887 return bytes_to_frames(substream->runtime, 1888 azx_get_position(chip, azx_dev)); 1889} 1890 1891/* 1892 * Check whether the current DMA position is acceptable for updating 1893 * periods. Returns non-zero if it's OK. 1894 * 1895 * Many HD-audio controllers appear pretty inaccurate about 1896 * the update-IRQ timing. The IRQ is issued before actually the 1897 * data is processed. So, we need to process it afterwords in a 1898 * workqueue. 1899 */ 1900static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 1901{ 1902 u32 wallclk; 1903 unsigned int pos; 1904 int stream; 1905 1906 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; 1907 if (wallclk < (azx_dev->period_wallclk * 2) / 3) 1908 return -1; /* bogus (too early) interrupt */ 1909 1910 stream = azx_dev->substream->stream; 1911 pos = azx_get_position(chip, azx_dev); 1912 if (chip->position_fix[stream] == POS_FIX_AUTO) { 1913 if (!pos) { 1914 printk(KERN_WARNING 1915 "hda-intel: Invalid position buffer, " 1916 "using LPIB read method instead.\n"); 1917 chip->position_fix[stream] = POS_FIX_LPIB; 1918 pos = azx_get_position(chip, azx_dev); 1919 } else 1920 chip->position_fix[stream] = POS_FIX_POSBUF; 1921 } 1922 1923 if (WARN_ONCE(!azx_dev->period_bytes, 1924 "hda-intel: zero azx_dev->period_bytes")) 1925 return -1; /* this shouldn't happen! */ 1926 if (wallclk < (azx_dev->period_wallclk * 5) / 4 && 1927 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) 1928 /* NG - it's below the first next period boundary */ 1929 return bdl_pos_adj[chip->dev_index] ? 0 : -1; 1930 azx_dev->start_wallclk += wallclk; 1931 return 1; /* OK, it's fine */ 1932} 1933 1934/* 1935 * The work for pending PCM period updates. 1936 */ 1937static void azx_irq_pending_work(struct work_struct *work) 1938{ 1939 struct azx *chip = container_of(work, struct azx, irq_pending_work); 1940 int i, pending, ok; 1941 1942 if (!chip->irq_pending_warned) { 1943 printk(KERN_WARNING 1944 "hda-intel: IRQ timing workaround is activated " 1945 "for card #%d. Suggest a bigger bdl_pos_adj.\n", 1946 chip->card->number); 1947 chip->irq_pending_warned = 1; 1948 } 1949 1950 for (;;) { 1951 pending = 0; 1952 spin_lock_irq(&chip->reg_lock); 1953 for (i = 0; i < chip->num_streams; i++) { 1954 struct azx_dev *azx_dev = &chip->azx_dev[i]; 1955 if (!azx_dev->irq_pending || 1956 !azx_dev->substream || 1957 !azx_dev->running) 1958 continue; 1959 ok = azx_position_ok(chip, azx_dev); 1960 if (ok > 0) { 1961 azx_dev->irq_pending = 0; 1962 spin_unlock(&chip->reg_lock); 1963 snd_pcm_period_elapsed(azx_dev->substream); 1964 spin_lock(&chip->reg_lock); 1965 } else if (ok < 0) { 1966 pending = 0; /* too early */ 1967 } else 1968 pending++; 1969 } 1970 spin_unlock_irq(&chip->reg_lock); 1971 if (!pending) 1972 return; 1973 msleep(1); 1974 } 1975} 1976 1977/* clear irq_pending flags and assure no on-going workq */ 1978static void azx_clear_irq_pending(struct azx *chip) 1979{ 1980 int i; 1981 1982 spin_lock_irq(&chip->reg_lock); 1983 for (i = 0; i < chip->num_streams; i++) 1984 chip->azx_dev[i].irq_pending = 0; 1985 spin_unlock_irq(&chip->reg_lock); 1986} 1987 1988static struct snd_pcm_ops azx_pcm_ops = { 1989 .open = azx_pcm_open, 1990 .close = azx_pcm_close, 1991 .ioctl = snd_pcm_lib_ioctl, 1992 .hw_params = azx_pcm_hw_params, 1993 .hw_free = azx_pcm_hw_free, 1994 .prepare = azx_pcm_prepare, 1995 .trigger = azx_pcm_trigger, 1996 .pointer = azx_pcm_pointer, 1997 .page = snd_pcm_sgbuf_ops_page, 1998}; 1999 2000static void azx_pcm_free(struct snd_pcm *pcm) 2001{ 2002 struct azx_pcm *apcm = pcm->private_data; 2003 if (apcm) { 2004 apcm->chip->pcm[pcm->device] = NULL; 2005 kfree(apcm); 2006 } 2007} 2008 2009static int 2010azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, 2011 struct hda_pcm *cpcm) 2012{ 2013 struct azx *chip = bus->private_data; 2014 struct snd_pcm *pcm; 2015 struct azx_pcm *apcm; 2016 int pcm_dev = cpcm->device; 2017 int s, err; 2018 2019 if (pcm_dev >= HDA_MAX_PCMS) { 2020 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n", 2021 pcm_dev); 2022 return -EINVAL; 2023 } 2024 if (chip->pcm[pcm_dev]) { 2025 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev); 2026 return -EBUSY; 2027 } 2028 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, 2029 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, 2030 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, 2031 &pcm); 2032 if (err < 0) 2033 return err; 2034 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); 2035 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); 2036 if (apcm == NULL) 2037 return -ENOMEM; 2038 apcm->chip = chip; 2039 apcm->codec = codec; 2040 pcm->private_data = apcm; 2041 pcm->private_free = azx_pcm_free; 2042 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) 2043 pcm->dev_class = SNDRV_PCM_CLASS_MODEM; 2044 chip->pcm[pcm_dev] = pcm; 2045 cpcm->pcm = pcm; 2046 for (s = 0; s < 2; s++) { 2047 apcm->hinfo[s] = &cpcm->stream[s]; 2048 if (cpcm->stream[s].substreams) 2049 snd_pcm_set_ops(pcm, s, &azx_pcm_ops); 2050 } 2051 /* buffer pre-allocation */ 2052 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, 2053 snd_dma_pci_data(chip->pci), 2054 1024 * 64, 32 * 1024 * 1024); 2055 return 0; 2056} 2057 2058/* 2059 * mixer creation - all stuff is implemented in hda module 2060 */ 2061static int __devinit azx_mixer_create(struct azx *chip) 2062{ 2063 return snd_hda_build_controls(chip->bus); 2064} 2065 2066 2067/* 2068 * initialize SD streams 2069 */ 2070static int __devinit azx_init_stream(struct azx *chip) 2071{ 2072 int i; 2073 2074 /* initialize each stream (aka device) 2075 * assign the starting bdl address to each stream (device) 2076 * and initialize 2077 */ 2078 for (i = 0; i < chip->num_streams; i++) { 2079 struct azx_dev *azx_dev = &chip->azx_dev[i]; 2080 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); 2081 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 2082 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); 2083 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ 2084 azx_dev->sd_int_sta_mask = 1 << i; 2085 /* stream tag: must be non-zero and unique */ 2086 azx_dev->index = i; 2087 azx_dev->stream_tag = i + 1; 2088 } 2089 2090 return 0; 2091} 2092 2093static int azx_acquire_irq(struct azx *chip, int do_disconnect) 2094{ 2095 if (request_irq(chip->pci->irq, azx_interrupt, 2096 chip->msi ? 0 : IRQF_SHARED, 2097 "hda_intel", chip)) { 2098 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, " 2099 "disabling device\n", chip->pci->irq); 2100 if (do_disconnect) 2101 snd_card_disconnect(chip->card); 2102 return -1; 2103 } 2104 chip->irq = chip->pci->irq; 2105 pci_intx(chip->pci, !chip->msi); 2106 return 0; 2107} 2108 2109 2110static void azx_stop_chip(struct azx *chip) 2111{ 2112 if (!chip->initialized) 2113 return; 2114 2115 /* disable interrupts */ 2116 azx_int_disable(chip); 2117 azx_int_clear(chip); 2118 2119 /* disable CORB/RIRB */ 2120 azx_free_cmd_io(chip); 2121 2122 /* disable position buffer */ 2123 azx_writel(chip, DPLBASE, 0); 2124 azx_writel(chip, DPUBASE, 0); 2125 2126 chip->initialized = 0; 2127} 2128 2129#ifdef CONFIG_SND_HDA_POWER_SAVE 2130/* power-up/down the controller */ 2131static void azx_power_notify(struct hda_bus *bus) 2132{ 2133 struct azx *chip = bus->private_data; 2134 struct hda_codec *c; 2135 int power_on = 0; 2136 2137 list_for_each_entry(c, &bus->codec_list, list) { 2138 if (c->power_on) { 2139 power_on = 1; 2140 break; 2141 } 2142 } 2143 if (power_on) 2144 azx_init_chip(chip, 1); 2145 else if (chip->running && power_save_controller && 2146 !bus->power_keep_link_on) 2147 azx_stop_chip(chip); 2148} 2149#endif /* CONFIG_SND_HDA_POWER_SAVE */ 2150 2151#ifdef CONFIG_PM 2152/* 2153 * power management 2154 */ 2155 2156static int snd_hda_codecs_inuse(struct hda_bus *bus) 2157{ 2158 struct hda_codec *codec; 2159 2160 list_for_each_entry(codec, &bus->codec_list, list) { 2161 if (snd_hda_codec_needs_resume(codec)) 2162 return 1; 2163 } 2164 return 0; 2165} 2166 2167static int azx_suspend(struct pci_dev *pci, pm_message_t state) 2168{ 2169 struct snd_card *card = pci_get_drvdata(pci); 2170 struct azx *chip = card->private_data; 2171 int i; 2172 2173 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2174 azx_clear_irq_pending(chip); 2175 for (i = 0; i < HDA_MAX_PCMS; i++) 2176 snd_pcm_suspend_all(chip->pcm[i]); 2177 if (chip->initialized) 2178 snd_hda_suspend(chip->bus); 2179 azx_stop_chip(chip); 2180 if (chip->irq >= 0) { 2181 free_irq(chip->irq, chip); 2182 chip->irq = -1; 2183 } 2184 if (chip->msi) 2185 pci_disable_msi(chip->pci); 2186 pci_disable_device(pci); 2187 pci_save_state(pci); 2188 pci_set_power_state(pci, pci_choose_state(pci, state)); 2189 return 0; 2190} 2191 2192static int azx_resume(struct pci_dev *pci) 2193{ 2194 struct snd_card *card = pci_get_drvdata(pci); 2195 struct azx *chip = card->private_data; 2196 2197 pci_set_power_state(pci, PCI_D0); 2198 pci_restore_state(pci); 2199 if (pci_enable_device(pci) < 0) { 2200 printk(KERN_ERR "hda-intel: pci_enable_device failed, " 2201 "disabling device\n"); 2202 snd_card_disconnect(card); 2203 return -EIO; 2204 } 2205 pci_set_master(pci); 2206 if (chip->msi) 2207 if (pci_enable_msi(pci) < 0) 2208 chip->msi = 0; 2209 if (azx_acquire_irq(chip, 1) < 0) 2210 return -EIO; 2211 azx_init_pci(chip); 2212 2213 if (snd_hda_codecs_inuse(chip->bus)) 2214 azx_init_chip(chip, 1); 2215 2216 snd_hda_resume(chip->bus); 2217 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2218 return 0; 2219} 2220#endif /* CONFIG_PM */ 2221 2222 2223/* 2224 * reboot notifier for hang-up problem at power-down 2225 */ 2226static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf) 2227{ 2228 struct azx *chip = container_of(nb, struct azx, reboot_notifier); 2229 snd_hda_bus_reboot_notify(chip->bus); 2230 azx_stop_chip(chip); 2231 return NOTIFY_OK; 2232} 2233 2234static void azx_notifier_register(struct azx *chip) 2235{ 2236 chip->reboot_notifier.notifier_call = azx_halt; 2237 register_reboot_notifier(&chip->reboot_notifier); 2238} 2239 2240static void azx_notifier_unregister(struct azx *chip) 2241{ 2242 if (chip->reboot_notifier.notifier_call) 2243 unregister_reboot_notifier(&chip->reboot_notifier); 2244} 2245 2246/* 2247 * destructor 2248 */ 2249static int azx_free(struct azx *chip) 2250{ 2251 int i; 2252 2253 azx_notifier_unregister(chip); 2254 2255 if (chip->initialized) { 2256 azx_clear_irq_pending(chip); 2257 for (i = 0; i < chip->num_streams; i++) 2258 azx_stream_stop(chip, &chip->azx_dev[i]); 2259 azx_stop_chip(chip); 2260 } 2261 2262 if (chip->irq >= 0) 2263 free_irq(chip->irq, (void*)chip); 2264 if (chip->msi) 2265 pci_disable_msi(chip->pci); 2266 if (chip->remap_addr) 2267 iounmap(chip->remap_addr); 2268 2269 if (chip->azx_dev) { 2270 for (i = 0; i < chip->num_streams; i++) 2271 if (chip->azx_dev[i].bdl.area) 2272 snd_dma_free_pages(&chip->azx_dev[i].bdl); 2273 } 2274 if (chip->rb.area) 2275 snd_dma_free_pages(&chip->rb); 2276 if (chip->posbuf.area) 2277 snd_dma_free_pages(&chip->posbuf); 2278 pci_release_regions(chip->pci); 2279 pci_disable_device(chip->pci); 2280 kfree(chip->azx_dev); 2281 kfree(chip); 2282 2283 return 0; 2284} 2285 2286static int azx_dev_free(struct snd_device *device) 2287{ 2288 return azx_free(device->device_data); 2289} 2290 2291/* 2292 * white/black-listing for position_fix 2293 */ 2294static struct snd_pci_quirk position_fix_list[] __devinitdata = { 2295 SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB), 2296 SND_PCI_QUIRK(0x1025, 0x026f, "Acer Aspire 5538", POS_FIX_LPIB), 2297 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 2298 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 2299 SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB), 2300 SND_PCI_QUIRK(0x1028, 0x0470, "Dell Inspiron 1120", POS_FIX_LPIB), 2301 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 2302 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 2303 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 2304 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 2305 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 2306 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB), 2307 SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB), 2308 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 2309 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 2310 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 2311 SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB), 2312 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 2313 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 2314 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 2315 SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB), 2316 {} 2317}; 2318 2319static int __devinit check_position_fix(struct azx *chip, int fix) 2320{ 2321 const struct snd_pci_quirk *q; 2322 2323 switch (fix) { 2324 case POS_FIX_LPIB: 2325 case POS_FIX_POSBUF: 2326 return fix; 2327 } 2328 2329 /* Check VIA/ATI HD Audio Controller exist */ 2330 switch (chip->driver_type) { 2331 case AZX_DRIVER_VIA: 2332 case AZX_DRIVER_ATI: 2333 chip->via_dmapos_patch = 1; 2334 /* Use link position directly, avoid any transfer problem. */ 2335 return POS_FIX_LPIB; 2336 } 2337 chip->via_dmapos_patch = 0; 2338 2339 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 2340 if (q) { 2341 printk(KERN_INFO 2342 "hda_intel: position_fix set to %d " 2343 "for device %04x:%04x\n", 2344 q->value, q->subvendor, q->subdevice); 2345 return q->value; 2346 } 2347 return POS_FIX_AUTO; 2348} 2349 2350/* 2351 * black-lists for probe_mask 2352 */ 2353static struct snd_pci_quirk probe_mask_list[] __devinitdata = { 2354 /* Thinkpad often breaks the controller communication when accessing 2355 * to the non-working (or non-existing) modem codec slot. 2356 */ 2357 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 2358 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 2359 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 2360 /* broken BIOS */ 2361 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 2362 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 2363 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 2364 /* forced codec slots */ 2365 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 2366 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 2367 {} 2368}; 2369 2370#define AZX_FORCE_CODEC_MASK 0x100 2371 2372static void __devinit check_probe_mask(struct azx *chip, int dev) 2373{ 2374 const struct snd_pci_quirk *q; 2375 2376 chip->codec_probe_mask = probe_mask[dev]; 2377 if (chip->codec_probe_mask == -1) { 2378 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 2379 if (q) { 2380 printk(KERN_INFO 2381 "hda_intel: probe_mask set to 0x%x " 2382 "for device %04x:%04x\n", 2383 q->value, q->subvendor, q->subdevice); 2384 chip->codec_probe_mask = q->value; 2385 } 2386 } 2387 2388 /* check forced option */ 2389 if (chip->codec_probe_mask != -1 && 2390 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 2391 chip->codec_mask = chip->codec_probe_mask & 0xff; 2392 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n", 2393 chip->codec_mask); 2394 } 2395} 2396 2397/* 2398 * white/black-list for enable_msi 2399 */ 2400static struct snd_pci_quirk msi_black_list[] __devinitdata = { 2401 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 2402 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 2403 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 2404 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 2405 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 2406 {} 2407}; 2408 2409static void __devinit check_msi(struct azx *chip) 2410{ 2411 const struct snd_pci_quirk *q; 2412 2413 if (enable_msi >= 0) { 2414 chip->msi = !!enable_msi; 2415 return; 2416 } 2417 chip->msi = 1; /* enable MSI as default */ 2418 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 2419 if (q) { 2420 printk(KERN_INFO 2421 "hda_intel: msi for device %04x:%04x set to %d\n", 2422 q->subvendor, q->subdevice, q->value); 2423 chip->msi = q->value; 2424 return; 2425 } 2426 2427 /* NVidia chipsets seem to cause troubles with MSI */ 2428 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 2429 printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n"); 2430 chip->msi = 0; 2431 } 2432} 2433 2434 2435/* 2436 * constructor 2437 */ 2438static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci, 2439 int dev, int driver_type, 2440 struct azx **rchip) 2441{ 2442 struct azx *chip; 2443 int i, err; 2444 unsigned short gcap; 2445 static struct snd_device_ops ops = { 2446 .dev_free = azx_dev_free, 2447 }; 2448 2449 *rchip = NULL; 2450 2451 err = pci_enable_device(pci); 2452 if (err < 0) 2453 return err; 2454 2455 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2456 if (!chip) { 2457 snd_printk(KERN_ERR SFX "cannot allocate chip\n"); 2458 pci_disable_device(pci); 2459 return -ENOMEM; 2460 } 2461 2462 spin_lock_init(&chip->reg_lock); 2463 mutex_init(&chip->open_mutex); 2464 chip->card = card; 2465 chip->pci = pci; 2466 chip->irq = -1; 2467 chip->driver_type = driver_type; 2468 check_msi(chip); 2469 chip->dev_index = dev; 2470 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work); 2471 2472 chip->position_fix[0] = chip->position_fix[1] = 2473 check_position_fix(chip, position_fix[dev]); 2474 check_probe_mask(chip, dev); 2475 2476 chip->single_cmd = single_cmd; 2477 2478 if (bdl_pos_adj[dev] < 0) { 2479 switch (chip->driver_type) { 2480 case AZX_DRIVER_ICH: 2481 case AZX_DRIVER_PCH: 2482 bdl_pos_adj[dev] = 1; 2483 break; 2484 default: 2485 bdl_pos_adj[dev] = 32; 2486 break; 2487 } 2488 } 2489 2490#if BITS_PER_LONG != 64 2491 /* Fix up base address on ULI M5461 */ 2492 if (chip->driver_type == AZX_DRIVER_ULI) { 2493 u16 tmp3; 2494 pci_read_config_word(pci, 0x40, &tmp3); 2495 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 2496 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 2497 } 2498#endif 2499 2500 err = pci_request_regions(pci, "ICH HD audio"); 2501 if (err < 0) { 2502 kfree(chip); 2503 pci_disable_device(pci); 2504 return err; 2505 } 2506 2507 chip->addr = pci_resource_start(pci, 0); 2508 chip->remap_addr = pci_ioremap_bar(pci, 0); 2509 if (chip->remap_addr == NULL) { 2510 snd_printk(KERN_ERR SFX "ioremap error\n"); 2511 err = -ENXIO; 2512 goto errout; 2513 } 2514 2515 if (chip->msi) 2516 if (pci_enable_msi(pci) < 0) 2517 chip->msi = 0; 2518 2519 if (azx_acquire_irq(chip, 0) < 0) { 2520 err = -EBUSY; 2521 goto errout; 2522 } 2523 2524 pci_set_master(pci); 2525 synchronize_irq(chip->irq); 2526 2527 gcap = azx_readw(chip, GCAP); 2528 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap); 2529 2530 /* disable SB600 64bit support for safety */ 2531 if ((chip->driver_type == AZX_DRIVER_ATI) || 2532 (chip->driver_type == AZX_DRIVER_ATIHDMI)) { 2533 struct pci_dev *p_smbus; 2534 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 2535 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2536 NULL); 2537 if (p_smbus) { 2538 if (p_smbus->revision < 0x30) 2539 gcap &= ~ICH6_GCAP_64OK; 2540 pci_dev_put(p_smbus); 2541 } 2542 } 2543 2544 /* disable 64bit DMA address for Teradici */ 2545 /* it does not work with device 6549:1200 subsys e4a2:040b */ 2546 if (chip->driver_type == AZX_DRIVER_TERA) 2547 gcap &= ~ICH6_GCAP_64OK; 2548 2549 /* allow 64bit DMA address if supported by H/W */ 2550 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64))) 2551 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64)); 2552 else { 2553 pci_set_dma_mask(pci, DMA_BIT_MASK(32)); 2554 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); 2555 } 2556 2557 /* read number of streams from GCAP register instead of using 2558 * hardcoded value 2559 */ 2560 chip->capture_streams = (gcap >> 8) & 0x0f; 2561 chip->playback_streams = (gcap >> 12) & 0x0f; 2562 if (!chip->playback_streams && !chip->capture_streams) { 2563 /* gcap didn't give any info, switching to old method */ 2564 2565 switch (chip->driver_type) { 2566 case AZX_DRIVER_ULI: 2567 chip->playback_streams = ULI_NUM_PLAYBACK; 2568 chip->capture_streams = ULI_NUM_CAPTURE; 2569 break; 2570 case AZX_DRIVER_ATIHDMI: 2571 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 2572 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 2573 break; 2574 case AZX_DRIVER_GENERIC: 2575 default: 2576 chip->playback_streams = ICH6_NUM_PLAYBACK; 2577 chip->capture_streams = ICH6_NUM_CAPTURE; 2578 break; 2579 } 2580 } 2581 chip->capture_index_offset = 0; 2582 chip->playback_index_offset = chip->capture_streams; 2583 chip->num_streams = chip->playback_streams + chip->capture_streams; 2584 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), 2585 GFP_KERNEL); 2586 if (!chip->azx_dev) { 2587 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n"); 2588 goto errout; 2589 } 2590 2591 for (i = 0; i < chip->num_streams; i++) { 2592 /* allocate memory for the BDL for each stream */ 2593 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 2594 snd_dma_pci_data(chip->pci), 2595 BDL_SIZE, &chip->azx_dev[i].bdl); 2596 if (err < 0) { 2597 snd_printk(KERN_ERR SFX "cannot allocate BDL\n"); 2598 goto errout; 2599 } 2600 } 2601 /* allocate memory for the position buffer */ 2602 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 2603 snd_dma_pci_data(chip->pci), 2604 chip->num_streams * 8, &chip->posbuf); 2605 if (err < 0) { 2606 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n"); 2607 goto errout; 2608 } 2609 /* allocate CORB/RIRB */ 2610 err = azx_alloc_cmd_io(chip); 2611 if (err < 0) 2612 goto errout; 2613 2614 /* initialize streams */ 2615 azx_init_stream(chip); 2616 2617 /* initialize chip */ 2618 azx_init_pci(chip); 2619 azx_init_chip(chip, (probe_only[dev] & 2) == 0); 2620 2621 /* codec detection */ 2622 if (!chip->codec_mask) { 2623 snd_printk(KERN_ERR SFX "no codecs found!\n"); 2624 err = -ENODEV; 2625 goto errout; 2626 } 2627 2628 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 2629 if (err <0) { 2630 snd_printk(KERN_ERR SFX "Error creating device [card]!\n"); 2631 goto errout; 2632 } 2633 2634 strcpy(card->driver, "HDA-Intel"); 2635 strlcpy(card->shortname, driver_short_names[chip->driver_type], 2636 sizeof(card->shortname)); 2637 snprintf(card->longname, sizeof(card->longname), 2638 "%s at 0x%lx irq %i", 2639 card->shortname, chip->addr, chip->irq); 2640 2641 *rchip = chip; 2642 return 0; 2643 2644 errout: 2645 azx_free(chip); 2646 return err; 2647} 2648 2649static void power_down_all_codecs(struct azx *chip) 2650{ 2651#ifdef CONFIG_SND_HDA_POWER_SAVE 2652 /* The codecs were powered up in snd_hda_codec_new(). 2653 * Now all initialization done, so turn them down if possible 2654 */ 2655 struct hda_codec *codec; 2656 list_for_each_entry(codec, &chip->bus->codec_list, list) { 2657 snd_hda_power_down(codec); 2658 } 2659#endif 2660} 2661 2662static int __devinit azx_probe(struct pci_dev *pci, 2663 const struct pci_device_id *pci_id) 2664{ 2665 static int dev; 2666 struct snd_card *card; 2667 struct azx *chip; 2668 int err; 2669 2670 if (dev >= SNDRV_CARDS) 2671 return -ENODEV; 2672 if (!enable[dev]) { 2673 dev++; 2674 return -ENOENT; 2675 } 2676 2677 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); 2678 if (err < 0) { 2679 snd_printk(KERN_ERR SFX "Error creating card!\n"); 2680 return err; 2681 } 2682 2683 /* set this here since it's referred in snd_hda_load_patch() */ 2684 snd_card_set_dev(card, &pci->dev); 2685 2686 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2687 if (err < 0) 2688 goto out_free; 2689 card->private_data = chip; 2690 2691#ifdef CONFIG_SND_HDA_INPUT_BEEP 2692 chip->beep_mode = beep_mode[dev]; 2693#endif 2694 2695 /* create codec instances */ 2696 err = azx_codec_create(chip, model[dev]); 2697 if (err < 0) 2698 goto out_free; 2699#ifdef CONFIG_SND_HDA_PATCH_LOADER 2700 if (patch[dev]) { 2701 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n", 2702 patch[dev]); 2703 err = snd_hda_load_patch(chip->bus, patch[dev]); 2704 if (err < 0) 2705 goto out_free; 2706 } 2707#endif 2708 if ((probe_only[dev] & 1) == 0) { 2709 err = azx_codec_configure(chip); 2710 if (err < 0) 2711 goto out_free; 2712 } 2713 2714 /* create PCM streams */ 2715 err = snd_hda_build_pcms(chip->bus); 2716 if (err < 0) 2717 goto out_free; 2718 2719 /* create mixer controls */ 2720 err = azx_mixer_create(chip); 2721 if (err < 0) 2722 goto out_free; 2723 2724 err = snd_card_register(card); 2725 if (err < 0) 2726 goto out_free; 2727 2728 pci_set_drvdata(pci, card); 2729 chip->running = 1; 2730 power_down_all_codecs(chip); 2731 azx_notifier_register(chip); 2732 2733 dev++; 2734 return err; 2735out_free: 2736 snd_card_free(card); 2737 return err; 2738} 2739 2740static void __devexit azx_remove(struct pci_dev *pci) 2741{ 2742 snd_card_free(pci_get_drvdata(pci)); 2743 pci_set_drvdata(pci, NULL); 2744} 2745 2746/* PCI IDs */ 2747static DEFINE_PCI_DEVICE_TABLE(azx_ids) = { 2748 /* ICH 6..10 */ 2749 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH }, 2750 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH }, 2751 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH }, 2752 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH }, 2753 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH }, 2754 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH }, 2755 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH }, 2756 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH }, 2757 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH }, 2758 /* PCH */ 2759 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH }, 2760 { PCI_DEVICE(0x8086, 0x3b57), .driver_data = AZX_DRIVER_ICH }, 2761 /* CPT */ 2762 { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH }, 2763 /* PBG */ 2764 { PCI_DEVICE(0x8086, 0x1d20), .driver_data = AZX_DRIVER_PCH }, 2765 /* SCH */ 2766 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH }, 2767 /* ATI SB 450/600 */ 2768 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI }, 2769 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI }, 2770 /* ATI HDMI */ 2771 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI }, 2772 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI }, 2773 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI }, 2774 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI }, 2775 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI }, 2776 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI }, 2777 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI }, 2778 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI }, 2779 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI }, 2780 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI }, 2781 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI }, 2782 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI }, 2783 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI }, 2784 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI }, 2785 /* VIA VT8251/VT8237A */ 2786 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2787 /* SIS966 */ 2788 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2789 /* ULI M5461 */ 2790 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2791 /* NVIDIA MCP */ 2792 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2793 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2794 .class_mask = 0xffffff, 2795 .driver_data = AZX_DRIVER_NVIDIA }, 2796 /* Teradici */ 2797 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA }, 2798 /* Creative X-Fi (CA0110-IBG) */ 2799#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE) 2800 /* the following entry conflicts with snd-ctxfi driver, 2801 * as ctxfi driver mutates from HD-audio to native mode with 2802 * a special command sequence. 2803 */ 2804 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2805 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2806 .class_mask = 0xffffff, 2807 .driver_data = AZX_DRIVER_CTX }, 2808#else 2809 /* this entry seems still valid -- i.e. without emu20kx chip */ 2810 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_CTX }, 2811#endif 2812 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2813 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2814 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2815 .class_mask = 0xffffff, 2816 .driver_data = AZX_DRIVER_GENERIC }, 2817 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2818 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2819 .class_mask = 0xffffff, 2820 .driver_data = AZX_DRIVER_GENERIC }, 2821 { 0, } 2822}; 2823MODULE_DEVICE_TABLE(pci, azx_ids); 2824 2825/* pci_driver definition */ 2826static struct pci_driver driver = { 2827 .name = "HDA Intel", 2828 .id_table = azx_ids, 2829 .probe = azx_probe, 2830 .remove = __devexit_p(azx_remove), 2831#ifdef CONFIG_PM 2832 .suspend = azx_suspend, 2833 .resume = azx_resume, 2834#endif 2835}; 2836 2837static int __init alsa_card_azx_init(void) 2838{ 2839 return pci_register_driver(&driver); 2840} 2841 2842static void __exit alsa_card_azx_exit(void) 2843{ 2844 pci_unregister_driver(&driver); 2845} 2846 2847module_init(alsa_card_azx_init) 2848module_exit(alsa_card_azx_exit) 2849