1/* 2 * linux/drivers/video/vt8623fb.c - fbdev driver for 3 * integrated graphic core in VIA VT8623 [CLE266] chipset 4 * 5 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org> 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file COPYING in the main directory of this archive for 9 * more details. 10 * 11 * Code is based on s3fb, some parts are from David Boucher's viafb 12 * (http://davesdomain.org.uk/viafb/) 13 */ 14 15#include <linux/module.h> 16#include <linux/kernel.h> 17#include <linux/errno.h> 18#include <linux/string.h> 19#include <linux/mm.h> 20#include <linux/tty.h> 21#include <linux/delay.h> 22#include <linux/fb.h> 23#include <linux/svga.h> 24#include <linux/init.h> 25#include <linux/pci.h> 26#include <linux/console.h> /* Why should fb driver call console functions? because acquire_console_sem() */ 27#include <video/vga.h> 28 29#ifdef CONFIG_MTRR 30#include <asm/mtrr.h> 31#endif 32 33struct vt8623fb_info { 34 char __iomem *mmio_base; 35 int mtrr_reg; 36 struct vgastate state; 37 struct mutex open_lock; 38 unsigned int ref_count; 39 u32 pseudo_palette[16]; 40}; 41 42 43 44/* ------------------------------------------------------------------------- */ 45 46static const struct svga_fb_format vt8623fb_formats[] = { 47 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, 48 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP8, FB_VISUAL_PSEUDOCOLOR, 16, 16}, 49 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, 50 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 16, 16}, 51 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1, 52 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 16, 16}, 53 { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, 54 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 8}, 55/* {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0, 56 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4}, */ 57 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0, 58 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4}, 59 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, 60 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 2}, 61 SVGA_FORMAT_END 62}; 63 64static const struct svga_pll vt8623_pll = {2, 127, 2, 7, 0, 3, 65 60000, 300000, 14318}; 66 67/* CRT timing register sets */ 68 69static struct vga_regset vt8623_h_total_regs[] = {{0x00, 0, 7}, {0x36, 3, 3}, VGA_REGSET_END}; 70static struct vga_regset vt8623_h_display_regs[] = {{0x01, 0, 7}, VGA_REGSET_END}; 71static struct vga_regset vt8623_h_blank_start_regs[] = {{0x02, 0, 7}, VGA_REGSET_END}; 72static struct vga_regset vt8623_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, {0x33, 5, 5}, VGA_REGSET_END}; 73static struct vga_regset vt8623_h_sync_start_regs[] = {{0x04, 0, 7}, {0x33, 4, 4}, VGA_REGSET_END}; 74static struct vga_regset vt8623_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END}; 75 76static struct vga_regset vt8623_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x35, 0, 0}, VGA_REGSET_END}; 77static struct vga_regset vt8623_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x35, 2, 2}, VGA_REGSET_END}; 78static struct vga_regset vt8623_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x35, 3, 3}, VGA_REGSET_END}; 79static struct vga_regset vt8623_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END}; 80static struct vga_regset vt8623_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x35, 1, 1}, VGA_REGSET_END}; 81static struct vga_regset vt8623_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END}; 82 83static struct vga_regset vt8623_offset_regs[] = {{0x13, 0, 7}, {0x35, 5, 7}, VGA_REGSET_END}; 84static struct vga_regset vt8623_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x33, 0, 2}, {0x35, 4, 4}, VGA_REGSET_END}; 85static struct vga_regset vt8623_fetch_count_regs[] = {{0x1C, 0, 7}, {0x1D, 0, 1}, VGA_REGSET_END}; 86static struct vga_regset vt8623_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x34, 0, 7}, {0x48, 0, 1}, VGA_REGSET_END}; 87 88static struct svga_timing_regs vt8623_timing_regs = { 89 vt8623_h_total_regs, vt8623_h_display_regs, vt8623_h_blank_start_regs, 90 vt8623_h_blank_end_regs, vt8623_h_sync_start_regs, vt8623_h_sync_end_regs, 91 vt8623_v_total_regs, vt8623_v_display_regs, vt8623_v_blank_start_regs, 92 vt8623_v_blank_end_regs, vt8623_v_sync_start_regs, vt8623_v_sync_end_regs, 93}; 94 95 96/* ------------------------------------------------------------------------- */ 97 98 99/* Module parameters */ 100 101static char *mode_option = "640x480-8@60"; 102 103#ifdef CONFIG_MTRR 104static int mtrr = 1; 105#endif 106 107MODULE_AUTHOR("(c) 2006 Ondrej Zajicek <santiago@crfreenet.org>"); 108MODULE_LICENSE("GPL"); 109MODULE_DESCRIPTION("fbdev driver for integrated graphics core in VIA VT8623 [CLE266]"); 110 111module_param(mode_option, charp, 0644); 112MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)"); 113module_param_named(mode, mode_option, charp, 0); 114MODULE_PARM_DESC(mode, "Default video mode e.g. '648x480-8@60' (deprecated)"); 115 116#ifdef CONFIG_MTRR 117module_param(mtrr, int, 0444); 118MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)"); 119#endif 120 121 122/* ------------------------------------------------------------------------- */ 123 124 125static struct fb_tile_ops vt8623fb_tile_ops = { 126 .fb_settile = svga_settile, 127 .fb_tilecopy = svga_tilecopy, 128 .fb_tilefill = svga_tilefill, 129 .fb_tileblit = svga_tileblit, 130 .fb_tilecursor = svga_tilecursor, 131 .fb_get_tilemax = svga_get_tilemax, 132}; 133 134 135/* ------------------------------------------------------------------------- */ 136 137 138/* image data is MSB-first, fb structure is MSB-first too */ 139static inline u32 expand_color(u32 c) 140{ 141 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF; 142} 143 144/* vt8623fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */ 145static void vt8623fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image) 146{ 147 u32 fg = expand_color(image->fg_color); 148 u32 bg = expand_color(image->bg_color); 149 const u8 *src1, *src; 150 u8 __iomem *dst1; 151 u32 __iomem *dst; 152 u32 val; 153 int x, y; 154 155 src1 = image->data; 156 dst1 = info->screen_base + (image->dy * info->fix.line_length) 157 + ((image->dx / 8) * 4); 158 159 for (y = 0; y < image->height; y++) { 160 src = src1; 161 dst = (u32 __iomem *) dst1; 162 for (x = 0; x < image->width; x += 8) { 163 val = *(src++) * 0x01010101; 164 val = (val & fg) | (~val & bg); 165 fb_writel(val, dst++); 166 } 167 src1 += image->width / 8; 168 dst1 += info->fix.line_length; 169 } 170} 171 172/* vt8623fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */ 173static void vt8623fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 174{ 175 u32 fg = expand_color(rect->color); 176 u8 __iomem *dst1; 177 u32 __iomem *dst; 178 int x, y; 179 180 dst1 = info->screen_base + (rect->dy * info->fix.line_length) 181 + ((rect->dx / 8) * 4); 182 183 for (y = 0; y < rect->height; y++) { 184 dst = (u32 __iomem *) dst1; 185 for (x = 0; x < rect->width; x += 8) { 186 fb_writel(fg, dst++); 187 } 188 dst1 += info->fix.line_length; 189 } 190} 191 192 193/* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */ 194static inline u32 expand_pixel(u32 c) 195{ 196 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) | 197 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF; 198} 199 200/* vt8623fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */ 201static void vt8623fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image) 202{ 203 u32 fg = image->fg_color * 0x11111111; 204 u32 bg = image->bg_color * 0x11111111; 205 const u8 *src1, *src; 206 u8 __iomem *dst1; 207 u32 __iomem *dst; 208 u32 val; 209 int x, y; 210 211 src1 = image->data; 212 dst1 = info->screen_base + (image->dy * info->fix.line_length) 213 + ((image->dx / 8) * 4); 214 215 for (y = 0; y < image->height; y++) { 216 src = src1; 217 dst = (u32 __iomem *) dst1; 218 for (x = 0; x < image->width; x += 8) { 219 val = expand_pixel(*(src++)); 220 val = (val & fg) | (~val & bg); 221 fb_writel(val, dst++); 222 } 223 src1 += image->width / 8; 224 dst1 += info->fix.line_length; 225 } 226} 227 228static void vt8623fb_imageblit(struct fb_info *info, const struct fb_image *image) 229{ 230 if ((info->var.bits_per_pixel == 4) && (image->depth == 1) 231 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { 232 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) 233 vt8623fb_iplan_imageblit(info, image); 234 else 235 vt8623fb_cfb4_imageblit(info, image); 236 } else 237 cfb_imageblit(info, image); 238} 239 240static void vt8623fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 241{ 242 if ((info->var.bits_per_pixel == 4) 243 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) 244 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) 245 vt8623fb_iplan_fillrect(info, rect); 246 else 247 cfb_fillrect(info, rect); 248} 249 250 251/* ------------------------------------------------------------------------- */ 252 253 254static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock) 255{ 256 u16 m, n, r; 257 u8 regval; 258 int rv; 259 260 rv = svga_compute_pll(&vt8623_pll, 1000000000 / pixclock, &m, &n, &r, info->node); 261 if (rv < 0) { 262 printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node); 263 return; 264 } 265 266 /* Set VGA misc register */ 267 regval = vga_r(NULL, VGA_MIS_R); 268 vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); 269 270 /* Set clock registers */ 271 vga_wseq(NULL, 0x46, (n | (r << 6))); 272 vga_wseq(NULL, 0x47, m); 273 274 udelay(1000); 275 276 /* PLL reset */ 277 svga_wseq_mask(0x40, 0x02, 0x02); 278 svga_wseq_mask(0x40, 0x00, 0x02); 279} 280 281 282static int vt8623fb_open(struct fb_info *info, int user) 283{ 284 struct vt8623fb_info *par = info->par; 285 286 mutex_lock(&(par->open_lock)); 287 if (par->ref_count == 0) { 288 memset(&(par->state), 0, sizeof(struct vgastate)); 289 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; 290 par->state.num_crtc = 0xA2; 291 par->state.num_seq = 0x50; 292 save_vga(&(par->state)); 293 } 294 295 par->ref_count++; 296 mutex_unlock(&(par->open_lock)); 297 298 return 0; 299} 300 301static int vt8623fb_release(struct fb_info *info, int user) 302{ 303 struct vt8623fb_info *par = info->par; 304 305 mutex_lock(&(par->open_lock)); 306 if (par->ref_count == 0) { 307 mutex_unlock(&(par->open_lock)); 308 return -EINVAL; 309 } 310 311 if (par->ref_count == 1) 312 restore_vga(&(par->state)); 313 314 par->ref_count--; 315 mutex_unlock(&(par->open_lock)); 316 317 return 0; 318} 319 320static int vt8623fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 321{ 322 int rv, mem, step; 323 324 /* Find appropriate format */ 325 rv = svga_match_format (vt8623fb_formats, var, NULL); 326 if (rv < 0) 327 { 328 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node); 329 return rv; 330 } 331 332 /* Do not allow to have real resoulution larger than virtual */ 333 if (var->xres > var->xres_virtual) 334 var->xres_virtual = var->xres; 335 336 if (var->yres > var->yres_virtual) 337 var->yres_virtual = var->yres; 338 339 /* Round up xres_virtual to have proper alignment of lines */ 340 step = vt8623fb_formats[rv].xresstep - 1; 341 var->xres_virtual = (var->xres_virtual+step) & ~step; 342 343 /* Check whether have enough memory */ 344 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; 345 if (mem > info->screen_size) 346 { 347 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", info->node, mem >> 10, (unsigned int) (info->screen_size >> 10)); 348 return -EINVAL; 349 } 350 351 /* Text mode is limited to 256 kB of memory */ 352 if ((var->bits_per_pixel == 0) && (mem > (256*1024))) 353 { 354 printk(KERN_ERR "fb%d: text framebuffer size too large (%d kB requested, 256 kB possible)\n", info->node, mem >> 10); 355 return -EINVAL; 356 } 357 358 rv = svga_check_timings (&vt8623_timing_regs, var, info->node); 359 if (rv < 0) 360 { 361 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node); 362 return rv; 363 } 364 365 /* Interlaced mode not supported */ 366 if (var->vmode & FB_VMODE_INTERLACED) 367 return -EINVAL; 368 369 return 0; 370} 371 372 373static int vt8623fb_set_par(struct fb_info *info) 374{ 375 u32 mode, offset_value, fetch_value, screen_size; 376 u32 bpp = info->var.bits_per_pixel; 377 378 if (bpp != 0) { 379 info->fix.ypanstep = 1; 380 info->fix.line_length = (info->var.xres_virtual * bpp) / 8; 381 382 info->flags &= ~FBINFO_MISC_TILEBLITTING; 383 info->tileops = NULL; 384 385 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */ 386 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); 387 info->pixmap.blit_y = ~(u32)0; 388 389 offset_value = (info->var.xres_virtual * bpp) / 64; 390 fetch_value = ((info->var.xres * bpp) / 128) + 4; 391 392 if (bpp == 4) 393 fetch_value = (info->var.xres / 8) + 8; /* + 0 is OK */ 394 395 screen_size = info->var.yres_virtual * info->fix.line_length; 396 } else { 397 info->fix.ypanstep = 16; 398 info->fix.line_length = 0; 399 400 info->flags |= FBINFO_MISC_TILEBLITTING; 401 info->tileops = &vt8623fb_tile_ops; 402 403 /* supports 8x16 tiles only */ 404 info->pixmap.blit_x = 1 << (8 - 1); 405 info->pixmap.blit_y = 1 << (16 - 1); 406 407 offset_value = info->var.xres_virtual / 16; 408 fetch_value = (info->var.xres / 8) + 8; 409 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; 410 } 411 412 info->var.xoffset = 0; 413 info->var.yoffset = 0; 414 info->var.activate = FB_ACTIVATE_NOW; 415 416 /* Unlock registers */ 417 svga_wseq_mask(0x10, 0x01, 0x01); 418 svga_wcrt_mask(0x11, 0x00, 0x80); 419 svga_wcrt_mask(0x47, 0x00, 0x01); 420 421 /* Device, screen and sync off */ 422 svga_wseq_mask(0x01, 0x20, 0x20); 423 svga_wcrt_mask(0x36, 0x30, 0x30); 424 svga_wcrt_mask(0x17, 0x00, 0x80); 425 426 /* Set default values */ 427 svga_set_default_gfx_regs(); 428 svga_set_default_atc_regs(); 429 svga_set_default_seq_regs(); 430 svga_set_default_crt_regs(); 431 svga_wcrt_multi(vt8623_line_compare_regs, 0xFFFFFFFF); 432 svga_wcrt_multi(vt8623_start_address_regs, 0); 433 434 svga_wcrt_multi(vt8623_offset_regs, offset_value); 435 svga_wseq_multi(vt8623_fetch_count_regs, fetch_value); 436 437 /* Clear H/V Skew */ 438 svga_wcrt_mask(0x03, 0x00, 0x60); 439 svga_wcrt_mask(0x05, 0x00, 0x60); 440 441 if (info->var.vmode & FB_VMODE_DOUBLE) 442 svga_wcrt_mask(0x09, 0x80, 0x80); 443 else 444 svga_wcrt_mask(0x09, 0x00, 0x80); 445 446 svga_wseq_mask(0x1E, 0xF0, 0xF0); // DI/DVP bus 447 svga_wseq_mask(0x2A, 0x0F, 0x0F); // DI/DVP bus 448 svga_wseq_mask(0x16, 0x08, 0xBF); // FIFO read threshold 449 vga_wseq(NULL, 0x17, 0x1F); // FIFO depth 450 vga_wseq(NULL, 0x18, 0x4E); 451 svga_wseq_mask(0x1A, 0x08, 0x08); // enable MMIO ? 452 453 vga_wcrt(NULL, 0x32, 0x00); 454 vga_wcrt(NULL, 0x34, 0x00); 455 vga_wcrt(NULL, 0x6A, 0x80); 456 vga_wcrt(NULL, 0x6A, 0xC0); 457 458 vga_wgfx(NULL, 0x20, 0x00); 459 vga_wgfx(NULL, 0x21, 0x00); 460 vga_wgfx(NULL, 0x22, 0x00); 461 462 /* Set SR15 according to number of bits per pixel */ 463 mode = svga_match_format(vt8623fb_formats, &(info->var), &(info->fix)); 464 switch (mode) { 465 case 0: 466 pr_debug("fb%d: text mode\n", info->node); 467 svga_set_textmode_vga_regs(); 468 svga_wseq_mask(0x15, 0x00, 0xFE); 469 svga_wcrt_mask(0x11, 0x60, 0x70); 470 break; 471 case 1: 472 pr_debug("fb%d: 4 bit pseudocolor\n", info->node); 473 vga_wgfx(NULL, VGA_GFX_MODE, 0x40); 474 svga_wseq_mask(0x15, 0x20, 0xFE); 475 svga_wcrt_mask(0x11, 0x00, 0x70); 476 break; 477 case 2: 478 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); 479 svga_wseq_mask(0x15, 0x00, 0xFE); 480 svga_wcrt_mask(0x11, 0x00, 0x70); 481 break; 482 case 3: 483 pr_debug("fb%d: 8 bit pseudocolor\n", info->node); 484 svga_wseq_mask(0x15, 0x22, 0xFE); 485 break; 486 case 4: 487 pr_debug("fb%d: 5/6/5 truecolor\n", info->node); 488 svga_wseq_mask(0x15, 0xB6, 0xFE); 489 break; 490 case 5: 491 pr_debug("fb%d: 8/8/8 truecolor\n", info->node); 492 svga_wseq_mask(0x15, 0xAE, 0xFE); 493 break; 494 default: 495 printk(KERN_ERR "vt8623fb: unsupported mode - bug\n"); 496 return (-EINVAL); 497 } 498 499 vt8623_set_pixclock(info, info->var.pixclock); 500 svga_set_timings(&vt8623_timing_regs, &(info->var), 1, 1, 501 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, 1, 502 1, info->node); 503 504 memset_io(info->screen_base, 0x00, screen_size); 505 506 /* Device and screen back on */ 507 svga_wcrt_mask(0x17, 0x80, 0x80); 508 svga_wcrt_mask(0x36, 0x00, 0x30); 509 svga_wseq_mask(0x01, 0x00, 0x20); 510 511 return 0; 512} 513 514 515static int vt8623fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 516 u_int transp, struct fb_info *fb) 517{ 518 switch (fb->var.bits_per_pixel) { 519 case 0: 520 case 4: 521 if (regno >= 16) 522 return -EINVAL; 523 524 outb(0x0F, VGA_PEL_MSK); 525 outb(regno, VGA_PEL_IW); 526 outb(red >> 10, VGA_PEL_D); 527 outb(green >> 10, VGA_PEL_D); 528 outb(blue >> 10, VGA_PEL_D); 529 break; 530 case 8: 531 if (regno >= 256) 532 return -EINVAL; 533 534 outb(0xFF, VGA_PEL_MSK); 535 outb(regno, VGA_PEL_IW); 536 outb(red >> 10, VGA_PEL_D); 537 outb(green >> 10, VGA_PEL_D); 538 outb(blue >> 10, VGA_PEL_D); 539 break; 540 case 16: 541 if (regno >= 16) 542 return 0; 543 544 if (fb->var.green.length == 5) 545 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | 546 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11); 547 else if (fb->var.green.length == 6) 548 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) | 549 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11); 550 else 551 return -EINVAL; 552 break; 553 case 24: 554 case 32: 555 if (regno >= 16) 556 return 0; 557 558 /* ((transp & 0xFF00) << 16) */ 559 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | 560 (green & 0xFF00) | ((blue & 0xFF00) >> 8); 561 break; 562 default: 563 return -EINVAL; 564 } 565 566 return 0; 567} 568 569 570static int vt8623fb_blank(int blank_mode, struct fb_info *info) 571{ 572 switch (blank_mode) { 573 case FB_BLANK_UNBLANK: 574 pr_debug("fb%d: unblank\n", info->node); 575 svga_wcrt_mask(0x36, 0x00, 0x30); 576 svga_wseq_mask(0x01, 0x00, 0x20); 577 break; 578 case FB_BLANK_NORMAL: 579 pr_debug("fb%d: blank\n", info->node); 580 svga_wcrt_mask(0x36, 0x00, 0x30); 581 svga_wseq_mask(0x01, 0x20, 0x20); 582 break; 583 case FB_BLANK_HSYNC_SUSPEND: 584 pr_debug("fb%d: DPMS standby (hsync off)\n", info->node); 585 svga_wcrt_mask(0x36, 0x10, 0x30); 586 svga_wseq_mask(0x01, 0x20, 0x20); 587 break; 588 case FB_BLANK_VSYNC_SUSPEND: 589 pr_debug("fb%d: DPMS suspend (vsync off)\n", info->node); 590 svga_wcrt_mask(0x36, 0x20, 0x30); 591 svga_wseq_mask(0x01, 0x20, 0x20); 592 break; 593 case FB_BLANK_POWERDOWN: 594 pr_debug("fb%d: DPMS off (no sync)\n", info->node); 595 svga_wcrt_mask(0x36, 0x30, 0x30); 596 svga_wseq_mask(0x01, 0x20, 0x20); 597 break; 598 } 599 600 return 0; 601} 602 603 604static int vt8623fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 605{ 606 unsigned int offset; 607 608 /* Calculate the offset */ 609 if (var->bits_per_pixel == 0) { 610 offset = (var->yoffset / 16) * var->xres_virtual + var->xoffset; 611 offset = offset >> 3; 612 } else { 613 offset = (var->yoffset * info->fix.line_length) + 614 (var->xoffset * var->bits_per_pixel / 8); 615 offset = offset >> ((var->bits_per_pixel == 4) ? 2 : 1); 616 } 617 618 /* Set the offset */ 619 svga_wcrt_multi(vt8623_start_address_regs, offset); 620 621 return 0; 622} 623 624 625/* ------------------------------------------------------------------------- */ 626 627 628/* Frame buffer operations */ 629 630static struct fb_ops vt8623fb_ops = { 631 .owner = THIS_MODULE, 632 .fb_open = vt8623fb_open, 633 .fb_release = vt8623fb_release, 634 .fb_check_var = vt8623fb_check_var, 635 .fb_set_par = vt8623fb_set_par, 636 .fb_setcolreg = vt8623fb_setcolreg, 637 .fb_blank = vt8623fb_blank, 638 .fb_pan_display = vt8623fb_pan_display, 639 .fb_fillrect = vt8623fb_fillrect, 640 .fb_copyarea = cfb_copyarea, 641 .fb_imageblit = vt8623fb_imageblit, 642 .fb_get_caps = svga_get_caps, 643}; 644 645 646/* PCI probe */ 647 648static int __devinit vt8623_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 649{ 650 struct fb_info *info; 651 struct vt8623fb_info *par; 652 unsigned int memsize1, memsize2; 653 int rc; 654 655 /* Ignore secondary VGA device because there is no VGA arbitration */ 656 if (! svga_primary_device(dev)) { 657 dev_info(&(dev->dev), "ignoring secondary device\n"); 658 return -ENODEV; 659 } 660 661 /* Allocate and fill driver data structure */ 662 info = framebuffer_alloc(sizeof(struct vt8623fb_info), &(dev->dev)); 663 if (! info) { 664 dev_err(&(dev->dev), "cannot allocate memory\n"); 665 return -ENOMEM; 666 } 667 668 par = info->par; 669 mutex_init(&par->open_lock); 670 671 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN; 672 info->fbops = &vt8623fb_ops; 673 674 /* Prepare PCI device */ 675 676 rc = pci_enable_device(dev); 677 if (rc < 0) { 678 dev_err(info->device, "cannot enable PCI device\n"); 679 goto err_enable_device; 680 } 681 682 rc = pci_request_regions(dev, "vt8623fb"); 683 if (rc < 0) { 684 dev_err(info->device, "cannot reserve framebuffer region\n"); 685 goto err_request_regions; 686 } 687 688 info->fix.smem_start = pci_resource_start(dev, 0); 689 info->fix.smem_len = pci_resource_len(dev, 0); 690 info->fix.mmio_start = pci_resource_start(dev, 1); 691 info->fix.mmio_len = pci_resource_len(dev, 1); 692 693 /* Map physical IO memory address into kernel space */ 694 info->screen_base = pci_iomap(dev, 0, 0); 695 if (! info->screen_base) { 696 rc = -ENOMEM; 697 dev_err(info->device, "iomap for framebuffer failed\n"); 698 goto err_iomap_1; 699 } 700 701 par->mmio_base = pci_iomap(dev, 1, 0); 702 if (! par->mmio_base) { 703 rc = -ENOMEM; 704 dev_err(info->device, "iomap for MMIO failed\n"); 705 goto err_iomap_2; 706 } 707 708 /* Find how many physical memory there is on card */ 709 memsize1 = (vga_rseq(NULL, 0x34) + 1) >> 1; 710 memsize2 = vga_rseq(NULL, 0x39) << 2; 711 712 if ((16 <= memsize1) && (memsize1 <= 64) && (memsize1 == memsize2)) 713 info->screen_size = memsize1 << 20; 714 else { 715 dev_err(info->device, "memory size detection failed (%x %x), suppose 16 MB\n", memsize1, memsize2); 716 info->screen_size = 16 << 20; 717 } 718 719 info->fix.smem_len = info->screen_size; 720 strcpy(info->fix.id, "VIA VT8623"); 721 info->fix.type = FB_TYPE_PACKED_PIXELS; 722 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 723 info->fix.ypanstep = 0; 724 info->fix.accel = FB_ACCEL_NONE; 725 info->pseudo_palette = (void*)par->pseudo_palette; 726 727 /* Prepare startup mode */ 728 729 kparam_block_sysfs_write(mode_option); 730 rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8); 731 kparam_unblock_sysfs_write(mode_option); 732 if (! ((rc == 1) || (rc == 2))) { 733 rc = -EINVAL; 734 dev_err(info->device, "mode %s not found\n", mode_option); 735 goto err_find_mode; 736 } 737 738 rc = fb_alloc_cmap(&info->cmap, 256, 0); 739 if (rc < 0) { 740 dev_err(info->device, "cannot allocate colormap\n"); 741 goto err_alloc_cmap; 742 } 743 744 rc = register_framebuffer(info); 745 if (rc < 0) { 746 dev_err(info->device, "cannot register framebugger\n"); 747 goto err_reg_fb; 748 } 749 750 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM\n", info->node, info->fix.id, 751 pci_name(dev), info->fix.smem_len >> 20); 752 753 /* Record a reference to the driver data */ 754 pci_set_drvdata(dev, info); 755 756#ifdef CONFIG_MTRR 757 if (mtrr) { 758 par->mtrr_reg = -1; 759 par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1); 760 } 761#endif 762 763 return 0; 764 765 /* Error handling */ 766err_reg_fb: 767 fb_dealloc_cmap(&info->cmap); 768err_alloc_cmap: 769err_find_mode: 770 pci_iounmap(dev, par->mmio_base); 771err_iomap_2: 772 pci_iounmap(dev, info->screen_base); 773err_iomap_1: 774 pci_release_regions(dev); 775err_request_regions: 776/* pci_disable_device(dev); */ 777err_enable_device: 778 framebuffer_release(info); 779 return rc; 780} 781 782/* PCI remove */ 783 784static void __devexit vt8623_pci_remove(struct pci_dev *dev) 785{ 786 struct fb_info *info = pci_get_drvdata(dev); 787 788 if (info) { 789 struct vt8623fb_info *par = info->par; 790 791#ifdef CONFIG_MTRR 792 if (par->mtrr_reg >= 0) { 793 mtrr_del(par->mtrr_reg, 0, 0); 794 par->mtrr_reg = -1; 795 } 796#endif 797 798 unregister_framebuffer(info); 799 fb_dealloc_cmap(&info->cmap); 800 801 pci_iounmap(dev, info->screen_base); 802 pci_iounmap(dev, par->mmio_base); 803 pci_release_regions(dev); 804/* pci_disable_device(dev); */ 805 806 pci_set_drvdata(dev, NULL); 807 framebuffer_release(info); 808 } 809} 810 811 812#ifdef CONFIG_PM 813/* PCI suspend */ 814 815static int vt8623_pci_suspend(struct pci_dev* dev, pm_message_t state) 816{ 817 struct fb_info *info = pci_get_drvdata(dev); 818 struct vt8623fb_info *par = info->par; 819 820 dev_info(info->device, "suspend\n"); 821 822 acquire_console_sem(); 823 mutex_lock(&(par->open_lock)); 824 825 if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) { 826 mutex_unlock(&(par->open_lock)); 827 release_console_sem(); 828 return 0; 829 } 830 831 fb_set_suspend(info, 1); 832 833 pci_save_state(dev); 834 pci_disable_device(dev); 835 pci_set_power_state(dev, pci_choose_state(dev, state)); 836 837 mutex_unlock(&(par->open_lock)); 838 release_console_sem(); 839 840 return 0; 841} 842 843 844/* PCI resume */ 845 846static int vt8623_pci_resume(struct pci_dev* dev) 847{ 848 struct fb_info *info = pci_get_drvdata(dev); 849 struct vt8623fb_info *par = info->par; 850 851 dev_info(info->device, "resume\n"); 852 853 acquire_console_sem(); 854 mutex_lock(&(par->open_lock)); 855 856 if (par->ref_count == 0) 857 goto fail; 858 859 pci_set_power_state(dev, PCI_D0); 860 pci_restore_state(dev); 861 862 if (pci_enable_device(dev)) 863 goto fail; 864 865 pci_set_master(dev); 866 867 vt8623fb_set_par(info); 868 fb_set_suspend(info, 0); 869 870fail: 871 mutex_unlock(&(par->open_lock)); 872 release_console_sem(); 873 874 return 0; 875} 876#else 877#define vt8623_pci_suspend NULL 878#define vt8623_pci_resume NULL 879#endif /* CONFIG_PM */ 880 881/* List of boards that we are trying to support */ 882 883static struct pci_device_id vt8623_devices[] __devinitdata = { 884 {PCI_DEVICE(PCI_VENDOR_ID_VIA, 0x3122)}, 885 {0, 0, 0, 0, 0, 0, 0} 886}; 887 888MODULE_DEVICE_TABLE(pci, vt8623_devices); 889 890static struct pci_driver vt8623fb_pci_driver = { 891 .name = "vt8623fb", 892 .id_table = vt8623_devices, 893 .probe = vt8623_pci_probe, 894 .remove = __devexit_p(vt8623_pci_remove), 895 .suspend = vt8623_pci_suspend, 896 .resume = vt8623_pci_resume, 897}; 898 899/* Cleanup */ 900 901static void __exit vt8623fb_cleanup(void) 902{ 903 pr_debug("vt8623fb: cleaning up\n"); 904 pci_unregister_driver(&vt8623fb_pci_driver); 905} 906 907/* Driver Initialisation */ 908 909static int __init vt8623fb_init(void) 910{ 911 912#ifndef MODULE 913 char *option = NULL; 914 915 if (fb_get_options("vt8623fb", &option)) 916 return -ENODEV; 917 918 if (option && *option) 919 mode_option = option; 920#endif 921 922 pr_debug("vt8623fb: initializing\n"); 923 return pci_register_driver(&vt8623fb_pci_driver); 924} 925 926/* ------------------------------------------------------------------------- */ 927 928/* Modularization */ 929 930module_init(vt8623fb_init); 931module_exit(vt8623fb_cleanup); 932