1/* 2 * linux/drivers/video/sstfb.c -- voodoo graphics frame buffer 3 * 4 * Copyright (c) 2000-2002 Ghozlane Toumi <gtoumi@laposte.net> 5 * 6 * Created 15 Jan 2000 by Ghozlane Toumi 7 * 8 * Contributions (and many thanks) : 9 * 10 * 03/2001 James Simmons <jsimmons@infradead.org> 11 * 04/2001 Paul Mundt <lethal@chaoticdreams.org> 12 * 05/2001 Urs Ganse <ursg@uni.de> 13 * (initial work on voodoo2 port, interlace) 14 * 09/2002 Helge Deller <deller@gmx.de> 15 * (enable driver on big-endian machines (hppa), ioctl fixes) 16 * 12/2002 Helge Deller <deller@gmx.de> 17 * (port driver to new frambuffer infrastructure) 18 * 01/2003 Helge Deller <deller@gmx.de> 19 * (initial work on fb hardware acceleration for voodoo2) 20 * 08/2006 Alan Cox <alan@redhat.com> 21 * Remove never finished and bogus 24/32bit support 22 * Clean up macro abuse 23 * Minor tidying for format. 24 * 12/2006 Helge Deller <deller@gmx.de> 25 * add /sys/class/graphics/fbX/vgapass sysfs-interface 26 * add module option "mode_option" to set initial screen mode 27 * use fbdev default videomode database 28 * remove debug functions from ioctl 29 */ 30 31/* 32 * The voodoo1 has the following memory mapped address space: 33 * 0x000000 - 0x3fffff : registers (4MB) 34 * 0x400000 - 0x7fffff : linear frame buffer (4MB) 35 * 0x800000 - 0xffffff : texture memory (8MB) 36 */ 37 38 39/* 40 * debug info 41 * SST_DEBUG : enable debugging 42 * SST_DEBUG_REG : debug registers 43 * 0 : no debug 44 * 1 : dac calls, [un]set_bits, FbiInit 45 * 2 : insane debug level (log every register read/write) 46 * SST_DEBUG_FUNC : functions 47 * 0 : no debug 48 * 1 : function call / debug ioctl 49 * 2 : variables 50 * 3 : flood . you don't want to do that. trust me. 51 * SST_DEBUG_VAR : debug display/var structs 52 * 0 : no debug 53 * 1 : dumps display, fb_var 54 * 55 * sstfb specific ioctls: 56 * toggle vga (0x46db) : toggle vga_pass_through 57 */ 58 59#undef SST_DEBUG 60 61 62/* 63 * Includes 64 */ 65 66#include <linux/string.h> 67#include <linux/kernel.h> 68#include <linux/module.h> 69#include <linux/fb.h> 70#include <linux/pci.h> 71#include <linux/delay.h> 72#include <linux/init.h> 73#include <asm/io.h> 74#include <linux/uaccess.h> 75#include <video/sstfb.h> 76 77 78/* initialized by setup */ 79 80static int vgapass; /* enable VGA passthrough cable */ 81static int mem; /* mem size in MB, 0 = autodetect */ 82static int clipping = 1; /* use clipping (slower, safer) */ 83static int gfxclk; /* force FBI freq in Mhz . Dangerous */ 84static int slowpci; /* slow PCI settings */ 85 86/* 87 Possible default video modes: 800x600@60, 640x480@75, 1024x768@76, 640x480@60 88*/ 89#define DEFAULT_VIDEO_MODE "640x480@60" 90 91static char *mode_option __devinitdata = DEFAULT_VIDEO_MODE; 92 93enum { 94 ID_VOODOO1 = 0, 95 ID_VOODOO2 = 1, 96}; 97 98#define IS_VOODOO2(par) ((par)->type == ID_VOODOO2) 99 100static struct sst_spec voodoo_spec[] __devinitdata = { 101 { .name = "Voodoo Graphics", .default_gfx_clock = 50000, .max_gfxclk = 60 }, 102 { .name = "Voodoo2", .default_gfx_clock = 75000, .max_gfxclk = 85 }, 103}; 104 105 106/* 107 * debug functions 108 */ 109 110#if (SST_DEBUG_REG > 0) 111static void sst_dbg_print_read_reg(u32 reg, u32 val) { 112 const char *regname; 113 switch (reg) { 114 case FBIINIT0: regname = "FbiInit0"; break; 115 case FBIINIT1: regname = "FbiInit1"; break; 116 case FBIINIT2: regname = "FbiInit2"; break; 117 case FBIINIT3: regname = "FbiInit3"; break; 118 case FBIINIT4: regname = "FbiInit4"; break; 119 case FBIINIT5: regname = "FbiInit5"; break; 120 case FBIINIT6: regname = "FbiInit6"; break; 121 default: regname = NULL; break; 122 } 123 if (regname == NULL) 124 r_ddprintk("sst_read(%#x): %#x\n", reg, val); 125 else 126 r_dprintk(" sst_read(%s): %#x\n", regname, val); 127} 128 129static void sst_dbg_print_write_reg(u32 reg, u32 val) { 130 const char *regname; 131 switch (reg) { 132 case FBIINIT0: regname = "FbiInit0"; break; 133 case FBIINIT1: regname = "FbiInit1"; break; 134 case FBIINIT2: regname = "FbiInit2"; break; 135 case FBIINIT3: regname = "FbiInit3"; break; 136 case FBIINIT4: regname = "FbiInit4"; break; 137 case FBIINIT5: regname = "FbiInit5"; break; 138 case FBIINIT6: regname = "FbiInit6"; break; 139 default: regname = NULL; break; 140 } 141 if (regname == NULL) 142 r_ddprintk("sst_write(%#x, %#x)\n", reg, val); 143 else 144 r_dprintk(" sst_write(%s, %#x)\n", regname, val); 145} 146#else /* (SST_DEBUG_REG > 0) */ 147# define sst_dbg_print_read_reg(reg, val) do {} while(0) 148# define sst_dbg_print_write_reg(reg, val) do {} while(0) 149#endif /* (SST_DEBUG_REG > 0) */ 150 151/* 152 * hardware access functions 153 */ 154 155/* register access */ 156#define sst_read(reg) __sst_read(par->mmio_vbase, reg) 157#define sst_write(reg,val) __sst_write(par->mmio_vbase, reg, val) 158#define sst_set_bits(reg,val) __sst_set_bits(par->mmio_vbase, reg, val) 159#define sst_unset_bits(reg,val) __sst_unset_bits(par->mmio_vbase, reg, val) 160#define sst_dac_read(reg) __sst_dac_read(par->mmio_vbase, reg) 161#define sst_dac_write(reg,val) __sst_dac_write(par->mmio_vbase, reg, val) 162#define dac_i_read(reg) __dac_i_read(par->mmio_vbase, reg) 163#define dac_i_write(reg,val) __dac_i_write(par->mmio_vbase, reg, val) 164 165static inline u32 __sst_read(u8 __iomem *vbase, u32 reg) 166{ 167 u32 ret = readl(vbase + reg); 168 sst_dbg_print_read_reg(reg, ret); 169 return ret; 170} 171 172static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val) 173{ 174 sst_dbg_print_write_reg(reg, val); 175 writel(val, vbase + reg); 176} 177 178static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val) 179{ 180 r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val); 181 __sst_write(vbase, reg, __sst_read(vbase, reg) | val); 182} 183 184static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val) 185{ 186 r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val); 187 __sst_write(vbase, reg, __sst_read(vbase, reg) & ~val); 188} 189 190/* 191 * wait for the fbi chip. ASK: what happens if the fbi is stuck ? 192 * 193 * the FBI is supposed to be ready if we receive 5 time 194 * in a row a "idle" answer to our requests 195 */ 196 197#define sst_wait_idle() __sst_wait_idle(par->mmio_vbase) 198 199static int __sst_wait_idle(u8 __iomem *vbase) 200{ 201 int count = 0; 202 203 /* if (doFBINOP) __sst_write(vbase, NOPCMD, 0); */ 204 205 while(1) { 206 if (__sst_read(vbase, STATUS) & STATUS_FBI_BUSY) { 207 f_dddprintk("status: busy\n"); 208 count = 0; 209 } else { 210 count++; 211 f_dddprintk("status: idle(%d)\n", count); 212 } 213 if (count >= 5) return 1; 214 } 215} 216 217 218/* dac access */ 219/* dac_read should be remaped to FbiInit2 (via the pci reg init_enable) */ 220static u8 __sst_dac_read(u8 __iomem *vbase, u8 reg) 221{ 222 u8 ret; 223 224 reg &= 0x07; 225 __sst_write(vbase, DAC_DATA, ((u32)reg << 8) | DAC_READ_CMD ); 226 __sst_wait_idle(vbase); 227 /* udelay(10); */ 228 ret = __sst_read(vbase, DAC_READ) & 0xff; 229 r_dprintk("sst_dac_read(%#x): %#x\n", reg, ret); 230 231 return ret; 232} 233 234static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val) 235{ 236 r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val); 237 reg &= 0x07; 238 __sst_write(vbase, DAC_DATA,(((u32)reg << 8)) | (u32)val); 239 __sst_wait_idle(vbase); 240} 241 242/* indexed access to ti/att dacs */ 243static u32 __dac_i_read(u8 __iomem *vbase, u8 reg) 244{ 245 u32 ret; 246 247 __sst_dac_write(vbase, DACREG_ADDR_I, reg); 248 ret = __sst_dac_read(vbase, DACREG_DATA_I); 249 r_dprintk("sst_dac_read_i(%#x): %#x\n", reg, ret); 250 return ret; 251} 252static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val) 253{ 254 r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val); 255 __sst_dac_write(vbase, DACREG_ADDR_I, reg); 256 __sst_dac_write(vbase, DACREG_DATA_I, val); 257} 258 259/* compute the m,n,p , returns the real freq 260 * (ics datasheet : N <-> N1 , P <-> N2) 261 * 262 * Fout= Fref * (M+2)/( 2^P * (N+2)) 263 * we try to get close to the asked freq 264 * with P as high, and M as low as possible 265 * range: 266 * ti/att : 0 <= M <= 255; 0 <= P <= 3; 0<= N <= 63 267 * ics : 1 <= M <= 127; 0 <= P <= 3; 1<= N <= 31 268 * we'll use the lowest limitation, should be precise enouth 269 */ 270static int sst_calc_pll(const int freq, int *freq_out, struct pll_timing *t) 271{ 272 int m, m2, n, p, best_err, fout; 273 int best_n = -1; 274 int best_m = -1; 275 276 best_err = freq; 277 p = 3; 278 /* f * 2^P = vco should be less than VCOmax ~ 250 MHz for ics*/ 279 while (((1 << p) * freq > VCO_MAX) && (p >= 0)) 280 p--; 281 if (p == -1) 282 return -EINVAL; 283 for (n = 1; n < 32; n++) { 284 /* calc 2 * m so we can round it later*/ 285 m2 = (2 * freq * (1 << p) * (n + 2) ) / DAC_FREF - 4 ; 286 287 m = (m2 % 2 ) ? m2/2+1 : m2/2 ; 288 if (m >= 128) 289 break; 290 fout = (DAC_FREF * (m + 2)) / ((1 << p) * (n + 2)); 291 if ((abs(fout - freq) < best_err) && (m > 0)) { 292 best_n = n; 293 best_m = m; 294 best_err = abs(fout - freq); 295 /* we get the lowest m , allowing 0.5% error in freq*/ 296 if (200*best_err < freq) break; 297 } 298 } 299 if (best_n == -1) /* unlikely, but who knows ? */ 300 return -EINVAL; 301 t->p = p; 302 t->n = best_n; 303 t->m = best_m; 304 *freq_out = (DAC_FREF * (t->m + 2)) / ((1 << t->p) * (t->n + 2)); 305 f_ddprintk ("m: %d, n: %d, p: %d, F: %dKhz\n", 306 t->m, t->n, t->p, *freq_out); 307 return 0; 308} 309 310/* 311 * clear lfb screen 312 */ 313static void sstfb_clear_screen(struct fb_info *info) 314{ 315 /* clear screen */ 316 fb_memset(info->screen_base, 0, info->fix.smem_len); 317} 318 319 320/** 321 * sstfb_check_var - Optional function. Validates a var passed in. 322 * @var: frame buffer variable screen structure 323 * @info: frame buffer structure that represents a single frame buffer 324 * 325 * Limit to the abilities of a single chip as SLI is not supported 326 * by this driver. 327 */ 328 329static int sstfb_check_var(struct fb_var_screeninfo *var, 330 struct fb_info *info) 331{ 332 struct sstfb_par *par = info->par; 333 int hSyncOff = var->xres + var->right_margin + var->left_margin; 334 int vSyncOff = var->yres + var->lower_margin + var->upper_margin; 335 int vBackPorch = var->left_margin, yDim = var->yres; 336 int vSyncOn = var->vsync_len; 337 int tiles_in_X, real_length; 338 unsigned int freq; 339 340 if (sst_calc_pll(PICOS2KHZ(var->pixclock), &freq, &par->pll)) { 341 printk(KERN_ERR "sstfb: Pixclock at %ld KHZ out of range\n", 342 PICOS2KHZ(var->pixclock)); 343 return -EINVAL; 344 } 345 var->pixclock = KHZ2PICOS(freq); 346 347 if (var->vmode & FB_VMODE_INTERLACED) 348 vBackPorch += (vBackPorch % 2); 349 if (var->vmode & FB_VMODE_DOUBLE) { 350 vBackPorch <<= 1; 351 yDim <<=1; 352 vSyncOn <<=1; 353 vSyncOff <<=1; 354 } 355 356 switch (var->bits_per_pixel) { 357 case 0 ... 16 : 358 var->bits_per_pixel = 16; 359 break; 360 default : 361 printk(KERN_ERR "sstfb: Unsupported bpp %d\n", var->bits_per_pixel); 362 return -EINVAL; 363 } 364 365 /* validity tests */ 366 if (var->xres <= 1 || yDim <= 0 || var->hsync_len <= 1 || 367 hSyncOff <= 1 || var->left_margin <= 2 || vSyncOn <= 0 || 368 vSyncOff <= 0 || vBackPorch <= 0) { 369 return -EINVAL; 370 } 371 372 if (IS_VOODOO2(par)) { 373 /* Voodoo 2 limits */ 374 tiles_in_X = (var->xres + 63 ) / 64 * 2; 375 376 if (var->xres > POW2(11) || yDim >= POW2(11)) { 377 printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n", 378 var->xres, var->yres); 379 return -EINVAL; 380 } 381 382 if (var->hsync_len > POW2(9) || hSyncOff > POW2(11) || 383 var->left_margin - 2 >= POW2(9) || vSyncOn >= POW2(13) || 384 vSyncOff >= POW2(13) || vBackPorch >= POW2(9) || 385 tiles_in_X >= POW2(6) || tiles_in_X <= 0) { 386 printk(KERN_ERR "sstfb: Unsupported timings\n"); 387 return -EINVAL; 388 } 389 } else { 390 /* Voodoo limits */ 391 tiles_in_X = (var->xres + 63 ) / 64; 392 393 if (var->vmode) { 394 printk(KERN_ERR "sstfb: Interlace/doublescan not supported %#x\n", 395 var->vmode); 396 return -EINVAL; 397 } 398 if (var->xres > POW2(10) || var->yres >= POW2(10)) { 399 printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n", 400 var->xres, var->yres); 401 return -EINVAL; 402 } 403 if (var->hsync_len > POW2(8) || hSyncOff - 1 > POW2(10) || 404 var->left_margin - 2 >= POW2(8) || vSyncOn >= POW2(12) || 405 vSyncOff >= POW2(12) || vBackPorch >= POW2(8) || 406 tiles_in_X >= POW2(4) || tiles_in_X <= 0) { 407 printk(KERN_ERR "sstfb: Unsupported timings\n"); 408 return -EINVAL; 409 } 410 } 411 412 /* it seems that the fbi uses tiles of 64x16 pixels to "map" the mem */ 413 real_length = tiles_in_X * (IS_VOODOO2(par) ? 32 : 64 ) 414 * ((var->bits_per_pixel == 16) ? 2 : 4); 415 416 if (real_length * yDim > info->fix.smem_len) { 417 printk(KERN_ERR "sstfb: Not enough video memory\n"); 418 return -ENOMEM; 419 } 420 421 var->sync &= (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT); 422 var->vmode &= (FB_VMODE_INTERLACED | FB_VMODE_DOUBLE); 423 var->xoffset = 0; 424 var->yoffset = 0; 425 var->height = -1; 426 var->width = -1; 427 428 /* 429 * correct the color bit fields 430 */ 431 /* var->{red|green|blue}.msb_right = 0; */ 432 433 switch (var->bits_per_pixel) { 434 case 16: /* RGB 565 LfbMode 0 */ 435 var->red.length = 5; 436 var->green.length = 6; 437 var->blue.length = 5; 438 var->transp.length = 0; 439 440 var->red.offset = 11; 441 var->green.offset = 5; 442 var->blue.offset = 0; 443 var->transp.offset = 0; 444 break; 445 default: 446 return -EINVAL; 447 } 448 return 0; 449} 450 451/** 452 * sstfb_set_par - Optional function. Alters the hardware state. 453 * @info: frame buffer structure that represents a single frame buffer 454 */ 455static int sstfb_set_par(struct fb_info *info) 456{ 457 struct sstfb_par *par = info->par; 458 u32 lfbmode, fbiinit1, fbiinit2, fbiinit3, fbiinit5, fbiinit6=0; 459 struct pci_dev *sst_dev = par->dev; 460 unsigned int freq; 461 int ntiles; 462 463 par->hSyncOff = info->var.xres + info->var.right_margin + info->var.left_margin; 464 465 par->yDim = info->var.yres; 466 par->vSyncOn = info->var.vsync_len; 467 par->vSyncOff = info->var.yres + info->var.lower_margin + info->var.upper_margin; 468 par->vBackPorch = info->var.upper_margin; 469 470 /* We need par->pll */ 471 sst_calc_pll(PICOS2KHZ(info->var.pixclock), &freq, &par->pll); 472 473 if (info->var.vmode & FB_VMODE_INTERLACED) 474 par->vBackPorch += (par->vBackPorch % 2); 475 if (info->var.vmode & FB_VMODE_DOUBLE) { 476 par->vBackPorch <<= 1; 477 par->yDim <<=1; 478 par->vSyncOn <<=1; 479 par->vSyncOff <<=1; 480 } 481 482 if (IS_VOODOO2(par)) { 483 /* voodoo2 has 32 pixel wide tiles , BUT stange things 484 happen with odd number of tiles */ 485 par->tiles_in_X = (info->var.xres + 63 ) / 64 * 2; 486 } else { 487 /* voodoo1 has 64 pixels wide tiles. */ 488 par->tiles_in_X = (info->var.xres + 63 ) / 64; 489 } 490 491 f_ddprintk("hsync_len hSyncOff vsync_len vSyncOff\n"); 492 f_ddprintk("%-7d %-8d %-7d %-8d\n", 493 info->var.hsync_len, par->hSyncOff, 494 par->vSyncOn, par->vSyncOff); 495 f_ddprintk("left_margin upper_margin xres yres Freq\n"); 496 f_ddprintk("%-10d %-10d %-4d %-4d %-8ld\n", 497 info->var.left_margin, info->var.upper_margin, 498 info->var.xres, info->var.yres, PICOS2KHZ(info->var.pixclock)); 499 500 sst_write(NOPCMD, 0); 501 sst_wait_idle(); 502 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR); 503 sst_set_bits(FBIINIT1, VIDEO_RESET); 504 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET); 505 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH); 506 sst_wait_idle(); 507 508 /*sst_unset_bits (FBIINIT0, FBI_RESET); / reenable FBI ? */ 509 510 sst_write(BACKPORCH, par->vBackPorch << 16 | (info->var.left_margin - 2)); 511 sst_write(VIDEODIMENSIONS, par->yDim << 16 | (info->var.xres - 1)); 512 sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1)); 513 sst_write(VSYNC, par->vSyncOff << 16 | par->vSyncOn); 514 515 fbiinit2 = sst_read(FBIINIT2); 516 fbiinit3 = sst_read(FBIINIT3); 517 518 /* everything is reset. we enable fbiinit2/3 remap : dac acces ok */ 519 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, 520 PCI_EN_INIT_WR | PCI_REMAP_DAC ); 521 522 par->dac_sw.set_vidmod(info, info->var.bits_per_pixel); 523 524 /* set video clock */ 525 par->dac_sw.set_pll(info, &par->pll, VID_CLOCK); 526 527 /* disable fbiinit2/3 remap */ 528 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, 529 PCI_EN_INIT_WR); 530 531 /* restore fbiinit2/3 */ 532 sst_write(FBIINIT2,fbiinit2); 533 sst_write(FBIINIT3,fbiinit3); 534 535 fbiinit1 = (sst_read(FBIINIT1) & VIDEO_MASK) 536 | EN_DATA_OE 537 | EN_BLANK_OE 538 | EN_HVSYNC_OE 539 | EN_DCLK_OE 540 /* | (15 << TILES_IN_X_SHIFT) */ 541 | SEL_INPUT_VCLK_2X 542 /* | (2 << VCLK_2X_SEL_DEL_SHIFT) 543 | (2 << VCLK_DEL_SHIFT) */; 544 545 ntiles = par->tiles_in_X; 546 if (IS_VOODOO2(par)) { 547 fbiinit1 |= ((ntiles & 0x20) >> 5) << TILES_IN_X_MSB_SHIFT 548 | ((ntiles & 0x1e) >> 1) << TILES_IN_X_SHIFT; 549/* as the only value of importance for us in fbiinit6 is tiles in X (lsb), 550 and as reading fbinit 6 will return crap (see FBIINIT6_DEFAULT) we just 551 write our value. BTW due to the dac unable to read odd number of tiles, this 552 field is always null ... */ 553 fbiinit6 = (ntiles & 0x1) << TILES_IN_X_LSB_SHIFT; 554 } 555 else 556 fbiinit1 |= ntiles << TILES_IN_X_SHIFT; 557 558 switch (info->var.bits_per_pixel) { 559 case 16: 560 fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL; 561 break; 562 default: 563 return -EINVAL; 564 } 565 sst_write(FBIINIT1, fbiinit1); 566 if (IS_VOODOO2(par)) { 567 sst_write(FBIINIT6, fbiinit6); 568 fbiinit5=sst_read(FBIINIT5) & FBIINIT5_MASK ; 569 if (info->var.vmode & FB_VMODE_INTERLACED) 570 fbiinit5 |= INTERLACE; 571 if (info->var.vmode & FB_VMODE_DOUBLE) 572 fbiinit5 |= VDOUBLESCAN; 573 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 574 fbiinit5 |= HSYNC_HIGH; 575 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 576 fbiinit5 |= VSYNC_HIGH; 577 sst_write(FBIINIT5, fbiinit5); 578 } 579 sst_wait_idle(); 580 sst_unset_bits(FBIINIT1, VIDEO_RESET); 581 sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET); 582 sst_set_bits(FBIINIT2, EN_DRAM_REFRESH); 583 /* disables fbiinit writes */ 584 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR); 585 586 /* set lfbmode : set mode + front buffer for reads/writes 587 + disable pipeline */ 588 switch (info->var.bits_per_pixel) { 589 case 16: 590 lfbmode = LFB_565; 591 break; 592 default: 593 return -EINVAL; 594 } 595 596#if defined(__BIG_ENDIAN) 597 /* Enable byte-swizzle functionality in hardware. 598 * With this enabled, all our read- and write-accesses to 599 * the voodoo framebuffer can be done in native format, and 600 * the hardware will automatically convert it to little-endian. 601 * - tested on HP-PARISC, Helge Deller <deller@gmx.de> */ 602 lfbmode |= ( LFB_WORD_SWIZZLE_WR | LFB_BYTE_SWIZZLE_WR | 603 LFB_WORD_SWIZZLE_RD | LFB_BYTE_SWIZZLE_RD ); 604#endif 605 606 if (clipping) { 607 sst_write(LFBMODE, lfbmode | EN_PXL_PIPELINE); 608 /* 609 * Set "clipping" dimensions. If clipping is disabled and 610 * writes to offscreen areas of the framebuffer are performed, 611 * the "behaviour is undefined" (_very_ undefined) - Urs 612 */ 613 /* btw, it requires enabling pixel pipeline in LFBMODE . 614 off screen read/writes will just wrap and read/print pixels 615 on screen. Ugly but not that dangerous */ 616 f_ddprintk("setting clipping dimensions 0..%d, 0..%d\n", 617 info->var.xres - 1, par->yDim - 1); 618 619 sst_write(CLIP_LEFT_RIGHT, info->var.xres); 620 sst_write(CLIP_LOWY_HIGHY, par->yDim); 621 sst_set_bits(FBZMODE, EN_CLIPPING | EN_RGB_WRITE); 622 } else { 623 /* no clipping : direct access, no pipeline */ 624 sst_write(LFBMODE, lfbmode); 625 } 626 return 0; 627} 628 629/** 630 * sstfb_setcolreg - Optional function. Sets a color register. 631 * @regno: hardware colormap register 632 * @red: frame buffer colormap structure 633 * @green: The green value which can be up to 16 bits wide 634 * @blue: The blue value which can be up to 16 bits wide. 635 * @transp: If supported the alpha value which can be up to 16 bits wide. 636 * @info: frame buffer info structure 637 */ 638static int sstfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 639 u_int transp, struct fb_info *info) 640{ 641 struct sstfb_par *par = info->par; 642 u32 col; 643 644 f_dddprintk("sstfb_setcolreg\n"); 645 f_dddprintk("%-2d rgbt: %#x, %#x, %#x, %#x\n", 646 regno, red, green, blue, transp); 647 if (regno > 15) 648 return 0; 649 650 red >>= (16 - info->var.red.length); 651 green >>= (16 - info->var.green.length); 652 blue >>= (16 - info->var.blue.length); 653 transp >>= (16 - info->var.transp.length); 654 col = (red << info->var.red.offset) 655 | (green << info->var.green.offset) 656 | (blue << info->var.blue.offset) 657 | (transp << info->var.transp.offset); 658 659 par->palette[regno] = col; 660 661 return 0; 662} 663 664static void sstfb_setvgapass( struct fb_info *info, int enable ) 665{ 666 struct sstfb_par *par = info->par; 667 struct pci_dev *sst_dev = par->dev; 668 u32 fbiinit0, tmp; 669 670 enable = enable ? 1:0; 671 if (par->vgapass == enable) 672 return; 673 par->vgapass = enable; 674 675 pci_read_config_dword(sst_dev, PCI_INIT_ENABLE, &tmp); 676 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, 677 tmp | PCI_EN_INIT_WR ); 678 fbiinit0 = sst_read (FBIINIT0); 679 if (par->vgapass) { 680 sst_write(FBIINIT0, fbiinit0 & ~DIS_VGA_PASSTHROUGH); 681 printk(KERN_INFO "fb%d: Enabling VGA pass-through\n", info->node ); 682 } else { 683 sst_write(FBIINIT0, fbiinit0 | DIS_VGA_PASSTHROUGH); 684 printk(KERN_INFO "fb%d: Disabling VGA pass-through\n", info->node ); 685 } 686 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, tmp); 687} 688 689static ssize_t store_vgapass(struct device *device, struct device_attribute *attr, 690 const char *buf, size_t count) 691{ 692 struct fb_info *info = dev_get_drvdata(device); 693 char ** last = NULL; 694 int val; 695 696 val = simple_strtoul(buf, last, 0); 697 sstfb_setvgapass(info, val); 698 699 return count; 700} 701 702static ssize_t show_vgapass(struct device *device, struct device_attribute *attr, 703 char *buf) 704{ 705 struct fb_info *info = dev_get_drvdata(device); 706 struct sstfb_par *par = info->par; 707 return snprintf(buf, PAGE_SIZE, "%d\n", par->vgapass); 708} 709 710static struct device_attribute device_attrs[] = { 711 __ATTR(vgapass, S_IRUGO|S_IWUSR, show_vgapass, store_vgapass) 712 }; 713 714static int sstfb_ioctl(struct fb_info *info, unsigned int cmd, 715 unsigned long arg) 716{ 717 struct sstfb_par *par; 718 u32 val; 719 720 switch (cmd) { 721 /* set/get VGA pass_through mode */ 722 case SSTFB_SET_VGAPASS: 723 if (copy_from_user(&val, (void __user *)arg, sizeof(val))) 724 return -EFAULT; 725 sstfb_setvgapass(info, val); 726 return 0; 727 case SSTFB_GET_VGAPASS: 728 par = info->par; 729 val = par->vgapass; 730 if (copy_to_user((void __user *)arg, &val, sizeof(val))) 731 return -EFAULT; 732 return 0; 733 } 734 735 return -EINVAL; 736} 737 738 739/* 740 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) - Voodoo2 only 741 */ 742 743 744/* 745 * FillRect 2D command (solidfill or invert (via ROP_XOR)) - Voodoo2 only 746 */ 747 748 749 750/* 751 * get lfb size 752 */ 753static int __devinit sst_get_memsize(struct fb_info *info, __u32 *memsize) 754{ 755 u8 __iomem *fbbase_virt = info->screen_base; 756 757 /* force memsize */ 758 if (mem >= 1 && mem <= 4) { 759 *memsize = (mem * 0x100000); 760 printk(KERN_INFO "supplied memsize: %#x\n", *memsize); 761 return 1; 762 } 763 764 writel(0xdeadbeef, fbbase_virt); 765 writel(0xdeadbeef, fbbase_virt+0x100000); 766 writel(0xdeadbeef, fbbase_virt+0x200000); 767 f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n", 768 readl(fbbase_virt), readl(fbbase_virt + 0x100000), 769 readl(fbbase_virt + 0x200000)); 770 771 writel(0xabcdef01, fbbase_virt); 772 773 f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n", 774 readl(fbbase_virt), readl(fbbase_virt + 0x100000), 775 readl(fbbase_virt + 0x200000)); 776 777 /* checks for 4mb lfb, then 2, then defaults to 1 */ 778 if (readl(fbbase_virt + 0x200000) == 0xdeadbeef) 779 *memsize = 0x400000; 780 else if (readl(fbbase_virt + 0x100000) == 0xdeadbeef) 781 *memsize = 0x200000; 782 else 783 *memsize = 0x100000; 784 f_ddprintk("detected memsize: %dMB\n", *memsize >> 20); 785 return 1; 786} 787 788 789/* 790 * DAC detection routines 791 */ 792 793/* fbi should be idle, and fifo emty and mem disabled */ 794/* supposed to detect AT&T ATT20C409 and Ti TVP3409 ramdacs */ 795 796static int __devinit sst_detect_att(struct fb_info *info) 797{ 798 struct sstfb_par *par = info->par; 799 int i, mir, dir; 800 801 for (i = 0; i < 3; i++) { 802 sst_dac_write(DACREG_WMA, 0); /* backdoor */ 803 sst_dac_read(DACREG_RMR); /* read 4 times RMR */ 804 sst_dac_read(DACREG_RMR); 805 sst_dac_read(DACREG_RMR); 806 sst_dac_read(DACREG_RMR); 807 /* the fifth time, CR0 is read */ 808 sst_dac_read(DACREG_RMR); 809 /* the 6th, manufacturer id register */ 810 mir = sst_dac_read(DACREG_RMR); 811 /*the 7th, device ID register */ 812 dir = sst_dac_read(DACREG_RMR); 813 f_ddprintk("mir: %#x, dir: %#x\n", mir, dir); 814 if (mir == DACREG_MIR_ATT && dir == DACREG_DIR_ATT) { 815 return 1; 816 } 817 } 818 return 0; 819} 820 821static int __devinit sst_detect_ti(struct fb_info *info) 822{ 823 struct sstfb_par *par = info->par; 824 int i, mir, dir; 825 826 for (i = 0; i<3; i++) { 827 sst_dac_write(DACREG_WMA, 0); /* backdoor */ 828 sst_dac_read(DACREG_RMR); /* read 4 times RMR */ 829 sst_dac_read(DACREG_RMR); 830 sst_dac_read(DACREG_RMR); 831 sst_dac_read(DACREG_RMR); 832 /* the fifth time, CR0 is read */ 833 sst_dac_read(DACREG_RMR); 834 /* the 6th, manufacturer id register */ 835 mir = sst_dac_read(DACREG_RMR); 836 /*the 7th, device ID register */ 837 dir = sst_dac_read(DACREG_RMR); 838 f_ddprintk("mir: %#x, dir: %#x\n", mir, dir); 839 if ((mir == DACREG_MIR_TI ) && (dir == DACREG_DIR_TI)) { 840 return 1; 841 } 842 } 843 return 0; 844} 845 846/* 847 * try to detect ICS5342 ramdac 848 * we get the 1st byte (M value) of preset f1,f7 and fB 849 * why those 3 ? mmmh... for now, i'll do it the glide way... 850 * and ask questions later. anyway, it seems that all the freq registers are 851 * realy at their default state (cf specs) so i ask again, why those 3 regs ? 852 * mmmmh.. it seems that's much more ugly than i thought. we use f0 and fA for 853 * pll programming, so in fact, we *hope* that the f1, f7 & fB won't be 854 * touched... 855 * is it realy safe ? how can i reset this ramdac ? geee... 856 */ 857static int __devinit sst_detect_ics(struct fb_info *info) 858{ 859 struct sstfb_par *par = info->par; 860 int m_clk0_1, m_clk0_7, m_clk1_b; 861 int n_clk0_1, n_clk0_7, n_clk1_b; 862 int i; 863 864 for (i = 0; i<5; i++ ) { 865 sst_dac_write(DACREG_ICS_PLLRMA, 0x1); /* f1 */ 866 m_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA); 867 n_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA); 868 sst_dac_write(DACREG_ICS_PLLRMA, 0x7); /* f7 */ 869 m_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA); 870 n_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA); 871 sst_dac_write(DACREG_ICS_PLLRMA, 0xb); /* fB */ 872 m_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA); 873 n_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA); 874 f_ddprintk("m_clk0_1: %#x, m_clk0_7: %#x, m_clk1_b: %#x\n", 875 m_clk0_1, m_clk0_7, m_clk1_b); 876 f_ddprintk("n_clk0_1: %#x, n_clk0_7: %#x, n_clk1_b: %#x\n", 877 n_clk0_1, n_clk0_7, n_clk1_b); 878 if (( m_clk0_1 == DACREG_ICS_PLL_CLK0_1_INI) 879 && (m_clk0_7 == DACREG_ICS_PLL_CLK0_7_INI) 880 && (m_clk1_b == DACREG_ICS_PLL_CLK1_B_INI)) { 881 return 1; 882 } 883 } 884 return 0; 885} 886 887 888/* 889 * gfx, video, pci fifo should be reset, dram refresh disabled 890 * see detect_dac 891 */ 892 893static int sst_set_pll_att_ti(struct fb_info *info, 894 const struct pll_timing *t, const int clock) 895{ 896 struct sstfb_par *par = info->par; 897 u8 cr0, cc; 898 899 /* enable indexed mode */ 900 sst_dac_write(DACREG_WMA, 0); /* backdoor */ 901 sst_dac_read(DACREG_RMR); /* 1 time: RMR */ 902 sst_dac_read(DACREG_RMR); /* 2 RMR */ 903 sst_dac_read(DACREG_RMR); /* 3 // */ 904 sst_dac_read(DACREG_RMR); /* 4 // */ 905 cr0 = sst_dac_read(DACREG_RMR); /* 5 CR0 */ 906 907 sst_dac_write(DACREG_WMA, 0); 908 sst_dac_read(DACREG_RMR); 909 sst_dac_read(DACREG_RMR); 910 sst_dac_read(DACREG_RMR); 911 sst_dac_read(DACREG_RMR); 912 sst_dac_write(DACREG_RMR, (cr0 & 0xf0) 913 | DACREG_CR0_EN_INDEXED 914 | DACREG_CR0_8BIT 915 | DACREG_CR0_PWDOWN ); 916 /* so, now we are in indexed mode . dunno if its common, but 917 i find this way of doing things a little bit weird :p */ 918 919 udelay(300); 920 cc = dac_i_read(DACREG_CC_I); 921 switch (clock) { 922 case VID_CLOCK: 923 dac_i_write(DACREG_AC0_I, t->m); 924 dac_i_write(DACREG_AC1_I, t->p << 6 | t->n); 925 dac_i_write(DACREG_CC_I, 926 (cc & 0x0f) | DACREG_CC_CLKA | DACREG_CC_CLKA_C); 927 break; 928 case GFX_CLOCK: 929 dac_i_write(DACREG_BD0_I, t->m); 930 dac_i_write(DACREG_BD1_I, t->p << 6 | t->n); 931 dac_i_write(DACREG_CC_I, 932 (cc & 0xf0) | DACREG_CC_CLKB | DACREG_CC_CLKB_D); 933 break; 934 default: 935 dprintk("%s: wrong clock code '%d'\n", 936 __func__, clock); 937 return 0; 938 } 939 udelay(300); 940 941 /* power up the dac & return to "normal" non-indexed mode */ 942 dac_i_write(DACREG_CR0_I, 943 cr0 & ~DACREG_CR0_PWDOWN & ~DACREG_CR0_EN_INDEXED); 944 return 1; 945} 946 947static int sst_set_pll_ics(struct fb_info *info, 948 const struct pll_timing *t, const int clock) 949{ 950 struct sstfb_par *par = info->par; 951 u8 pll_ctrl; 952 953 sst_dac_write(DACREG_ICS_PLLRMA, DACREG_ICS_PLL_CTRL); 954 pll_ctrl = sst_dac_read(DACREG_ICS_PLLDATA); 955 switch(clock) { 956 case VID_CLOCK: 957 sst_dac_write(DACREG_ICS_PLLWMA, 0x0); /* CLK0, f0 */ 958 sst_dac_write(DACREG_ICS_PLLDATA, t->m); 959 sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n); 960 /* selects freq f0 for clock 0 */ 961 sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL); 962 sst_dac_write(DACREG_ICS_PLLDATA, 963 (pll_ctrl & 0xd8) 964 | DACREG_ICS_CLK0 965 | DACREG_ICS_CLK0_0); 966 break; 967 case GFX_CLOCK : 968 sst_dac_write(DACREG_ICS_PLLWMA, 0xa); /* CLK1, fA */ 969 sst_dac_write(DACREG_ICS_PLLDATA, t->m); 970 sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n); 971 /* selects freq fA for clock 1 */ 972 sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL); 973 sst_dac_write(DACREG_ICS_PLLDATA, 974 (pll_ctrl & 0xef) | DACREG_ICS_CLK1_A); 975 break; 976 default: 977 dprintk("%s: wrong clock code '%d'\n", 978 __func__, clock); 979 return 0; 980 } 981 udelay(300); 982 return 1; 983} 984 985static void sst_set_vidmod_att_ti(struct fb_info *info, const int bpp) 986{ 987 struct sstfb_par *par = info->par; 988 u8 cr0; 989 990 sst_dac_write(DACREG_WMA, 0); /* backdoor */ 991 sst_dac_read(DACREG_RMR); /* read 4 times RMR */ 992 sst_dac_read(DACREG_RMR); 993 sst_dac_read(DACREG_RMR); 994 sst_dac_read(DACREG_RMR); 995 /* the fifth time, CR0 is read */ 996 cr0 = sst_dac_read(DACREG_RMR); 997 998 sst_dac_write(DACREG_WMA, 0); /* backdoor */ 999 sst_dac_read(DACREG_RMR); /* read 4 times RMR */ 1000 sst_dac_read(DACREG_RMR); 1001 sst_dac_read(DACREG_RMR); 1002 sst_dac_read(DACREG_RMR); 1003 /* cr0 */ 1004 switch(bpp) { 1005 case 16: 1006 sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP); 1007 break; 1008 default: 1009 dprintk("%s: bad depth '%u'\n", __func__, bpp); 1010 break; 1011 } 1012} 1013 1014static void sst_set_vidmod_ics(struct fb_info *info, const int bpp) 1015{ 1016 struct sstfb_par *par = info->par; 1017 1018 switch(bpp) { 1019 case 16: 1020 sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_16BPP); 1021 break; 1022 default: 1023 dprintk("%s: bad depth '%u'\n", __func__, bpp); 1024 break; 1025 } 1026} 1027 1028/* 1029 * detect dac type 1030 * prerequisite : write to FbiInitx enabled, video and fbi and pci fifo reset, 1031 * dram refresh disabled, FbiInit remaped. 1032 * TODO: mmh.. maybe i should put the "prerequisite" in the func ... 1033 */ 1034 1035 1036static struct dac_switch dacs[] __devinitdata = { 1037 { .name = "TI TVP3409", 1038 .detect = sst_detect_ti, 1039 .set_pll = sst_set_pll_att_ti, 1040 .set_vidmod = sst_set_vidmod_att_ti }, 1041 1042 { .name = "AT&T ATT20C409", 1043 .detect = sst_detect_att, 1044 .set_pll = sst_set_pll_att_ti, 1045 .set_vidmod = sst_set_vidmod_att_ti }, 1046 { .name = "ICS ICS5342", 1047 .detect = sst_detect_ics, 1048 .set_pll = sst_set_pll_ics, 1049 .set_vidmod = sst_set_vidmod_ics }, 1050}; 1051 1052static int __devinit sst_detect_dactype(struct fb_info *info, struct sstfb_par *par) 1053{ 1054 int i, ret = 0; 1055 1056 for (i = 0; i < ARRAY_SIZE(dacs); i++) { 1057 ret = dacs[i].detect(info); 1058 if (ret) 1059 break; 1060 } 1061 if (!ret) 1062 return 0; 1063 f_dprintk("%s found %s\n", __func__, dacs[i].name); 1064 par->dac_sw = dacs[i]; 1065 return 1; 1066} 1067 1068/* 1069 * Internal Routines 1070 */ 1071static int __devinit sst_init(struct fb_info *info, struct sstfb_par *par) 1072{ 1073 u32 fbiinit0, fbiinit1, fbiinit4; 1074 struct pci_dev *dev = par->dev; 1075 struct pll_timing gfx_timings; 1076 struct sst_spec *spec; 1077 int Fout; 1078 int gfx_clock; 1079 1080 spec = &voodoo_spec[par->type]; 1081 f_ddprintk(" fbiinit0 fbiinit1 fbiinit2 fbiinit3 fbiinit4 " 1082 " fbiinit6\n"); 1083 f_ddprintk("%0#10x %0#10x %0#10x %0#10x %0#10x %0#10x\n", 1084 sst_read(FBIINIT0), sst_read(FBIINIT1), sst_read(FBIINIT2), 1085 sst_read(FBIINIT3), sst_read(FBIINIT4), sst_read(FBIINIT6)); 1086 /* disable video clock */ 1087 pci_write_config_dword(dev, PCI_VCLK_DISABLE, 0); 1088 1089 /* enable writing to init registers, disable pci fifo */ 1090 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR); 1091 /* reset video */ 1092 sst_set_bits(FBIINIT1, VIDEO_RESET); 1093 sst_wait_idle(); 1094 /* reset gfx + pci fifo */ 1095 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET); 1096 sst_wait_idle(); 1097 1098 /* unreset fifo */ 1099 /*sst_unset_bits(FBIINIT0, FIFO_RESET); 1100 sst_wait_idle();*/ 1101 /* unreset FBI */ 1102 /*sst_unset_bits(FBIINIT0, FBI_RESET); 1103 sst_wait_idle();*/ 1104 1105 /* disable dram refresh */ 1106 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH); 1107 sst_wait_idle(); 1108 /* remap fbinit2/3 to dac */ 1109 pci_write_config_dword(dev, PCI_INIT_ENABLE, 1110 PCI_EN_INIT_WR | PCI_REMAP_DAC ); 1111 /* detect dac type */ 1112 if (!sst_detect_dactype(info, par)) { 1113 printk(KERN_ERR "sstfb: unknown dac type.\n"); 1114 return 0; 1115 } 1116 1117 /* set graphic clock */ 1118 gfx_clock = spec->default_gfx_clock; 1119 if ((gfxclk >10 ) && (gfxclk < spec->max_gfxclk)) { 1120 printk(KERN_INFO "sstfb: Using supplied graphic freq : %dMHz\n", gfxclk); 1121 gfx_clock = gfxclk *1000; 1122 } else if (gfxclk) { 1123 printk(KERN_WARNING "sstfb: %dMhz is way out of spec! Using default\n", gfxclk); 1124 } 1125 1126 sst_calc_pll(gfx_clock, &Fout, &gfx_timings); 1127 par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK); 1128 1129 /* disable fbiinit remap */ 1130 pci_write_config_dword(dev, PCI_INIT_ENABLE, 1131 PCI_EN_INIT_WR| PCI_EN_FIFO_WR ); 1132 /* defaults init registers */ 1133 /* FbiInit0: unreset gfx, unreset fifo */ 1134 fbiinit0 = FBIINIT0_DEFAULT; 1135 fbiinit1 = FBIINIT1_DEFAULT; 1136 fbiinit4 = FBIINIT4_DEFAULT; 1137 par->vgapass = vgapass; 1138 if (par->vgapass) 1139 fbiinit0 &= ~DIS_VGA_PASSTHROUGH; 1140 else 1141 fbiinit0 |= DIS_VGA_PASSTHROUGH; 1142 if (slowpci) { 1143 fbiinit1 |= SLOW_PCI_WRITES; 1144 fbiinit4 |= SLOW_PCI_READS; 1145 } else { 1146 fbiinit1 &= ~SLOW_PCI_WRITES; 1147 fbiinit4 &= ~SLOW_PCI_READS; 1148 } 1149 sst_write(FBIINIT0, fbiinit0); 1150 sst_wait_idle(); 1151 sst_write(FBIINIT1, fbiinit1); 1152 sst_wait_idle(); 1153 sst_write(FBIINIT2, FBIINIT2_DEFAULT); 1154 sst_wait_idle(); 1155 sst_write(FBIINIT3, FBIINIT3_DEFAULT); 1156 sst_wait_idle(); 1157 sst_write(FBIINIT4, fbiinit4); 1158 sst_wait_idle(); 1159 if (IS_VOODOO2(par)) { 1160 sst_write(FBIINIT6, FBIINIT6_DEFAULT); 1161 sst_wait_idle(); 1162 } 1163 1164 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR); 1165 pci_write_config_dword(dev, PCI_VCLK_ENABLE, 0); 1166 return 1; 1167} 1168 1169static void __devexit sst_shutdown(struct fb_info *info) 1170{ 1171 struct sstfb_par *par = info->par; 1172 struct pci_dev *dev = par->dev; 1173 struct pll_timing gfx_timings; 1174 int Fout; 1175 1176 /* reset video, gfx, fifo, disable dram + remap fbiinit2/3 */ 1177 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR); 1178 sst_set_bits(FBIINIT1, VIDEO_RESET | EN_BLANKING); 1179 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH); 1180 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET); 1181 sst_wait_idle(); 1182 pci_write_config_dword(dev, PCI_INIT_ENABLE, 1183 PCI_EN_INIT_WR | PCI_REMAP_DAC); 1184 /* set 20Mhz gfx clock */ 1185 sst_calc_pll(20000, &Fout, &gfx_timings); 1186 par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK); 1187 /* TODO maybe shutdown the dac, vrefresh and so on... */ 1188 pci_write_config_dword(dev, PCI_INIT_ENABLE, 1189 PCI_EN_INIT_WR); 1190 sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET | DIS_VGA_PASSTHROUGH); 1191 pci_write_config_dword(dev, PCI_VCLK_DISABLE,0); 1192 /* maybe keep fbiinit* and PCI_INIT_enable in the fb_info struct 1193 * from start ? */ 1194 pci_write_config_dword(dev, PCI_INIT_ENABLE, 0); 1195 1196} 1197 1198/* 1199 * Interface to the world 1200 */ 1201static int __devinit sstfb_setup(char *options) 1202{ 1203 char *this_opt; 1204 1205 if (!options || !*options) 1206 return 0; 1207 1208 while ((this_opt = strsep(&options, ",")) != NULL) { 1209 if (!*this_opt) continue; 1210 1211 f_ddprintk("option %s\n", this_opt); 1212 1213 if (!strcmp(this_opt, "vganopass")) 1214 vgapass = 0; 1215 else if (!strcmp(this_opt, "vgapass")) 1216 vgapass = 1; 1217 else if (!strcmp(this_opt, "clipping")) 1218 clipping = 1; 1219 else if (!strcmp(this_opt, "noclipping")) 1220 clipping = 0; 1221 else if (!strcmp(this_opt, "fastpci")) 1222 slowpci = 0; 1223 else if (!strcmp(this_opt, "slowpci")) 1224 slowpci = 1; 1225 else if (!strncmp(this_opt, "mem:",4)) 1226 mem = simple_strtoul (this_opt+4, NULL, 0); 1227 else if (!strncmp(this_opt, "gfxclk:",7)) 1228 gfxclk = simple_strtoul (this_opt+7, NULL, 0); 1229 else 1230 mode_option = this_opt; 1231 } 1232 return 0; 1233} 1234 1235 1236static struct fb_ops sstfb_ops = { 1237 .owner = THIS_MODULE, 1238 .fb_check_var = sstfb_check_var, 1239 .fb_set_par = sstfb_set_par, 1240 .fb_setcolreg = sstfb_setcolreg, 1241 .fb_fillrect = cfb_fillrect, /* sstfb_fillrect */ 1242 .fb_copyarea = cfb_copyarea, /* sstfb_copyarea */ 1243 .fb_imageblit = cfb_imageblit, 1244 .fb_ioctl = sstfb_ioctl, 1245}; 1246 1247static int __devinit sstfb_probe(struct pci_dev *pdev, 1248 const struct pci_device_id *id) 1249{ 1250 struct fb_info *info; 1251 struct fb_fix_screeninfo *fix; 1252 struct sstfb_par *par; 1253 struct sst_spec *spec; 1254 int err; 1255 1256 /* Enable device in PCI config. */ 1257 if ((err=pci_enable_device(pdev))) { 1258 printk(KERN_ERR "cannot enable device\n"); 1259 return err; 1260 } 1261 1262 /* Allocate the fb and par structures. */ 1263 info = framebuffer_alloc(sizeof(struct sstfb_par), &pdev->dev); 1264 if (!info) 1265 return -ENOMEM; 1266 1267 pci_set_drvdata(pdev, info); 1268 1269 par = info->par; 1270 fix = &info->fix; 1271 1272 par->type = id->driver_data; 1273 spec = &voodoo_spec[par->type]; 1274 f_ddprintk("found device : %s\n", spec->name); 1275 1276 par->dev = pdev; 1277 par->revision = pdev->revision; 1278 1279 fix->mmio_start = pci_resource_start(pdev,0); 1280 fix->mmio_len = 0x400000; 1281 fix->smem_start = fix->mmio_start + 0x400000; 1282 1283 if (!request_mem_region(fix->mmio_start, fix->mmio_len, "sstfb MMIO")) { 1284 printk(KERN_ERR "sstfb: cannot reserve mmio memory\n"); 1285 goto fail_mmio_mem; 1286 } 1287 1288 if (!request_mem_region(fix->smem_start, 0x400000,"sstfb FB")) { 1289 printk(KERN_ERR "sstfb: cannot reserve fb memory\n"); 1290 goto fail_fb_mem; 1291 } 1292 1293 par->mmio_vbase = ioremap_nocache(fix->mmio_start, 1294 fix->mmio_len); 1295 if (!par->mmio_vbase) { 1296 printk(KERN_ERR "sstfb: cannot remap register area %#lx\n", 1297 fix->mmio_start); 1298 goto fail_mmio_remap; 1299 } 1300 info->screen_base = ioremap_nocache(fix->smem_start, 0x400000); 1301 if (!info->screen_base) { 1302 printk(KERN_ERR "sstfb: cannot remap framebuffer %#lx\n", 1303 fix->smem_start); 1304 goto fail_fb_remap; 1305 } 1306 1307 if (!sst_init(info, par)) { 1308 printk(KERN_ERR "sstfb: Init failed\n"); 1309 goto fail; 1310 } 1311 sst_get_memsize(info, &fix->smem_len); 1312 strlcpy(fix->id, spec->name, sizeof(fix->id)); 1313 1314 printk(KERN_INFO "%s (revision %d) with %s dac\n", 1315 fix->id, par->revision, par->dac_sw.name); 1316 printk(KERN_INFO "framebuffer at %#lx, mapped to 0x%p, size %dMB\n", 1317 fix->smem_start, info->screen_base, 1318 fix->smem_len >> 20); 1319 1320 f_ddprintk("regbase_virt: %#lx\n", par->mmio_vbase); 1321 f_ddprintk("membase_phys: %#lx\n", fix->smem_start); 1322 f_ddprintk("fbbase_virt: %p\n", info->screen_base); 1323 1324 info->flags = FBINFO_DEFAULT; 1325 info->fbops = &sstfb_ops; 1326 info->pseudo_palette = par->palette; 1327 1328 fix->type = FB_TYPE_PACKED_PIXELS; 1329 fix->visual = FB_VISUAL_TRUECOLOR; 1330 fix->accel = FB_ACCEL_NONE; 1331 /* 1332 * According to the specs, the linelength must be of 1024 *pixels* 1333 * and the 24bpp mode is in fact a 32 bpp mode (and both are in 1334 * fact dithered to 16bit). 1335 */ 1336 fix->line_length = 2048; /* default value, for 24 or 32bit: 4096 */ 1337 1338 fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 16); 1339 1340 if (sstfb_check_var(&info->var, info)) { 1341 printk(KERN_ERR "sstfb: invalid video mode.\n"); 1342 goto fail; 1343 } 1344 1345 if (sstfb_set_par(info)) { 1346 printk(KERN_ERR "sstfb: can't set default video mode.\n"); 1347 goto fail; 1348 } 1349 1350 if (fb_alloc_cmap(&info->cmap, 256, 0)) { 1351 printk(KERN_ERR "sstfb: can't alloc cmap memory.\n"); 1352 goto fail; 1353 } 1354 1355 /* register fb */ 1356 info->device = &pdev->dev; 1357 if (register_framebuffer(info) < 0) { 1358 printk(KERN_ERR "sstfb: can't register framebuffer.\n"); 1359 goto fail_register; 1360 } 1361 1362 sstfb_clear_screen(info); 1363 1364 if (device_create_file(info->dev, &device_attrs[0])) 1365 printk(KERN_WARNING "sstfb: can't create sysfs entry.\n"); 1366 1367 1368 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%p\n", 1369 info->node, fix->id, info->screen_base); 1370 1371 return 0; 1372 1373fail_register: 1374 fb_dealloc_cmap(&info->cmap); 1375fail: 1376 iounmap(info->screen_base); 1377fail_fb_remap: 1378 iounmap(par->mmio_vbase); 1379fail_mmio_remap: 1380 release_mem_region(fix->smem_start, 0x400000); 1381fail_fb_mem: 1382 release_mem_region(fix->mmio_start, info->fix.mmio_len); 1383fail_mmio_mem: 1384 framebuffer_release(info); 1385 return -ENXIO; /* no voodoo detected */ 1386} 1387 1388static void __devexit sstfb_remove(struct pci_dev *pdev) 1389{ 1390 struct sstfb_par *par; 1391 struct fb_info *info; 1392 1393 info = pci_get_drvdata(pdev); 1394 par = info->par; 1395 1396 device_remove_file(info->dev, &device_attrs[0]); 1397 sst_shutdown(info); 1398 iounmap(info->screen_base); 1399 iounmap(par->mmio_vbase); 1400 release_mem_region(info->fix.smem_start, 0x400000); 1401 release_mem_region(info->fix.mmio_start, info->fix.mmio_len); 1402 fb_dealloc_cmap(&info->cmap); 1403 unregister_framebuffer(info); 1404 framebuffer_release(info); 1405} 1406 1407 1408static const struct pci_device_id sstfb_id_tbl[] = { 1409 { PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO ), 1410 .driver_data = ID_VOODOO1, }, 1411 { PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO2), 1412 .driver_data = ID_VOODOO2, }, 1413 { 0 }, 1414}; 1415 1416static struct pci_driver sstfb_driver = { 1417 .name = "sstfb", 1418 .id_table = sstfb_id_tbl, 1419 .probe = sstfb_probe, 1420 .remove = __devexit_p(sstfb_remove), 1421}; 1422 1423 1424static int __devinit sstfb_init(void) 1425{ 1426 char *option = NULL; 1427 1428 if (fb_get_options("sstfb", &option)) 1429 return -ENODEV; 1430 sstfb_setup(option); 1431 1432 return pci_register_driver(&sstfb_driver); 1433} 1434 1435static void __devexit sstfb_exit(void) 1436{ 1437 pci_unregister_driver(&sstfb_driver); 1438} 1439 1440 1441module_init(sstfb_init); 1442module_exit(sstfb_exit); 1443 1444MODULE_AUTHOR("(c) 2000,2002 Ghozlane Toumi <gtoumi@laposte.net>"); 1445MODULE_DESCRIPTION("FBDev driver for 3dfx Voodoo Graphics and Voodoo2 based video boards"); 1446MODULE_LICENSE("GPL"); 1447 1448module_param(mem, int, 0); 1449MODULE_PARM_DESC(mem, "Size of frame buffer memory in MB (1, 2, 4 MB, default=autodetect)"); 1450module_param(vgapass, bool, 0); 1451MODULE_PARM_DESC(vgapass, "Enable VGA PassThrough mode (0 or 1) (default=0)"); 1452module_param(clipping, bool, 0); 1453MODULE_PARM_DESC(clipping, "Enable clipping (slower, safer) (0 or 1) (default=1)"); 1454module_param(gfxclk, int, 0); 1455MODULE_PARM_DESC(gfxclk, "Force graphic chip frequency in MHz. DANGEROUS. (default=auto)"); 1456module_param(slowpci, bool, 0); 1457MODULE_PARM_DESC(slowpci, "Uses slow PCI settings (0 or 1) (default=0)"); 1458module_param(mode_option, charp, 0); 1459MODULE_PARM_DESC(mode_option, "Initial video mode (default=" DEFAULT_VIDEO_MODE ")"); 1460