1/* drivers/video/s1d13xxxfb.c 2 * 3 * (c) 2004 Simtec Electronics 4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org> 5 * (c) 2009 Kristoffer Ericson <kristoffer.ericson@gmail.com> 6 * 7 * Driver for Epson S1D13xxx series framebuffer chips 8 * 9 * Adapted from 10 * linux/drivers/video/skeletonfb.c 11 * linux/drivers/video/epson1355fb.c 12 * linux/drivers/video/epson/s1d13xxxfb.c (2.4 driver by Epson) 13 * 14 * TODO: - handle dual screen display (CRT and LCD at the same time). 15 * - check_var(), mode change, etc. 16 * - probably not SMP safe :) 17 * - support all bitblt operations on all cards 18 * 19 * This file is subject to the terms and conditions of the GNU General Public 20 * License. See the file COPYING in the main directory of this archive for 21 * more details. 22 */ 23 24#include <linux/module.h> 25#include <linux/platform_device.h> 26#include <linux/delay.h> 27#include <linux/types.h> 28#include <linux/errno.h> 29#include <linux/mm.h> 30#include <linux/mman.h> 31#include <linux/fb.h> 32#include <linux/spinlock_types.h> 33#include <linux/spinlock.h> 34#include <linux/slab.h> 35 36#include <asm/io.h> 37 38#include <video/s1d13xxxfb.h> 39 40#define PFX "s1d13xxxfb: " 41#define BLIT "s1d13xxxfb_bitblt: " 42 43/* 44 * set this to enable debugging on general functions 45 */ 46#define dbg(fmt, args...) do { } while (0) 47 48/* 49 * set this to enable debugging on 2D acceleration 50 */ 51#define dbg_blit(fmt, args...) do { } while (0) 52 53/* 54 * we make sure only one bitblt operation is running 55 */ 56static DEFINE_SPINLOCK(s1d13xxxfb_bitblt_lock); 57 58/* 59 * list of card production ids 60 */ 61static const int s1d13xxxfb_prod_ids[] = { 62 S1D13505_PROD_ID, 63 S1D13506_PROD_ID, 64 S1D13806_PROD_ID, 65}; 66 67/* 68 * List of card strings 69 */ 70static const char *s1d13xxxfb_prod_names[] = { 71 "S1D13505", 72 "S1D13506", 73 "S1D13806", 74}; 75 76/* 77 * here we define the default struct fb_fix_screeninfo 78 */ 79static struct fb_fix_screeninfo __devinitdata s1d13xxxfb_fix = { 80 .id = S1D_FBID, 81 .type = FB_TYPE_PACKED_PIXELS, 82 .visual = FB_VISUAL_PSEUDOCOLOR, 83 .xpanstep = 0, 84 .ypanstep = 1, 85 .ywrapstep = 0, 86 .accel = FB_ACCEL_NONE, 87}; 88 89static inline u8 90s1d13xxxfb_readreg(struct s1d13xxxfb_par *par, u16 regno) 91{ 92#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || \ 93 defined(CONFIG_PLAT_MAPPI3) 94 regno=((regno & 1) ? (regno & ~1L) : (regno + 1)); 95#endif 96 return readb(par->regs + regno); 97} 98 99static inline void 100s1d13xxxfb_writereg(struct s1d13xxxfb_par *par, u16 regno, u8 value) 101{ 102#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || \ 103 defined(CONFIG_PLAT_MAPPI3) 104 regno=((regno & 1) ? (regno & ~1L) : (regno + 1)); 105#endif 106 writeb(value, par->regs + regno); 107} 108 109static inline void 110s1d13xxxfb_runinit(struct s1d13xxxfb_par *par, 111 const struct s1d13xxxfb_regval *initregs, 112 const unsigned int size) 113{ 114 int i; 115 116 for (i = 0; i < size; i++) { 117 if ((initregs[i].addr == S1DREG_DELAYOFF) || 118 (initregs[i].addr == S1DREG_DELAYON)) 119 mdelay((int)initregs[i].value); 120 else { 121 s1d13xxxfb_writereg(par, initregs[i].addr, initregs[i].value); 122 } 123 } 124 125 /* make sure the hardware can cope with us */ 126 mdelay(1); 127} 128 129static inline void 130lcd_enable(struct s1d13xxxfb_par *par, int enable) 131{ 132 u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE); 133 134 if (enable) 135 mode |= 0x01; 136 else 137 mode &= ~0x01; 138 139 s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode); 140} 141 142static inline void 143crt_enable(struct s1d13xxxfb_par *par, int enable) 144{ 145 u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE); 146 147 if (enable) 148 mode |= 0x02; 149 else 150 mode &= ~0x02; 151 152 s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode); 153} 154 155 156/************************************************************* 157 framebuffer control functions 158 *************************************************************/ 159static inline void 160s1d13xxxfb_setup_pseudocolour(struct fb_info *info) 161{ 162 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 163 164 info->var.red.length = 4; 165 info->var.green.length = 4; 166 info->var.blue.length = 4; 167} 168 169static inline void 170s1d13xxxfb_setup_truecolour(struct fb_info *info) 171{ 172 info->fix.visual = FB_VISUAL_TRUECOLOR; 173 info->var.bits_per_pixel = 16; 174 175 info->var.red.length = 5; 176 info->var.red.offset = 11; 177 178 info->var.green.length = 6; 179 info->var.green.offset = 5; 180 181 info->var.blue.length = 5; 182 info->var.blue.offset = 0; 183} 184 185static int 186s1d13xxxfb_set_par(struct fb_info *info) 187{ 188 struct s1d13xxxfb_par *s1dfb = info->par; 189 unsigned int val; 190 191 dbg("s1d13xxxfb_set_par: bpp=%d\n", info->var.bits_per_pixel); 192 193 if ((s1dfb->display & 0x01)) /* LCD */ 194 val = s1d13xxxfb_readreg(s1dfb, S1DREG_LCD_DISP_MODE); /* read colour control */ 195 else /* CRT */ 196 val = s1d13xxxfb_readreg(s1dfb, S1DREG_CRT_DISP_MODE); /* read colour control */ 197 198 val &= ~0x07; 199 200 switch (info->var.bits_per_pixel) { 201 case 4: 202 dbg("pseudo colour 4\n"); 203 s1d13xxxfb_setup_pseudocolour(info); 204 val |= 2; 205 break; 206 case 8: 207 dbg("pseudo colour 8\n"); 208 s1d13xxxfb_setup_pseudocolour(info); 209 val |= 3; 210 break; 211 case 16: 212 dbg("true colour\n"); 213 s1d13xxxfb_setup_truecolour(info); 214 val |= 5; 215 break; 216 217 default: 218 dbg("bpp not supported!\n"); 219 return -EINVAL; 220 } 221 222 dbg("writing %02x to display mode register\n", val); 223 224 if ((s1dfb->display & 0x01)) /* LCD */ 225 s1d13xxxfb_writereg(s1dfb, S1DREG_LCD_DISP_MODE, val); 226 else /* CRT */ 227 s1d13xxxfb_writereg(s1dfb, S1DREG_CRT_DISP_MODE, val); 228 229 info->fix.line_length = info->var.xres * info->var.bits_per_pixel; 230 info->fix.line_length /= 8; 231 232 dbg("setting line_length to %d\n", info->fix.line_length); 233 234 dbg("done setup\n"); 235 236 return 0; 237} 238 239/** 240 * s1d13xxxfb_setcolreg - sets a color register. 241 * @regno: Which register in the CLUT we are programming 242 * @red: The red value which can be up to 16 bits wide 243 * @green: The green value which can be up to 16 bits wide 244 * @blue: The blue value which can be up to 16 bits wide. 245 * @transp: If supported the alpha value which can be up to 16 bits wide. 246 * @info: frame buffer info structure 247 * 248 * Returns negative errno on error, or zero on success. 249 */ 250static int 251s1d13xxxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 252 u_int transp, struct fb_info *info) 253{ 254 struct s1d13xxxfb_par *s1dfb = info->par; 255 unsigned int pseudo_val; 256 257 if (regno >= S1D_PALETTE_SIZE) 258 return -EINVAL; 259 260 dbg("s1d13xxxfb_setcolreg: %d: rgb=%d,%d,%d, tr=%d\n", 261 regno, red, green, blue, transp); 262 263 if (info->var.grayscale) 264 red = green = blue = (19595*red + 38470*green + 7471*blue) >> 16; 265 266 switch (info->fix.visual) { 267 case FB_VISUAL_TRUECOLOR: 268 if (regno >= 16) 269 return -EINVAL; 270 271 /* deal with creating pseudo-palette entries */ 272 273 pseudo_val = (red >> 11) << info->var.red.offset; 274 pseudo_val |= (green >> 10) << info->var.green.offset; 275 pseudo_val |= (blue >> 11) << info->var.blue.offset; 276 277 dbg("s1d13xxxfb_setcolreg: pseudo %d, val %08x\n", 278 regno, pseudo_val); 279 280#if defined(CONFIG_PLAT_MAPPI) 281 ((u32 *)info->pseudo_palette)[regno] = cpu_to_le16(pseudo_val); 282#else 283 ((u32 *)info->pseudo_palette)[regno] = pseudo_val; 284#endif 285 286 break; 287 case FB_VISUAL_PSEUDOCOLOR: 288 s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_ADDR, regno); 289 s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, red); 290 s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, green); 291 s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, blue); 292 293 break; 294 default: 295 return -ENOSYS; 296 } 297 298 dbg("s1d13xxxfb_setcolreg: done\n"); 299 300 return 0; 301} 302 303/** 304 * s1d13xxxfb_blank - blanks the display. 305 * @blank_mode: the blank mode we want. 306 * @info: frame buffer structure that represents a single frame buffer 307 * 308 * Blank the screen if blank_mode != 0, else unblank. Return 0 if 309 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a 310 * video mode which doesn't support it. Implements VESA suspend 311 * and powerdown modes on hardware that supports disabling hsync/vsync: 312 * blank_mode == 2: suspend vsync 313 * blank_mode == 3: suspend hsync 314 * blank_mode == 4: powerdown 315 * 316 * Returns negative errno on error, or zero on success. 317 */ 318static int 319s1d13xxxfb_blank(int blank_mode, struct fb_info *info) 320{ 321 struct s1d13xxxfb_par *par = info->par; 322 323 dbg("s1d13xxxfb_blank: blank=%d, info=%p\n", blank_mode, info); 324 325 switch (blank_mode) { 326 case FB_BLANK_UNBLANK: 327 case FB_BLANK_NORMAL: 328 if ((par->display & 0x01) != 0) 329 lcd_enable(par, 1); 330 if ((par->display & 0x02) != 0) 331 crt_enable(par, 1); 332 break; 333 case FB_BLANK_VSYNC_SUSPEND: 334 case FB_BLANK_HSYNC_SUSPEND: 335 break; 336 case FB_BLANK_POWERDOWN: 337 lcd_enable(par, 0); 338 crt_enable(par, 0); 339 break; 340 default: 341 return -EINVAL; 342 } 343 344 /* let fbcon do a soft blank for us */ 345 return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0); 346} 347 348/** 349 * s1d13xxxfb_pan_display - Pans the display. 350 * @var: frame buffer variable screen structure 351 * @info: frame buffer structure that represents a single frame buffer 352 * 353 * Pan (or wrap, depending on the `vmode' field) the display using the 354 * `yoffset' field of the `var' structure (`xoffset' not yet supported). 355 * If the values don't fit, return -EINVAL. 356 * 357 * Returns negative errno on error, or zero on success. 358 */ 359static int 360s1d13xxxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 361{ 362 struct s1d13xxxfb_par *par = info->par; 363 u32 start; 364 365 if (var->xoffset != 0) /* not yet ... */ 366 return -EINVAL; 367 368 if (var->yoffset + info->var.yres > info->var.yres_virtual) 369 return -EINVAL; 370 371 start = (info->fix.line_length >> 1) * var->yoffset; 372 373 if ((par->display & 0x01)) { 374 /* LCD */ 375 s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START0, (start & 0xff)); 376 s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START1, ((start >> 8) & 0xff)); 377 s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START2, ((start >> 16) & 0x0f)); 378 } else { 379 /* CRT */ 380 s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START0, (start & 0xff)); 381 s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START1, ((start >> 8) & 0xff)); 382 s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START2, ((start >> 16) & 0x0f)); 383 } 384 385 return 0; 386} 387 388/************************************************************ 389 functions to handle bitblt acceleration 390 ************************************************************/ 391 392/** 393 * bltbit_wait_bitset - waits for change in register value 394 * @info : framebuffer structure 395 * @bit : value expected in register 396 * @timeout : ... 397 * 398 * waits until value changes INTO bit 399 */ 400static u8 401bltbit_wait_bitset(struct fb_info *info, u8 bit, int timeout) 402{ 403 while (!(s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0) & bit)) { 404 udelay(10); 405 if (!--timeout) { 406 dbg_blit("wait_bitset timeout\n"); 407 break; 408 } 409 } 410 411 return timeout; 412} 413 414/** 415 * bltbit_wait_bitclear - waits for change in register value 416 * @info : frambuffer structure 417 * @bit : value currently in register 418 * @timeout : ... 419 * 420 * waits until value changes FROM bit 421 * 422 */ 423static u8 424bltbit_wait_bitclear(struct fb_info *info, u8 bit, int timeout) 425{ 426 while (s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0) & bit) { 427 udelay(10); 428 if (!--timeout) { 429 dbg_blit("wait_bitclear timeout\n"); 430 break; 431 } 432 } 433 434 return timeout; 435} 436 437/** 438 * bltbit_fifo_status - checks the current status of the fifo 439 * @info : framebuffer structure 440 * 441 * returns number of free words in buffer 442 */ 443static u8 444bltbit_fifo_status(struct fb_info *info) 445{ 446 u8 status; 447 448 status = s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0); 449 450 /* its empty so room for 16 words */ 451 if (status & BBLT_FIFO_EMPTY) 452 return 16; 453 454 /* its full so we dont want to add */ 455 if (status & BBLT_FIFO_FULL) 456 return 0; 457 458 /* its atleast half full but we can add one atleast */ 459 if (status & BBLT_FIFO_NOT_FULL) 460 return 1; 461 462 return 0; 463} 464 465/* 466 * s1d13xxxfb_bitblt_copyarea - accelerated copyarea function 467 * @info : framebuffer structure 468 * @area : fb_copyarea structure 469 * 470 * supports (atleast) S1D13506 471 * 472 */ 473static void 474s1d13xxxfb_bitblt_copyarea(struct fb_info *info, const struct fb_copyarea *area) 475{ 476 u32 dst, src; 477 u32 stride; 478 u16 reverse = 0; 479 u16 sx = area->sx, sy = area->sy; 480 u16 dx = area->dx, dy = area->dy; 481 u16 width = area->width, height = area->height; 482 u16 bpp; 483 484 spin_lock(&s1d13xxxfb_bitblt_lock); 485 486 /* bytes per xres line */ 487 bpp = (info->var.bits_per_pixel >> 3); 488 stride = bpp * info->var.xres; 489 490 /* reverse, calculate the last pixel in rectangle */ 491 if ((dy > sy) || ((dy == sy) && (dx >= sx))) { 492 dst = (((dy + height - 1) * stride) + (bpp * (dx + width - 1))); 493 src = (((sy + height - 1) * stride) + (bpp * (sx + width - 1))); 494 reverse = 1; 495 /* not reverse, calculate the first pixel in rectangle */ 496 } else { /* (y * xres) + (bpp * x) */ 497 dst = (dy * stride) + (bpp * dx); 498 src = (sy * stride) + (bpp * sx); 499 } 500 501 /* set source address */ 502 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START0, (src & 0xff)); 503 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START1, (src >> 8) & 0x00ff); 504 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START2, (src >> 16) & 0x00ff); 505 506 /* set destination address */ 507 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dst & 0xff)); 508 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, (dst >> 8) & 0x00ff); 509 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, (dst >> 16) & 0x00ff); 510 511 /* program height and width */ 512 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, (width & 0xff) - 1); 513 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (width >> 8)); 514 515 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, (height & 0xff) - 1); 516 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (height >> 8)); 517 518 /* negative direction ROP */ 519 if (reverse == 1) { 520 dbg_blit("(copyarea) negative rop\n"); 521 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x03); 522 } else /* positive direction ROP */ { 523 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x02); 524 dbg_blit("(copyarea) positive rop\n"); 525 } 526 527 /* set for rectangel mode and not linear */ 528 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0); 529 530 /* setup the bpp 1 = 16bpp, 0 = 8bpp*/ 531 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (bpp >> 1)); 532 533 /* set words per xres */ 534 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (stride >> 1) & 0xff); 535 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (stride >> 9)); 536 537 dbg_blit("(copyarea) dx=%d, dy=%d\n", dx, dy); 538 dbg_blit("(copyarea) sx=%d, sy=%d\n", sx, sy); 539 dbg_blit("(copyarea) width=%d, height=%d\n", width - 1, height - 1); 540 dbg_blit("(copyarea) stride=%d\n", stride); 541 dbg_blit("(copyarea) bpp=%d=0x0%d, mem_offset1=%d, mem_offset2=%d\n", bpp, (bpp >> 1), 542 (stride >> 1) & 0xff, stride >> 9); 543 544 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CC_EXP, 0x0c); 545 546 /* initialize the engine */ 547 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80); 548 549 /* wait to complete */ 550 bltbit_wait_bitclear(info, 0x80, 8000); 551 552 spin_unlock(&s1d13xxxfb_bitblt_lock); 553} 554 555/** 556 * 557 * s1d13xxxfb_bitblt_solidfill - accelerated solidfill function 558 * @info : framebuffer structure 559 * @rect : fb_fillrect structure 560 * 561 * supports (atleast 13506) 562 * 563 **/ 564static void 565s1d13xxxfb_bitblt_solidfill(struct fb_info *info, const struct fb_fillrect *rect) 566{ 567 u32 screen_stride, dest; 568 u32 fg; 569 u16 bpp = (info->var.bits_per_pixel >> 3); 570 571 /* grab spinlock */ 572 spin_lock(&s1d13xxxfb_bitblt_lock); 573 574 /* bytes per x width */ 575 screen_stride = (bpp * info->var.xres); 576 577 /* bytes to starting point */ 578 dest = ((rect->dy * screen_stride) + (bpp * rect->dx)); 579 580 dbg_blit("(solidfill) dx=%d, dy=%d, stride=%d, dest=%d\n" 581 "(solidfill) : rect_width=%d, rect_height=%d\n", 582 rect->dx, rect->dy, screen_stride, dest, 583 rect->width - 1, rect->height - 1); 584 585 dbg_blit("(solidfill) : xres=%d, yres=%d, bpp=%d\n", 586 info->var.xres, info->var.yres, 587 info->var.bits_per_pixel); 588 dbg_blit("(solidfill) : rop=%d\n", rect->rop); 589 590 /* We split the destination into the three registers */ 591 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dest & 0x00ff)); 592 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, ((dest >> 8) & 0x00ff)); 593 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, ((dest >> 16) & 0x00ff)); 594 595 /* give information regarding rectangel width */ 596 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, ((rect->width) & 0x00ff) - 1); 597 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (rect->width >> 8)); 598 599 /* give information regarding rectangel height */ 600 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, ((rect->height) & 0x00ff) - 1); 601 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (rect->height >> 8)); 602 603 if (info->fix.visual == FB_VISUAL_TRUECOLOR || 604 info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 605 fg = ((u32 *)info->pseudo_palette)[rect->color]; 606 dbg_blit("(solidfill) truecolor/directcolor\n"); 607 dbg_blit("(solidfill) pseudo_palette[%d] = %d\n", rect->color, fg); 608 } else { 609 fg = rect->color; 610 dbg_blit("(solidfill) color = %d\n", rect->color); 611 } 612 613 /* set foreground color */ 614 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC0, (fg & 0xff)); 615 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC1, (fg >> 8) & 0xff); 616 617 /* set rectangual region of memory (rectangle and not linear) */ 618 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0); 619 620 /* set operation mode SOLID_FILL */ 621 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, BBLT_SOLID_FILL); 622 623 /* set bits per pixel (1 = 16bpp, 0 = 8bpp) */ 624 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (info->var.bits_per_pixel >> 4)); 625 626 /* set the memory offset for the bblt in word sizes */ 627 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (screen_stride >> 1) & 0x00ff); 628 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (screen_stride >> 9)); 629 630 /* and away we go.... */ 631 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80); 632 633 /* wait until its done */ 634 bltbit_wait_bitclear(info, 0x80, 8000); 635 636 /* let others play */ 637 spin_unlock(&s1d13xxxfb_bitblt_lock); 638} 639 640/* framebuffer information structures */ 641static struct fb_ops s1d13xxxfb_fbops = { 642 .owner = THIS_MODULE, 643 .fb_set_par = s1d13xxxfb_set_par, 644 .fb_setcolreg = s1d13xxxfb_setcolreg, 645 .fb_blank = s1d13xxxfb_blank, 646 647 .fb_pan_display = s1d13xxxfb_pan_display, 648 649 /* gets replaced at chip detection time */ 650 .fb_fillrect = cfb_fillrect, 651 .fb_copyarea = cfb_copyarea, 652 .fb_imageblit = cfb_imageblit, 653}; 654 655static int s1d13xxxfb_width_tab[2][4] __devinitdata = { 656 {4, 8, 16, -1}, 657 {9, 12, 18, -1}, 658}; 659 660/** 661 * s1d13xxxfb_fetch_hw_state - Configure the framebuffer according to 662 * hardware setup. 663 * @info: frame buffer structure 664 * 665 * We setup the framebuffer structures according to the current 666 * hardware setup. On some machines, the BIOS will have filled 667 * the chip registers with such info, on others, these values will 668 * have been written in some init procedure. In any case, the 669 * software values needs to match the hardware ones. This is what 670 * this function ensures. 671 * 672 * Note: some of the hardcoded values here might need some love to 673 * work on various chips, and might need to no longer be hardcoded. 674 */ 675static void __devinit 676s1d13xxxfb_fetch_hw_state(struct fb_info *info) 677{ 678 struct fb_var_screeninfo *var = &info->var; 679 struct fb_fix_screeninfo *fix = &info->fix; 680 struct s1d13xxxfb_par *par = info->par; 681 u8 panel, display; 682 u16 offset; 683 u32 xres, yres; 684 u32 xres_virtual, yres_virtual; 685 int bpp, lcd_bpp; 686 int is_color, is_dual, is_tft; 687 int lcd_enabled, crt_enabled; 688 689 fix->type = FB_TYPE_PACKED_PIXELS; 690 691 /* general info */ 692 par->display = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE); 693 crt_enabled = (par->display & 0x02) != 0; 694 lcd_enabled = (par->display & 0x01) != 0; 695 696 if (lcd_enabled && crt_enabled) 697 printk(KERN_WARNING PFX "Warning: LCD and CRT detected, using LCD\n"); 698 699 if (lcd_enabled) 700 display = s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_MODE); 701 else /* CRT */ 702 display = s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_MODE); 703 704 bpp = display & 0x07; 705 706 switch (bpp) { 707 case 2: /* 4 bpp */ 708 case 3: /* 8 bpp */ 709 var->bits_per_pixel = 8; 710 var->red.offset = var->green.offset = var->blue.offset = 0; 711 var->red.length = var->green.length = var->blue.length = 8; 712 break; 713 case 5: /* 16 bpp */ 714 s1d13xxxfb_setup_truecolour(info); 715 break; 716 default: 717 dbg("bpp: %i\n", bpp); 718 } 719 fb_alloc_cmap(&info->cmap, 256, 0); 720 721 /* LCD info */ 722 panel = s1d13xxxfb_readreg(par, S1DREG_PANEL_TYPE); 723 is_color = (panel & 0x04) != 0; 724 is_dual = (panel & 0x02) != 0; 725 is_tft = (panel & 0x01) != 0; 726 lcd_bpp = s1d13xxxfb_width_tab[is_tft][(panel >> 4) & 3]; 727 728 if (lcd_enabled) { 729 xres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_HWIDTH) + 1) * 8; 730 yres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT0) + 731 ((s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT1) & 0x03) << 8) + 1); 732 733 offset = (s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF0) + 734 ((s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF1) & 0x7) << 8)); 735 } else { /* crt */ 736 xres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_HWIDTH) + 1) * 8; 737 yres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT0) + 738 ((s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT1) & 0x03) << 8) + 1); 739 740 offset = (s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF0) + 741 ((s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF1) & 0x7) << 8)); 742 } 743 xres_virtual = offset * 16 / var->bits_per_pixel; 744 yres_virtual = fix->smem_len / (offset * 2); 745 746 var->xres = xres; 747 var->yres = yres; 748 var->xres_virtual = xres_virtual; 749 var->yres_virtual = yres_virtual; 750 var->xoffset = var->yoffset = 0; 751 752 fix->line_length = offset * 2; 753 754 var->grayscale = !is_color; 755 756 var->activate = FB_ACTIVATE_NOW; 757 758 dbg(PFX "bpp=%d, lcd_bpp=%d, " 759 "crt_enabled=%d, lcd_enabled=%d\n", 760 var->bits_per_pixel, lcd_bpp, crt_enabled, lcd_enabled); 761 dbg(PFX "xres=%d, yres=%d, vxres=%d, vyres=%d " 762 "is_color=%d, is_dual=%d, is_tft=%d\n", 763 xres, yres, xres_virtual, yres_virtual, is_color, is_dual, is_tft); 764} 765 766 767static int 768s1d13xxxfb_remove(struct platform_device *pdev) 769{ 770 struct fb_info *info = platform_get_drvdata(pdev); 771 struct s1d13xxxfb_par *par = NULL; 772 773 if (info) { 774 par = info->par; 775 if (par && par->regs) { 776 /* disable output & enable powersave */ 777 s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, 0x00); 778 s1d13xxxfb_writereg(par, S1DREG_PS_CNF, 0x11); 779 iounmap(par->regs); 780 } 781 782 fb_dealloc_cmap(&info->cmap); 783 784 if (info->screen_base) 785 iounmap(info->screen_base); 786 787 framebuffer_release(info); 788 } 789 790 release_mem_region(pdev->resource[0].start, 791 pdev->resource[0].end - pdev->resource[0].start +1); 792 release_mem_region(pdev->resource[1].start, 793 pdev->resource[1].end - pdev->resource[1].start +1); 794 return 0; 795} 796 797static int __devinit 798s1d13xxxfb_probe(struct platform_device *pdev) 799{ 800 struct s1d13xxxfb_par *default_par; 801 struct fb_info *info; 802 struct s1d13xxxfb_pdata *pdata = NULL; 803 int ret = 0; 804 int i; 805 u8 revision, prod_id; 806 807 dbg("probe called: device is %p\n", pdev); 808 809 printk(KERN_INFO "Epson S1D13XXX FB Driver\n"); 810 811 /* enable platform-dependent hardware glue, if any */ 812 if (pdev->dev.platform_data) 813 pdata = pdev->dev.platform_data; 814 815 if (pdata && pdata->platform_init_video) 816 pdata->platform_init_video(); 817 818 if (pdev->num_resources != 2) { 819 dev_err(&pdev->dev, "invalid num_resources: %i\n", 820 pdev->num_resources); 821 ret = -ENODEV; 822 goto bail; 823 } 824 825 /* resource[0] is VRAM, resource[1] is registers */ 826 if (pdev->resource[0].flags != IORESOURCE_MEM 827 || pdev->resource[1].flags != IORESOURCE_MEM) { 828 dev_err(&pdev->dev, "invalid resource type\n"); 829 ret = -ENODEV; 830 goto bail; 831 } 832 833 if (!request_mem_region(pdev->resource[0].start, 834 pdev->resource[0].end - pdev->resource[0].start +1, "s1d13xxxfb mem")) { 835 dev_dbg(&pdev->dev, "request_mem_region failed\n"); 836 ret = -EBUSY; 837 goto bail; 838 } 839 840 if (!request_mem_region(pdev->resource[1].start, 841 pdev->resource[1].end - pdev->resource[1].start +1, "s1d13xxxfb regs")) { 842 dev_dbg(&pdev->dev, "request_mem_region failed\n"); 843 ret = -EBUSY; 844 goto bail; 845 } 846 847 info = framebuffer_alloc(sizeof(struct s1d13xxxfb_par) + sizeof(u32) * 256, &pdev->dev); 848 if (!info) { 849 ret = -ENOMEM; 850 goto bail; 851 } 852 853 platform_set_drvdata(pdev, info); 854 default_par = info->par; 855 default_par->regs = ioremap_nocache(pdev->resource[1].start, 856 pdev->resource[1].end - pdev->resource[1].start +1); 857 if (!default_par->regs) { 858 printk(KERN_ERR PFX "unable to map registers\n"); 859 ret = -ENOMEM; 860 goto bail; 861 } 862 info->pseudo_palette = default_par->pseudo_palette; 863 864 info->screen_base = ioremap_nocache(pdev->resource[0].start, 865 pdev->resource[0].end - pdev->resource[0].start +1); 866 867 if (!info->screen_base) { 868 printk(KERN_ERR PFX "unable to map framebuffer\n"); 869 ret = -ENOMEM; 870 goto bail; 871 } 872 873 /* production id is top 6 bits */ 874 prod_id = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) >> 2; 875 /* revision id is lower 2 bits */ 876 revision = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) & 0x3; 877 ret = -ENODEV; 878 879 for (i = 0; i < ARRAY_SIZE(s1d13xxxfb_prod_ids); i++) { 880 if (prod_id == s1d13xxxfb_prod_ids[i]) { 881 /* looks like we got it in our list */ 882 default_par->prod_id = prod_id; 883 default_par->revision = revision; 884 ret = 0; 885 break; 886 } 887 } 888 889 if (!ret) { 890 printk(KERN_INFO PFX "chip production id %i = %s\n", 891 prod_id, s1d13xxxfb_prod_names[i]); 892 printk(KERN_INFO PFX "chip revision %i\n", revision); 893 } else { 894 printk(KERN_INFO PFX 895 "unknown chip production id %i, revision %i\n", 896 prod_id, revision); 897 printk(KERN_INFO PFX "please contant maintainer\n"); 898 goto bail; 899 } 900 901 info->fix = s1d13xxxfb_fix; 902 info->fix.mmio_start = pdev->resource[1].start; 903 info->fix.mmio_len = pdev->resource[1].end - pdev->resource[1].start + 1; 904 info->fix.smem_start = pdev->resource[0].start; 905 info->fix.smem_len = pdev->resource[0].end - pdev->resource[0].start + 1; 906 907 printk(KERN_INFO PFX "regs mapped at 0x%p, fb %d KiB mapped at 0x%p\n", 908 default_par->regs, info->fix.smem_len / 1024, info->screen_base); 909 910 info->par = default_par; 911 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; 912 info->fbops = &s1d13xxxfb_fbops; 913 914 switch(prod_id) { 915 case S1D13506_PROD_ID: /* activate acceleration */ 916 s1d13xxxfb_fbops.fb_fillrect = s1d13xxxfb_bitblt_solidfill; 917 s1d13xxxfb_fbops.fb_copyarea = s1d13xxxfb_bitblt_copyarea; 918 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN | 919 FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA; 920 break; 921 default: 922 break; 923 } 924 925 /* perform "manual" chip initialization, if needed */ 926 if (pdata && pdata->initregs) 927 s1d13xxxfb_runinit(info->par, pdata->initregs, pdata->initregssize); 928 929 s1d13xxxfb_fetch_hw_state(info); 930 931 if (register_framebuffer(info) < 0) { 932 ret = -EINVAL; 933 goto bail; 934 } 935 936 printk(KERN_INFO "fb%d: %s frame buffer device\n", 937 info->node, info->fix.id); 938 939 return 0; 940 941bail: 942 s1d13xxxfb_remove(pdev); 943 return ret; 944 945} 946 947#ifdef CONFIG_PM 948static int s1d13xxxfb_suspend(struct platform_device *dev, pm_message_t state) 949{ 950 struct fb_info *info = platform_get_drvdata(dev); 951 struct s1d13xxxfb_par *s1dfb = info->par; 952 struct s1d13xxxfb_pdata *pdata = NULL; 953 954 /* disable display */ 955 lcd_enable(s1dfb, 0); 956 crt_enable(s1dfb, 0); 957 958 if (dev->dev.platform_data) 959 pdata = dev->dev.platform_data; 960 961 s1dfb->disp_save = NULL; 962 963 if (!s1dfb->regs_save) 964 s1dfb->regs_save = kmalloc(info->fix.mmio_len, GFP_KERNEL); 965 966 if (!s1dfb->regs_save) { 967 printk(KERN_ERR PFX "no memory to save registers"); 968 return -ENOMEM; 969 } 970 971 /* backup all registers */ 972 memcpy_fromio(s1dfb->regs_save, s1dfb->regs, info->fix.mmio_len); 973 974 /* now activate power save mode */ 975 s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x11); 976 977 if (pdata && pdata->platform_suspend_video) 978 return pdata->platform_suspend_video(); 979 else 980 return 0; 981} 982 983static int s1d13xxxfb_resume(struct platform_device *dev) 984{ 985 struct fb_info *info = platform_get_drvdata(dev); 986 struct s1d13xxxfb_par *s1dfb = info->par; 987 struct s1d13xxxfb_pdata *pdata = NULL; 988 989 /* awaken the chip */ 990 s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x10); 991 992 /* do not let go until SDRAM "wakes up" */ 993 while ((s1d13xxxfb_readreg(s1dfb, S1DREG_PS_STATUS) & 0x01)) 994 udelay(10); 995 996 if (dev->dev.platform_data) 997 pdata = dev->dev.platform_data; 998 999 if (s1dfb->regs_save) { 1000 /* will write RO regs, *should* get away with it :) */ 1001 memcpy_toio(s1dfb->regs, s1dfb->regs_save, info->fix.mmio_len); 1002 kfree(s1dfb->regs_save); 1003 } 1004 1005 if (s1dfb->disp_save) { 1006 memcpy_toio(info->screen_base, s1dfb->disp_save, 1007 info->fix.smem_len); 1008 kfree(s1dfb->disp_save); 1009 } 1010 1011 if ((s1dfb->display & 0x01) != 0) 1012 lcd_enable(s1dfb, 1); 1013 if ((s1dfb->display & 0x02) != 0) 1014 crt_enable(s1dfb, 1); 1015 1016 if (pdata && pdata->platform_resume_video) 1017 return pdata->platform_resume_video(); 1018 else 1019 return 0; 1020} 1021#endif /* CONFIG_PM */ 1022 1023static struct platform_driver s1d13xxxfb_driver = { 1024 .probe = s1d13xxxfb_probe, 1025 .remove = s1d13xxxfb_remove, 1026#ifdef CONFIG_PM 1027 .suspend = s1d13xxxfb_suspend, 1028 .resume = s1d13xxxfb_resume, 1029#endif 1030 .driver = { 1031 .name = S1D_DEVICENAME, 1032 }, 1033}; 1034 1035 1036static int __init 1037s1d13xxxfb_init(void) 1038{ 1039 1040#ifndef MODULE 1041 if (fb_get_options("s1d13xxxfb", NULL)) 1042 return -ENODEV; 1043#endif 1044 1045 return platform_driver_register(&s1d13xxxfb_driver); 1046} 1047 1048 1049static void __exit 1050s1d13xxxfb_exit(void) 1051{ 1052 platform_driver_unregister(&s1d13xxxfb_driver); 1053} 1054 1055module_init(s1d13xxxfb_init); 1056module_exit(s1d13xxxfb_exit); 1057 1058 1059MODULE_LICENSE("GPL"); 1060MODULE_DESCRIPTION("Framebuffer driver for S1D13xxx devices"); 1061MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Thibaut VARENE <varenet@parisc-linux.org>"); 1062