1/* 2 * MUSB OTG driver host support 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36#include <linux/module.h> 37#include <linux/kernel.h> 38#include <linux/delay.h> 39#include <linux/sched.h> 40#include <linux/slab.h> 41#include <linux/errno.h> 42#include <linux/init.h> 43#include <linux/list.h> 44 45#include "musb_core.h" 46#include "musb_host.h" 47 48 49/* MUSB HOST status 22-mar-2006 50 * 51 * - There's still lots of partial code duplication for fault paths, so 52 * they aren't handled as consistently as they need to be. 53 * 54 * - PIO mostly behaved when last tested. 55 * + including ep0, with all usbtest cases 9, 10 56 * + usbtest 14 (ep0out) doesn't seem to run at all 57 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest 58 * configurations, but otherwise double buffering passes basic tests. 59 * + for 2.6.N, for N > ~10, needs API changes for hcd framework. 60 * 61 * - DMA (CPPI) ... partially behaves, not currently recommended 62 * + about 1/15 the speed of typical EHCI implementations (PCI) 63 * + RX, all too often reqpkt seems to misbehave after tx 64 * + TX, no known issues (other than evident silicon issue) 65 * 66 * - DMA (Mentor/OMAP) ...has at least toggle update problems 67 * 68 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet 69 * starvation ... nothing yet for TX, interrupt, or bulk. 70 * 71 * - Not tested with HNP, but some SRP paths seem to behave. 72 * 73 * NOTE 24-August-2006: 74 * 75 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an 76 * extra endpoint for periodic use enabling hub + keybd + mouse. That 77 * mostly works, except that with "usbnet" it's easy to trigger cases 78 * with "ping" where RX loses. (a) ping to davinci, even "ping -f", 79 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses 80 * although ARP RX wins. (That test was done with a full speed link.) 81 */ 82 83 84/* 85 * NOTE on endpoint usage: 86 * 87 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN 88 * and OUT endpoints ... hardware is dedicated for those "async" queue(s). 89 * (Yes, bulk _could_ use more of the endpoints than that, and would even 90 * benefit from it.) 91 * 92 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints. 93 * So far that scheduling is both dumb and optimistic: the endpoint will be 94 * "claimed" until its software queue is no longer refilled. No multiplexing 95 * of transfers between endpoints, or anything clever. 96 */ 97 98 99static void musb_ep_program(struct musb *musb, u8 epnum, 100 struct urb *urb, int is_out, 101 u8 *buf, u32 offset, u32 len); 102 103/* 104 * Clear TX fifo. Needed to avoid BABBLE errors. 105 */ 106static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) 107{ 108 void __iomem *epio = ep->regs; 109 u16 csr; 110 u16 lastcsr = 0; 111 int retries = 1000; 112 113 csr = musb_readw(epio, MUSB_TXCSR); 114 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { 115 if (csr != lastcsr) 116 DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr); 117 lastcsr = csr; 118 csr |= MUSB_TXCSR_FLUSHFIFO; 119 musb_writew(epio, MUSB_TXCSR, csr); 120 csr = musb_readw(epio, MUSB_TXCSR); 121 if (WARN(retries-- < 1, 122 "Could not flush host TX%d fifo: csr: %04x\n", 123 ep->epnum, csr)) 124 return; 125 mdelay(1); 126 } 127} 128 129static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep) 130{ 131 void __iomem *epio = ep->regs; 132 u16 csr; 133 int retries = 5; 134 135 /* scrub any data left in the fifo */ 136 do { 137 csr = musb_readw(epio, MUSB_TXCSR); 138 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) 139 break; 140 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO); 141 csr = musb_readw(epio, MUSB_TXCSR); 142 udelay(10); 143 } while (--retries); 144 145 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n", 146 ep->epnum, csr); 147 148 /* and reset for the next transfer */ 149 musb_writew(epio, MUSB_TXCSR, 0); 150} 151 152/* 153 * Start transmit. Caller is responsible for locking shared resources. 154 * musb must be locked. 155 */ 156static inline void musb_h_tx_start(struct musb_hw_ep *ep) 157{ 158 u16 txcsr; 159 160 /* NOTE: no locks here; caller should lock and select EP */ 161 if (ep->epnum) { 162 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 163 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS; 164 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 165 } else { 166 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY; 167 musb_writew(ep->regs, MUSB_CSR0, txcsr); 168 } 169 170} 171 172static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep) 173{ 174 u16 txcsr; 175 176 /* NOTE: no locks here; caller should lock and select EP */ 177 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 178 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS; 179 if (is_cppi_enabled()) 180 txcsr |= MUSB_TXCSR_DMAMODE; 181 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 182} 183 184static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh) 185{ 186 if (is_in != 0 || ep->is_shared_fifo) 187 ep->in_qh = qh; 188 if (is_in == 0 || ep->is_shared_fifo) 189 ep->out_qh = qh; 190} 191 192static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in) 193{ 194 return is_in ? ep->in_qh : ep->out_qh; 195} 196 197/* 198 * Start the URB at the front of an endpoint's queue 199 * end must be claimed from the caller. 200 * 201 * Context: controller locked, irqs blocked 202 */ 203static void 204musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh) 205{ 206 u16 frame; 207 u32 len; 208 void __iomem *mbase = musb->mregs; 209 struct urb *urb = next_urb(qh); 210 void *buf = urb->transfer_buffer; 211 u32 offset = 0; 212 struct musb_hw_ep *hw_ep = qh->hw_ep; 213 unsigned pipe = urb->pipe; 214 u8 address = usb_pipedevice(pipe); 215 int epnum = hw_ep->epnum; 216 217 /* initialize software qh state */ 218 qh->offset = 0; 219 qh->segsize = 0; 220 221 /* gather right source of data */ 222 switch (qh->type) { 223 case USB_ENDPOINT_XFER_CONTROL: 224 /* control transfers always start with SETUP */ 225 is_in = 0; 226 musb->ep0_stage = MUSB_EP0_START; 227 buf = urb->setup_packet; 228 len = 8; 229 break; 230 case USB_ENDPOINT_XFER_ISOC: 231 qh->iso_idx = 0; 232 qh->frame = 0; 233 offset = urb->iso_frame_desc[0].offset; 234 len = urb->iso_frame_desc[0].length; 235 break; 236 default: /* bulk, interrupt */ 237 /* actual_length may be nonzero on retry paths */ 238 buf = urb->transfer_buffer + urb->actual_length; 239 len = urb->transfer_buffer_length - urb->actual_length; 240 } 241 242 DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n", 243 qh, urb, address, qh->epnum, 244 is_in ? "in" : "out", 245 ({char *s; switch (qh->type) { 246 case USB_ENDPOINT_XFER_CONTROL: s = ""; break; 247 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break; 248 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break; 249 default: s = "-intr"; break; 250 }; s; }), 251 epnum, buf + offset, len); 252 253 /* Configure endpoint */ 254 musb_ep_set_qh(hw_ep, is_in, qh); 255 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len); 256 257 /* transmit may have more work: start it when it is time */ 258 if (is_in) 259 return; 260 261 /* determine if the time is right for a periodic transfer */ 262 switch (qh->type) { 263 case USB_ENDPOINT_XFER_ISOC: 264 case USB_ENDPOINT_XFER_INT: 265 DBG(3, "check whether there's still time for periodic Tx\n"); 266 frame = musb_readw(mbase, MUSB_FRAME); 267 if ((urb->transfer_flags & URB_ISO_ASAP) 268 || (frame >= urb->start_frame)) { 269 /* REVISIT the SOF irq handler shouldn't duplicate 270 * this code; and we don't init urb->start_frame... 271 */ 272 qh->frame = 0; 273 goto start; 274 } else { 275 qh->frame = urb->start_frame; 276 /* enable SOF interrupt so we can count down */ 277 DBG(1, "SOF for %d\n", epnum); 278 musb_writeb(mbase, MUSB_INTRUSBE, 0xff); 279 } 280 break; 281 default: 282start: 283 DBG(4, "Start TX%d %s\n", epnum, 284 hw_ep->tx_channel ? "dma" : "pio"); 285 286 if (!hw_ep->tx_channel) 287 musb_h_tx_start(hw_ep); 288 else if (is_cppi_enabled() || tusb_dma_omap()) 289 musb_h_tx_dma_start(hw_ep); 290 } 291} 292 293/* Context: caller owns controller lock, IRQs are blocked */ 294static void musb_giveback(struct musb *musb, struct urb *urb, int status) 295__releases(musb->lock) 296__acquires(musb->lock) 297{ 298 DBG(({ int level; switch (status) { 299 case 0: 300 level = 4; 301 break; 302 /* common/boring faults */ 303 case -EREMOTEIO: 304 case -ESHUTDOWN: 305 case -ECONNRESET: 306 case -EPIPE: 307 level = 3; 308 break; 309 default: 310 level = 2; 311 break; 312 }; level; }), 313 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n", 314 urb, urb->complete, status, 315 usb_pipedevice(urb->pipe), 316 usb_pipeendpoint(urb->pipe), 317 usb_pipein(urb->pipe) ? "in" : "out", 318 urb->actual_length, urb->transfer_buffer_length 319 ); 320 321 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb); 322 spin_unlock(&musb->lock); 323 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status); 324 spin_lock(&musb->lock); 325} 326 327/* For bulk/interrupt endpoints only */ 328static inline void musb_save_toggle(struct musb_qh *qh, int is_in, 329 struct urb *urb) 330{ 331 void __iomem *epio = qh->hw_ep->regs; 332 u16 csr; 333 334 335 if (is_in) 336 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE; 337 else 338 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE; 339 340 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0); 341} 342 343/* 344 * Advance this hardware endpoint's queue, completing the specified URB and 345 * advancing to either the next URB queued to that qh, or else invalidating 346 * that qh and advancing to the next qh scheduled after the current one. 347 * 348 * Context: caller owns controller lock, IRQs are blocked 349 */ 350static void musb_advance_schedule(struct musb *musb, struct urb *urb, 351 struct musb_hw_ep *hw_ep, int is_in) 352{ 353 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in); 354 struct musb_hw_ep *ep = qh->hw_ep; 355 int ready = qh->is_ready; 356 int status; 357 358 status = (urb->status == -EINPROGRESS) ? 0 : urb->status; 359 360 /* save toggle eagerly, for paranoia */ 361 switch (qh->type) { 362 case USB_ENDPOINT_XFER_BULK: 363 case USB_ENDPOINT_XFER_INT: 364 musb_save_toggle(qh, is_in, urb); 365 break; 366 case USB_ENDPOINT_XFER_ISOC: 367 if (status == 0 && urb->error_count) 368 status = -EXDEV; 369 break; 370 } 371 372 qh->is_ready = 0; 373 musb_giveback(musb, urb, status); 374 qh->is_ready = ready; 375 376 /* reclaim resources (and bandwidth) ASAP; deschedule it, and 377 * invalidate qh as soon as list_empty(&hep->urb_list) 378 */ 379 if (list_empty(&qh->hep->urb_list)) { 380 struct list_head *head; 381 382 if (is_in) 383 ep->rx_reinit = 1; 384 else 385 ep->tx_reinit = 1; 386 387 /* Clobber old pointers to this qh */ 388 musb_ep_set_qh(ep, is_in, NULL); 389 qh->hep->hcpriv = NULL; 390 391 switch (qh->type) { 392 393 case USB_ENDPOINT_XFER_CONTROL: 394 case USB_ENDPOINT_XFER_BULK: 395 /* fifo policy for these lists, except that NAKing 396 * should rotate a qh to the end (for fairness). 397 */ 398 if (qh->mux == 1) { 399 head = qh->ring.prev; 400 list_del(&qh->ring); 401 kfree(qh); 402 qh = first_qh(head); 403 break; 404 } 405 406 case USB_ENDPOINT_XFER_ISOC: 407 case USB_ENDPOINT_XFER_INT: 408 /* this is where periodic bandwidth should be 409 * de-allocated if it's tracked and allocated; 410 * and where we'd update the schedule tree... 411 */ 412 kfree(qh); 413 qh = NULL; 414 break; 415 } 416 } 417 418 if (qh != NULL && qh->is_ready) { 419 DBG(4, "... next ep%d %cX urb %p\n", 420 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); 421 musb_start_urb(musb, is_in, qh); 422 } 423} 424 425static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) 426{ 427 /* we don't want fifo to fill itself again; 428 * ignore dma (various models), 429 * leave toggle alone (may not have been saved yet) 430 */ 431 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; 432 csr &= ~(MUSB_RXCSR_H_REQPKT 433 | MUSB_RXCSR_H_AUTOREQ 434 | MUSB_RXCSR_AUTOCLEAR); 435 436 /* write 2x to allow double buffering */ 437 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 438 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 439 440 /* flush writebuffer */ 441 return musb_readw(hw_ep->regs, MUSB_RXCSR); 442} 443 444/* 445 * PIO RX for a packet (or part of it). 446 */ 447static bool 448musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err) 449{ 450 u16 rx_count; 451 u8 *buf; 452 u16 csr; 453 bool done = false; 454 u32 length; 455 int do_flush = 0; 456 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 457 void __iomem *epio = hw_ep->regs; 458 struct musb_qh *qh = hw_ep->in_qh; 459 int pipe = urb->pipe; 460 void *buffer = urb->transfer_buffer; 461 462 /* musb_ep_select(mbase, epnum); */ 463 rx_count = musb_readw(epio, MUSB_RXCOUNT); 464 DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count, 465 urb->transfer_buffer, qh->offset, 466 urb->transfer_buffer_length); 467 468 /* unload FIFO */ 469 if (usb_pipeisoc(pipe)) { 470 int status = 0; 471 struct usb_iso_packet_descriptor *d; 472 473 if (iso_err) { 474 status = -EILSEQ; 475 urb->error_count++; 476 } 477 478 d = urb->iso_frame_desc + qh->iso_idx; 479 buf = buffer + d->offset; 480 length = d->length; 481 if (rx_count > length) { 482 if (status == 0) { 483 status = -EOVERFLOW; 484 urb->error_count++; 485 } 486 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length); 487 do_flush = 1; 488 } else 489 length = rx_count; 490 urb->actual_length += length; 491 d->actual_length = length; 492 493 d->status = status; 494 495 /* see if we are done */ 496 done = (++qh->iso_idx >= urb->number_of_packets); 497 } else { 498 /* non-isoch */ 499 buf = buffer + qh->offset; 500 length = urb->transfer_buffer_length - qh->offset; 501 if (rx_count > length) { 502 if (urb->status == -EINPROGRESS) 503 urb->status = -EOVERFLOW; 504 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length); 505 do_flush = 1; 506 } else 507 length = rx_count; 508 urb->actual_length += length; 509 qh->offset += length; 510 511 /* see if we are done */ 512 done = (urb->actual_length == urb->transfer_buffer_length) 513 || (rx_count < qh->maxpacket) 514 || (urb->status != -EINPROGRESS); 515 if (done 516 && (urb->status == -EINPROGRESS) 517 && (urb->transfer_flags & URB_SHORT_NOT_OK) 518 && (urb->actual_length 519 < urb->transfer_buffer_length)) 520 urb->status = -EREMOTEIO; 521 } 522 523 musb_read_fifo(hw_ep, length, buf); 524 525 csr = musb_readw(epio, MUSB_RXCSR); 526 csr |= MUSB_RXCSR_H_WZC_BITS; 527 if (unlikely(do_flush)) 528 musb_h_flush_rxfifo(hw_ep, csr); 529 else { 530 /* REVISIT this assumes AUTOCLEAR is never set */ 531 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); 532 if (!done) 533 csr |= MUSB_RXCSR_H_REQPKT; 534 musb_writew(epio, MUSB_RXCSR, csr); 535 } 536 537 return done; 538} 539 540/* we don't always need to reinit a given side of an endpoint... 541 * when we do, use tx/rx reinit routine and then construct a new CSR 542 * to address data toggle, NYET, and DMA or PIO. 543 * 544 * it's possible that driver bugs (especially for DMA) or aborting a 545 * transfer might have left the endpoint busier than it should be. 546 * the busy/not-empty tests are basically paranoia. 547 */ 548static void 549musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep) 550{ 551 u16 csr; 552 553 /* NOTE: we know the "rx" fifo reinit never triggers for ep0. 554 * That always uses tx_reinit since ep0 repurposes TX register 555 * offsets; the initial SETUP packet is also a kind of OUT. 556 */ 557 558 /* if programmed for Tx, put it in RX mode */ 559 if (ep->is_shared_fifo) { 560 csr = musb_readw(ep->regs, MUSB_TXCSR); 561 if (csr & MUSB_TXCSR_MODE) { 562 musb_h_tx_flush_fifo(ep); 563 csr = musb_readw(ep->regs, MUSB_TXCSR); 564 musb_writew(ep->regs, MUSB_TXCSR, 565 csr | MUSB_TXCSR_FRCDATATOG); 566 } 567 568 /* 569 * Clear the MODE bit (and everything else) to enable Rx. 570 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB. 571 */ 572 if (csr & MUSB_TXCSR_DMAMODE) 573 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE); 574 musb_writew(ep->regs, MUSB_TXCSR, 0); 575 576 /* scrub all previous state, clearing toggle */ 577 } else { 578 csr = musb_readw(ep->regs, MUSB_RXCSR); 579 if (csr & MUSB_RXCSR_RXPKTRDY) 580 WARNING("rx%d, packet/%d ready?\n", ep->epnum, 581 musb_readw(ep->regs, MUSB_RXCOUNT)); 582 583 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG); 584 } 585 586 /* target addr and (for multipoint) hub addr/port */ 587 if (musb->is_multipoint) { 588 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg); 589 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg); 590 musb_write_rxhubport(ep->target_regs, qh->h_port_reg); 591 592 } else 593 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); 594 595 /* protocol/endpoint, interval/NAKlimit, i/o size */ 596 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); 597 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); 598 /* NOTE: bulk combining rewrites high bits of maxpacket */ 599 /* Set RXMAXP with the FIFO size of the endpoint 600 * to disable double buffer mode. 601 */ 602 if (musb->hwvers < MUSB_HWVERS_2000) 603 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx); 604 else 605 musb_writew(ep->regs, MUSB_RXMAXP, 606 qh->maxpacket | ((qh->hb_mult - 1) << 11)); 607 608 ep->rx_reinit = 0; 609} 610 611static bool musb_tx_dma_program(struct dma_controller *dma, 612 struct musb_hw_ep *hw_ep, struct musb_qh *qh, 613 struct urb *urb, u32 offset, u32 length) 614{ 615 struct dma_channel *channel = hw_ep->tx_channel; 616 void __iomem *epio = hw_ep->regs; 617 u16 pkt_size = qh->maxpacket; 618 u16 csr; 619 u8 mode; 620 621#ifdef CONFIG_USB_INVENTRA_DMA 622 if (length > channel->max_len) 623 length = channel->max_len; 624 625 csr = musb_readw(epio, MUSB_TXCSR); 626 if (length > pkt_size) { 627 mode = 1; 628 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB; 629 /* autoset shouldn't be set in high bandwidth */ 630 if (qh->hb_mult == 1) 631 csr |= MUSB_TXCSR_AUTOSET; 632 } else { 633 mode = 0; 634 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE); 635 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */ 636 } 637 channel->desired_mode = mode; 638 musb_writew(epio, MUSB_TXCSR, csr); 639#else 640 if (!is_cppi_enabled() && !tusb_dma_omap()) 641 return false; 642 643 channel->actual_len = 0; 644 645 /* 646 * TX uses "RNDIS" mode automatically but needs help 647 * to identify the zero-length-final-packet case. 648 */ 649 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0; 650#endif 651 652 qh->segsize = length; 653 654 /* 655 * Ensure the data reaches to main memory before starting 656 * DMA transfer 657 */ 658 wmb(); 659 660 if (!dma->channel_program(channel, pkt_size, mode, 661 urb->transfer_dma + offset, length)) { 662 dma->channel_release(channel); 663 hw_ep->tx_channel = NULL; 664 665 csr = musb_readw(epio, MUSB_TXCSR); 666 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); 667 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS); 668 return false; 669 } 670 return true; 671} 672 673/* 674 * Program an HDRC endpoint as per the given URB 675 * Context: irqs blocked, controller lock held 676 */ 677static void musb_ep_program(struct musb *musb, u8 epnum, 678 struct urb *urb, int is_out, 679 u8 *buf, u32 offset, u32 len) 680{ 681 struct dma_controller *dma_controller; 682 struct dma_channel *dma_channel; 683 u8 dma_ok; 684 void __iomem *mbase = musb->mregs; 685 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 686 void __iomem *epio = hw_ep->regs; 687 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out); 688 u16 packet_sz = qh->maxpacket; 689 690 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s " 691 "h_addr%02x h_port%02x bytes %d\n", 692 is_out ? "-->" : "<--", 693 epnum, urb, urb->dev->speed, 694 qh->addr_reg, qh->epnum, is_out ? "out" : "in", 695 qh->h_addr_reg, qh->h_port_reg, 696 len); 697 698 musb_ep_select(mbase, epnum); 699 700 /* candidate for DMA? */ 701 dma_controller = musb->dma_controller; 702 if (is_dma_capable() && epnum && dma_controller) { 703 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; 704 if (!dma_channel) { 705 dma_channel = dma_controller->channel_alloc( 706 dma_controller, hw_ep, is_out); 707 if (is_out) 708 hw_ep->tx_channel = dma_channel; 709 else 710 hw_ep->rx_channel = dma_channel; 711 } 712 } else 713 dma_channel = NULL; 714 715 /* make sure we clear DMAEnab, autoSet bits from previous run */ 716 717 /* OUT/transmit/EP0 or IN/receive? */ 718 if (is_out) { 719 u16 csr; 720 u16 int_txe; 721 u16 load_count; 722 723 csr = musb_readw(epio, MUSB_TXCSR); 724 725 /* disable interrupt in case we flush */ 726 int_txe = musb_readw(mbase, MUSB_INTRTXE); 727 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); 728 729 /* general endpoint setup */ 730 if (epnum) { 731 /* flush all old state, set default */ 732 musb_h_tx_flush_fifo(hw_ep); 733 734 /* 735 * We must not clear the DMAMODE bit before or in 736 * the same cycle with the DMAENAB bit, so we clear 737 * the latter first... 738 */ 739 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT 740 | MUSB_TXCSR_AUTOSET 741 | MUSB_TXCSR_DMAENAB 742 | MUSB_TXCSR_FRCDATATOG 743 | MUSB_TXCSR_H_RXSTALL 744 | MUSB_TXCSR_H_ERROR 745 | MUSB_TXCSR_TXPKTRDY 746 ); 747 csr |= MUSB_TXCSR_MODE; 748 749 if (usb_gettoggle(urb->dev, qh->epnum, 1)) 750 csr |= MUSB_TXCSR_H_WR_DATATOGGLE 751 | MUSB_TXCSR_H_DATATOGGLE; 752 else 753 csr |= MUSB_TXCSR_CLRDATATOG; 754 755 musb_writew(epio, MUSB_TXCSR, csr); 756 /* REVISIT may need to clear FLUSHFIFO ... */ 757 csr &= ~MUSB_TXCSR_DMAMODE; 758 musb_writew(epio, MUSB_TXCSR, csr); 759 csr = musb_readw(epio, MUSB_TXCSR); 760 } else { 761 /* endpoint 0: just flush */ 762 musb_h_ep0_flush_fifo(hw_ep); 763 } 764 765 /* target addr and (for multipoint) hub addr/port */ 766 if (musb->is_multipoint) { 767 musb_write_txfunaddr(mbase, epnum, qh->addr_reg); 768 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg); 769 musb_write_txhubport(mbase, epnum, qh->h_port_reg); 770 } else 771 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); 772 773 /* protocol/endpoint/interval/NAKlimit */ 774 if (epnum) { 775 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); 776 if (can_bulk_split(musb, qh->type)) 777 musb_writew(epio, MUSB_TXMAXP, 778 packet_sz 779 | ((hw_ep->max_packet_sz_tx / 780 packet_sz) - 1) << 11); 781 else 782 musb_writew(epio, MUSB_TXMAXP, 783 packet_sz); 784 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg); 785 } else { 786 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg); 787 if (musb->is_multipoint) 788 musb_writeb(epio, MUSB_TYPE0, 789 qh->type_reg); 790 } 791 792 if (can_bulk_split(musb, qh->type)) 793 load_count = min((u32) hw_ep->max_packet_sz_tx, 794 len); 795 else 796 load_count = min((u32) packet_sz, len); 797 798 if (dma_channel && musb_tx_dma_program(dma_controller, 799 hw_ep, qh, urb, offset, len)) 800 load_count = 0; 801 802 if (load_count) { 803 /* PIO to load FIFO */ 804 qh->segsize = load_count; 805 musb_write_fifo(hw_ep, load_count, buf); 806 } 807 808 /* re-enable interrupt */ 809 musb_writew(mbase, MUSB_INTRTXE, int_txe); 810 811 /* IN/receive */ 812 } else { 813 u16 csr; 814 815 if (hw_ep->rx_reinit) { 816 musb_rx_reinit(musb, qh, hw_ep); 817 818 /* init new state: toggle and NYET, maybe DMA later */ 819 if (usb_gettoggle(urb->dev, qh->epnum, 0)) 820 csr = MUSB_RXCSR_H_WR_DATATOGGLE 821 | MUSB_RXCSR_H_DATATOGGLE; 822 else 823 csr = 0; 824 if (qh->type == USB_ENDPOINT_XFER_INT) 825 csr |= MUSB_RXCSR_DISNYET; 826 827 } else { 828 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 829 830 if (csr & (MUSB_RXCSR_RXPKTRDY 831 | MUSB_RXCSR_DMAENAB 832 | MUSB_RXCSR_H_REQPKT)) 833 ERR("broken !rx_reinit, ep%d csr %04x\n", 834 hw_ep->epnum, csr); 835 836 /* scrub any stale state, leaving toggle alone */ 837 csr &= MUSB_RXCSR_DISNYET; 838 } 839 840 /* kick things off */ 841 842 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) { 843 /* candidate for DMA */ 844 if (dma_channel) { 845 dma_channel->actual_len = 0L; 846 qh->segsize = len; 847 848 /* AUTOREQ is in a DMA register */ 849 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 850 csr = musb_readw(hw_ep->regs, 851 MUSB_RXCSR); 852 853 /* unless caller treats short rx transfers as 854 * errors, we dare not queue multiple transfers. 855 */ 856 dma_ok = dma_controller->channel_program( 857 dma_channel, packet_sz, 858 !(urb->transfer_flags 859 & URB_SHORT_NOT_OK), 860 urb->transfer_dma + offset, 861 qh->segsize); 862 if (!dma_ok) { 863 dma_controller->channel_release( 864 dma_channel); 865 hw_ep->rx_channel = NULL; 866 dma_channel = NULL; 867 } else 868 csr |= MUSB_RXCSR_DMAENAB; 869 } 870 } 871 872 csr |= MUSB_RXCSR_H_REQPKT; 873 DBG(7, "RXCSR%d := %04x\n", epnum, csr); 874 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 875 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 876 } 877} 878 879 880/* 881 * Service the default endpoint (ep0) as host. 882 * Return true until it's time to start the status stage. 883 */ 884static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb) 885{ 886 bool more = false; 887 u8 *fifo_dest = NULL; 888 u16 fifo_count = 0; 889 struct musb_hw_ep *hw_ep = musb->control_ep; 890 struct musb_qh *qh = hw_ep->in_qh; 891 struct usb_ctrlrequest *request; 892 893 switch (musb->ep0_stage) { 894 case MUSB_EP0_IN: 895 fifo_dest = urb->transfer_buffer + urb->actual_length; 896 fifo_count = min_t(size_t, len, urb->transfer_buffer_length - 897 urb->actual_length); 898 if (fifo_count < len) 899 urb->status = -EOVERFLOW; 900 901 musb_read_fifo(hw_ep, fifo_count, fifo_dest); 902 903 urb->actual_length += fifo_count; 904 if (len < qh->maxpacket) { 905 /* always terminate on short read; it's 906 * rarely reported as an error. 907 */ 908 } else if (urb->actual_length < 909 urb->transfer_buffer_length) 910 more = true; 911 break; 912 case MUSB_EP0_START: 913 request = (struct usb_ctrlrequest *) urb->setup_packet; 914 915 if (!request->wLength) { 916 DBG(4, "start no-DATA\n"); 917 break; 918 } else if (request->bRequestType & USB_DIR_IN) { 919 DBG(4, "start IN-DATA\n"); 920 musb->ep0_stage = MUSB_EP0_IN; 921 more = true; 922 break; 923 } else { 924 DBG(4, "start OUT-DATA\n"); 925 musb->ep0_stage = MUSB_EP0_OUT; 926 more = true; 927 } 928 /* FALLTHROUGH */ 929 case MUSB_EP0_OUT: 930 fifo_count = min_t(size_t, qh->maxpacket, 931 urb->transfer_buffer_length - 932 urb->actual_length); 933 if (fifo_count) { 934 fifo_dest = (u8 *) (urb->transfer_buffer 935 + urb->actual_length); 936 DBG(3, "Sending %d byte%s to ep0 fifo %p\n", 937 fifo_count, 938 (fifo_count == 1) ? "" : "s", 939 fifo_dest); 940 musb_write_fifo(hw_ep, fifo_count, fifo_dest); 941 942 urb->actual_length += fifo_count; 943 more = true; 944 } 945 break; 946 default: 947 ERR("bogus ep0 stage %d\n", musb->ep0_stage); 948 break; 949 } 950 951 return more; 952} 953 954/* 955 * Handle default endpoint interrupt as host. Only called in IRQ time 956 * from musb_interrupt(). 957 * 958 * called with controller irqlocked 959 */ 960irqreturn_t musb_h_ep0_irq(struct musb *musb) 961{ 962 struct urb *urb; 963 u16 csr, len; 964 int status = 0; 965 void __iomem *mbase = musb->mregs; 966 struct musb_hw_ep *hw_ep = musb->control_ep; 967 void __iomem *epio = hw_ep->regs; 968 struct musb_qh *qh = hw_ep->in_qh; 969 bool complete = false; 970 irqreturn_t retval = IRQ_NONE; 971 972 /* ep0 only has one queue, "in" */ 973 urb = next_urb(qh); 974 975 musb_ep_select(mbase, 0); 976 csr = musb_readw(epio, MUSB_CSR0); 977 len = (csr & MUSB_CSR0_RXPKTRDY) 978 ? musb_readb(epio, MUSB_COUNT0) 979 : 0; 980 981 DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", 982 csr, qh, len, urb, musb->ep0_stage); 983 984 /* if we just did status stage, we are done */ 985 if (MUSB_EP0_STATUS == musb->ep0_stage) { 986 retval = IRQ_HANDLED; 987 complete = true; 988 } 989 990 /* prepare status */ 991 if (csr & MUSB_CSR0_H_RXSTALL) { 992 DBG(6, "STALLING ENDPOINT\n"); 993 status = -EPIPE; 994 995 } else if (csr & MUSB_CSR0_H_ERROR) { 996 DBG(2, "no response, csr0 %04x\n", csr); 997 status = -EPROTO; 998 999 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { 1000 DBG(2, "control NAK timeout\n"); 1001 1002 /* NOTE: this code path would be a good place to PAUSE a 1003 * control transfer, if another one is queued, so that 1004 * ep0 is more likely to stay busy. That's already done 1005 * for bulk RX transfers. 1006 * 1007 * if (qh->ring.next != &musb->control), then 1008 * we have a candidate... NAKing is *NOT* an error 1009 */ 1010 musb_writew(epio, MUSB_CSR0, 0); 1011 retval = IRQ_HANDLED; 1012 } 1013 1014 if (status) { 1015 DBG(6, "aborting\n"); 1016 retval = IRQ_HANDLED; 1017 if (urb) 1018 urb->status = status; 1019 complete = true; 1020 1021 /* use the proper sequence to abort the transfer */ 1022 if (csr & MUSB_CSR0_H_REQPKT) { 1023 csr &= ~MUSB_CSR0_H_REQPKT; 1024 musb_writew(epio, MUSB_CSR0, csr); 1025 csr &= ~MUSB_CSR0_H_NAKTIMEOUT; 1026 musb_writew(epio, MUSB_CSR0, csr); 1027 } else { 1028 musb_h_ep0_flush_fifo(hw_ep); 1029 } 1030 1031 musb_writeb(epio, MUSB_NAKLIMIT0, 0); 1032 1033 /* clear it */ 1034 musb_writew(epio, MUSB_CSR0, 0); 1035 } 1036 1037 if (unlikely(!urb)) { 1038 /* stop endpoint since we have no place for its data, this 1039 * SHOULD NEVER HAPPEN! */ 1040 ERR("no URB for end 0\n"); 1041 1042 musb_h_ep0_flush_fifo(hw_ep); 1043 goto done; 1044 } 1045 1046 if (!complete) { 1047 /* call common logic and prepare response */ 1048 if (musb_h_ep0_continue(musb, len, urb)) { 1049 /* more packets required */ 1050 csr = (MUSB_EP0_IN == musb->ep0_stage) 1051 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY; 1052 } else { 1053 /* data transfer complete; perform status phase */ 1054 if (usb_pipeout(urb->pipe) 1055 || !urb->transfer_buffer_length) 1056 csr = MUSB_CSR0_H_STATUSPKT 1057 | MUSB_CSR0_H_REQPKT; 1058 else 1059 csr = MUSB_CSR0_H_STATUSPKT 1060 | MUSB_CSR0_TXPKTRDY; 1061 1062 /* flag status stage */ 1063 musb->ep0_stage = MUSB_EP0_STATUS; 1064 1065 DBG(5, "ep0 STATUS, csr %04x\n", csr); 1066 1067 } 1068 musb_writew(epio, MUSB_CSR0, csr); 1069 retval = IRQ_HANDLED; 1070 } else 1071 musb->ep0_stage = MUSB_EP0_IDLE; 1072 1073 /* call completion handler if done */ 1074 if (complete) 1075 musb_advance_schedule(musb, urb, hw_ep, 1); 1076done: 1077 return retval; 1078} 1079 1080 1081#ifdef CONFIG_USB_INVENTRA_DMA 1082 1083/* Host side TX (OUT) using Mentor DMA works as follows: 1084 submit_urb -> 1085 - if queue was empty, Program Endpoint 1086 - ... which starts DMA to fifo in mode 1 or 0 1087 1088 DMA Isr (transfer complete) -> TxAvail() 1089 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens 1090 only in musb_cleanup_urb) 1091 - TxPktRdy has to be set in mode 0 or for 1092 short packets in mode 1. 1093*/ 1094 1095#endif 1096 1097/* Service a Tx-Available or dma completion irq for the endpoint */ 1098void musb_host_tx(struct musb *musb, u8 epnum) 1099{ 1100 int pipe; 1101 bool done = false; 1102 u16 tx_csr; 1103 size_t length = 0; 1104 size_t offset = 0; 1105 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1106 void __iomem *epio = hw_ep->regs; 1107 struct musb_qh *qh = hw_ep->out_qh; 1108 struct urb *urb = next_urb(qh); 1109 u32 status = 0; 1110 void __iomem *mbase = musb->mregs; 1111 struct dma_channel *dma; 1112 1113 musb_ep_select(mbase, epnum); 1114 tx_csr = musb_readw(epio, MUSB_TXCSR); 1115 1116 /* with CPPI, DMA sometimes triggers "extra" irqs */ 1117 if (!urb) { 1118 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1119 return; 1120 } 1121 1122 pipe = urb->pipe; 1123 dma = is_dma_capable() ? hw_ep->tx_channel : NULL; 1124 DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, 1125 dma ? ", dma" : ""); 1126 1127 /* check for errors */ 1128 if (tx_csr & MUSB_TXCSR_H_RXSTALL) { 1129 /* dma was disabled, fifo flushed */ 1130 DBG(3, "TX end %d stall\n", epnum); 1131 1132 /* stall; record URB status */ 1133 status = -EPIPE; 1134 1135 } else if (tx_csr & MUSB_TXCSR_H_ERROR) { 1136 /* (NON-ISO) dma was disabled, fifo flushed */ 1137 DBG(3, "TX 3strikes on ep=%d\n", epnum); 1138 1139 status = -ETIMEDOUT; 1140 1141 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { 1142 DBG(6, "TX end=%d device not responding\n", epnum); 1143 1144 /* NOTE: this code path would be a good place to PAUSE a 1145 * transfer, if there's some other (nonperiodic) tx urb 1146 * that could use this fifo. (dma complicates it...) 1147 * That's already done for bulk RX transfers. 1148 * 1149 * if (bulk && qh->ring.next != &musb->out_bulk), then 1150 * we have a candidate... NAKing is *NOT* an error 1151 */ 1152 musb_ep_select(mbase, epnum); 1153 musb_writew(epio, MUSB_TXCSR, 1154 MUSB_TXCSR_H_WZC_BITS 1155 | MUSB_TXCSR_TXPKTRDY); 1156 return; 1157 } 1158 1159 if (status) { 1160 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1161 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1162 (void) musb->dma_controller->channel_abort(dma); 1163 } 1164 1165 /* do the proper sequence to abort the transfer in the 1166 * usb core; the dma engine should already be stopped. 1167 */ 1168 musb_h_tx_flush_fifo(hw_ep); 1169 tx_csr &= ~(MUSB_TXCSR_AUTOSET 1170 | MUSB_TXCSR_DMAENAB 1171 | MUSB_TXCSR_H_ERROR 1172 | MUSB_TXCSR_H_RXSTALL 1173 | MUSB_TXCSR_H_NAKTIMEOUT 1174 ); 1175 1176 musb_ep_select(mbase, epnum); 1177 musb_writew(epio, MUSB_TXCSR, tx_csr); 1178 /* REVISIT may need to clear FLUSHFIFO ... */ 1179 musb_writew(epio, MUSB_TXCSR, tx_csr); 1180 musb_writeb(epio, MUSB_TXINTERVAL, 0); 1181 1182 done = true; 1183 } 1184 1185 /* second cppi case */ 1186 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1187 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1188 return; 1189 } 1190 1191 if (is_dma_capable() && dma && !status) { 1192 /* 1193 * DMA has completed. But if we're using DMA mode 1 (multi 1194 * packet DMA), we need a terminal TXPKTRDY interrupt before 1195 * we can consider this transfer completed, lest we trash 1196 * its last packet when writing the next URB's data. So we 1197 * switch back to mode 0 to get that interrupt; we'll come 1198 * back here once it happens. 1199 */ 1200 if (tx_csr & MUSB_TXCSR_DMAMODE) { 1201 /* 1202 * We shouldn't clear DMAMODE with DMAENAB set; so 1203 * clear them in a safe order. That should be OK 1204 * once TXPKTRDY has been set (and I've never seen 1205 * it being 0 at this moment -- DMA interrupt latency 1206 * is significant) but if it hasn't been then we have 1207 * no choice but to stop being polite and ignore the 1208 * programmer's guide... :-) 1209 * 1210 * Note that we must write TXCSR with TXPKTRDY cleared 1211 * in order not to re-trigger the packet send (this bit 1212 * can't be cleared by CPU), and there's another caveat: 1213 * TXPKTRDY may be set shortly and then cleared in the 1214 * double-buffered FIFO mode, so we do an extra TXCSR 1215 * read for debouncing... 1216 */ 1217 tx_csr &= musb_readw(epio, MUSB_TXCSR); 1218 if (tx_csr & MUSB_TXCSR_TXPKTRDY) { 1219 tx_csr &= ~(MUSB_TXCSR_DMAENAB | 1220 MUSB_TXCSR_TXPKTRDY); 1221 musb_writew(epio, MUSB_TXCSR, 1222 tx_csr | MUSB_TXCSR_H_WZC_BITS); 1223 } 1224 tx_csr &= ~(MUSB_TXCSR_DMAMODE | 1225 MUSB_TXCSR_TXPKTRDY); 1226 musb_writew(epio, MUSB_TXCSR, 1227 tx_csr | MUSB_TXCSR_H_WZC_BITS); 1228 1229 /* 1230 * There is no guarantee that we'll get an interrupt 1231 * after clearing DMAMODE as we might have done this 1232 * too late (after TXPKTRDY was cleared by controller). 1233 * Re-read TXCSR as we have spoiled its previous value. 1234 */ 1235 tx_csr = musb_readw(epio, MUSB_TXCSR); 1236 } 1237 1238 /* 1239 * We may get here from a DMA completion or TXPKTRDY interrupt. 1240 * In any case, we must check the FIFO status here and bail out 1241 * only if the FIFO still has data -- that should prevent the 1242 * "missed" TXPKTRDY interrupts and deal with double-buffered 1243 * FIFO mode too... 1244 */ 1245 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) { 1246 DBG(2, "DMA complete but packet still in FIFO, " 1247 "CSR %04x\n", tx_csr); 1248 return; 1249 } 1250 } 1251 1252 if (!status || dma || usb_pipeisoc(pipe)) { 1253 if (dma) 1254 length = dma->actual_len; 1255 else 1256 length = qh->segsize; 1257 qh->offset += length; 1258 1259 if (usb_pipeisoc(pipe)) { 1260 struct usb_iso_packet_descriptor *d; 1261 1262 d = urb->iso_frame_desc + qh->iso_idx; 1263 d->actual_length = length; 1264 d->status = status; 1265 if (++qh->iso_idx >= urb->number_of_packets) { 1266 done = true; 1267 } else { 1268 d++; 1269 offset = d->offset; 1270 length = d->length; 1271 } 1272 } else if (dma) { 1273 done = true; 1274 } else { 1275 /* see if we need to send more data, or ZLP */ 1276 if (qh->segsize < qh->maxpacket) 1277 done = true; 1278 else if (qh->offset == urb->transfer_buffer_length 1279 && !(urb->transfer_flags 1280 & URB_ZERO_PACKET)) 1281 done = true; 1282 if (!done) { 1283 offset = qh->offset; 1284 length = urb->transfer_buffer_length - offset; 1285 } 1286 } 1287 } 1288 1289 /* urb->status != -EINPROGRESS means request has been faulted, 1290 * so we must abort this transfer after cleanup 1291 */ 1292 if (urb->status != -EINPROGRESS) { 1293 done = true; 1294 if (status == 0) 1295 status = urb->status; 1296 } 1297 1298 if (done) { 1299 /* set status */ 1300 urb->status = status; 1301 urb->actual_length = qh->offset; 1302 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); 1303 return; 1304 } else if (usb_pipeisoc(pipe) && dma) { 1305 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, 1306 offset, length)) { 1307 if (is_cppi_enabled() || tusb_dma_omap()) 1308 musb_h_tx_dma_start(hw_ep); 1309 return; 1310 } 1311 } else if (tx_csr & MUSB_TXCSR_DMAENAB) { 1312 DBG(1, "not complete, but DMA enabled?\n"); 1313 return; 1314 } 1315 1316 /* 1317 * PIO: start next packet in this URB. 1318 * 1319 * REVISIT: some docs say that when hw_ep->tx_double_buffered, 1320 * (and presumably, FIFO is not half-full) we should write *two* 1321 * packets before updating TXCSR; other docs disagree... 1322 */ 1323 if (length > qh->maxpacket) 1324 length = qh->maxpacket; 1325 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); 1326 qh->segsize = length; 1327 1328 musb_ep_select(mbase, epnum); 1329 musb_writew(epio, MUSB_TXCSR, 1330 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY); 1331} 1332 1333 1334#ifdef CONFIG_USB_INVENTRA_DMA 1335 1336/* Host side RX (IN) using Mentor DMA works as follows: 1337 submit_urb -> 1338 - if queue was empty, ProgramEndpoint 1339 - first IN token is sent out (by setting ReqPkt) 1340 LinuxIsr -> RxReady() 1341 /\ => first packet is received 1342 | - Set in mode 0 (DmaEnab, ~ReqPkt) 1343 | -> DMA Isr (transfer complete) -> RxReady() 1344 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab) 1345 | - if urb not complete, send next IN token (ReqPkt) 1346 | | else complete urb. 1347 | | 1348 --------------------------- 1349 * 1350 * Nuances of mode 1: 1351 * For short packets, no ack (+RxPktRdy) is sent automatically 1352 * (even if AutoClear is ON) 1353 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent 1354 * automatically => major problem, as collecting the next packet becomes 1355 * difficult. Hence mode 1 is not used. 1356 * 1357 * REVISIT 1358 * All we care about at this driver level is that 1359 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty; 1360 * (b) termination conditions are: short RX, or buffer full; 1361 * (c) fault modes include 1362 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO. 1363 * (and that endpoint's dma queue stops immediately) 1364 * - overflow (full, PLUS more bytes in the terminal packet) 1365 * 1366 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would 1367 * thus be a great candidate for using mode 1 ... for all but the 1368 * last packet of one URB's transfer. 1369 */ 1370 1371#endif 1372 1373/* Schedule next QH from musb->in_bulk and move the current qh to 1374 * the end; avoids starvation for other endpoints. 1375 */ 1376static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep) 1377{ 1378 struct dma_channel *dma; 1379 struct urb *urb; 1380 void __iomem *mbase = musb->mregs; 1381 void __iomem *epio = ep->regs; 1382 struct musb_qh *cur_qh, *next_qh; 1383 u16 rx_csr; 1384 1385 musb_ep_select(mbase, ep->epnum); 1386 dma = is_dma_capable() ? ep->rx_channel : NULL; 1387 1388 /* clear nak timeout bit */ 1389 rx_csr = musb_readw(epio, MUSB_RXCSR); 1390 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 1391 rx_csr &= ~MUSB_RXCSR_DATAERROR; 1392 musb_writew(epio, MUSB_RXCSR, rx_csr); 1393 1394 cur_qh = first_qh(&musb->in_bulk); 1395 if (cur_qh) { 1396 urb = next_urb(cur_qh); 1397 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1398 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1399 musb->dma_controller->channel_abort(dma); 1400 urb->actual_length += dma->actual_len; 1401 dma->actual_len = 0L; 1402 } 1403 musb_save_toggle(cur_qh, 1, urb); 1404 1405 /* move cur_qh to end of queue */ 1406 list_move_tail(&cur_qh->ring, &musb->in_bulk); 1407 1408 /* get the next qh from musb->in_bulk */ 1409 next_qh = first_qh(&musb->in_bulk); 1410 1411 /* set rx_reinit and schedule the next qh */ 1412 ep->rx_reinit = 1; 1413 musb_start_urb(musb, 1, next_qh); 1414 } 1415} 1416 1417/* 1418 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso, 1419 * and high-bandwidth IN transfer cases. 1420 */ 1421void musb_host_rx(struct musb *musb, u8 epnum) 1422{ 1423 struct urb *urb; 1424 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1425 void __iomem *epio = hw_ep->regs; 1426 struct musb_qh *qh = hw_ep->in_qh; 1427 size_t xfer_len; 1428 void __iomem *mbase = musb->mregs; 1429 int pipe; 1430 u16 rx_csr, val; 1431 bool iso_err = false; 1432 bool done = false; 1433 u32 status; 1434 struct dma_channel *dma; 1435 1436 musb_ep_select(mbase, epnum); 1437 1438 urb = next_urb(qh); 1439 dma = is_dma_capable() ? hw_ep->rx_channel : NULL; 1440 status = 0; 1441 xfer_len = 0; 1442 1443 rx_csr = musb_readw(epio, MUSB_RXCSR); 1444 val = rx_csr; 1445 1446 if (unlikely(!urb)) { 1447 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least 1448 * usbtest #11 (unlinks) triggers it regularly, sometimes 1449 * with fifo full. (Only with DMA??) 1450 */ 1451 DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, 1452 musb_readw(epio, MUSB_RXCOUNT)); 1453 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1454 return; 1455 } 1456 1457 pipe = urb->pipe; 1458 1459 DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n", 1460 epnum, rx_csr, urb->actual_length, 1461 dma ? dma->actual_len : 0); 1462 1463 /* check for errors, concurrent stall & unlink is not really 1464 * handled yet! */ 1465 if (rx_csr & MUSB_RXCSR_H_RXSTALL) { 1466 DBG(3, "RX end %d STALL\n", epnum); 1467 1468 /* stall; record URB status */ 1469 status = -EPIPE; 1470 1471 } else if (rx_csr & MUSB_RXCSR_H_ERROR) { 1472 DBG(3, "end %d RX proto error\n", epnum); 1473 1474 status = -EPROTO; 1475 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1476 1477 } else if (rx_csr & MUSB_RXCSR_DATAERROR) { 1478 1479 if (USB_ENDPOINT_XFER_ISOC != qh->type) { 1480 DBG(6, "RX end %d NAK timeout\n", epnum); 1481 1482 /* NOTE: NAKing is *NOT* an error, so we want to 1483 * continue. Except ... if there's a request for 1484 * another QH, use that instead of starving it. 1485 * 1486 * Devices like Ethernet and serial adapters keep 1487 * reads posted at all times, which will starve 1488 * other devices without this logic. 1489 */ 1490 if (usb_pipebulk(urb->pipe) 1491 && qh->mux == 1 1492 && !list_is_singular(&musb->in_bulk)) { 1493 musb_bulk_rx_nak_timeout(musb, hw_ep); 1494 return; 1495 } 1496 musb_ep_select(mbase, epnum); 1497 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 1498 rx_csr &= ~MUSB_RXCSR_DATAERROR; 1499 musb_writew(epio, MUSB_RXCSR, rx_csr); 1500 1501 goto finish; 1502 } else { 1503 DBG(4, "RX end %d ISO data error\n", epnum); 1504 /* packet error reported later */ 1505 iso_err = true; 1506 } 1507 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) { 1508 DBG(3, "end %d high bandwidth incomplete ISO packet RX\n", 1509 epnum); 1510 status = -EPROTO; 1511 } 1512 1513 /* faults abort the transfer */ 1514 if (status) { 1515 /* clean up dma and collect transfer count */ 1516 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1517 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1518 (void) musb->dma_controller->channel_abort(dma); 1519 xfer_len = dma->actual_len; 1520 } 1521 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1522 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1523 done = true; 1524 goto finish; 1525 } 1526 1527 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) { 1528 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */ 1529 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); 1530 goto finish; 1531 } 1532 1533 /* thorough shutdown for now ... given more precise fault handling 1534 * and better queueing support, we might keep a DMA pipeline going 1535 * while processing this irq for earlier completions. 1536 */ 1537 1538 1539#ifndef CONFIG_USB_INVENTRA_DMA 1540 if (rx_csr & MUSB_RXCSR_H_REQPKT) { 1541 /* REVISIT this happened for a while on some short reads... 1542 * the cleanup still needs investigation... looks bad... 1543 * and also duplicates dma cleanup code above ... plus, 1544 * shouldn't this be the "half full" double buffer case? 1545 */ 1546 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1547 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1548 (void) musb->dma_controller->channel_abort(dma); 1549 xfer_len = dma->actual_len; 1550 done = true; 1551 } 1552 1553 DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr, 1554 xfer_len, dma ? ", dma" : ""); 1555 rx_csr &= ~MUSB_RXCSR_H_REQPKT; 1556 1557 musb_ep_select(mbase, epnum); 1558 musb_writew(epio, MUSB_RXCSR, 1559 MUSB_RXCSR_H_WZC_BITS | rx_csr); 1560 } 1561#endif 1562 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) { 1563 xfer_len = dma->actual_len; 1564 1565 val &= ~(MUSB_RXCSR_DMAENAB 1566 | MUSB_RXCSR_H_AUTOREQ 1567 | MUSB_RXCSR_AUTOCLEAR 1568 | MUSB_RXCSR_RXPKTRDY); 1569 musb_writew(hw_ep->regs, MUSB_RXCSR, val); 1570 1571#ifdef CONFIG_USB_INVENTRA_DMA 1572 if (usb_pipeisoc(pipe)) { 1573 struct usb_iso_packet_descriptor *d; 1574 1575 d = urb->iso_frame_desc + qh->iso_idx; 1576 d->actual_length = xfer_len; 1577 1578 /* even if there was an error, we did the dma 1579 * for iso_frame_desc->length 1580 */ 1581 if (d->status != EILSEQ && d->status != -EOVERFLOW) 1582 d->status = 0; 1583 1584 if (++qh->iso_idx >= urb->number_of_packets) 1585 done = true; 1586 else 1587 done = false; 1588 1589 } else { 1590 /* done if urb buffer is full or short packet is recd */ 1591 done = (urb->actual_length + xfer_len >= 1592 urb->transfer_buffer_length 1593 || dma->actual_len < qh->maxpacket); 1594 } 1595 1596 /* send IN token for next packet, without AUTOREQ */ 1597 if (!done) { 1598 val |= MUSB_RXCSR_H_REQPKT; 1599 musb_writew(epio, MUSB_RXCSR, 1600 MUSB_RXCSR_H_WZC_BITS | val); 1601 } 1602 1603 DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum, 1604 done ? "off" : "reset", 1605 musb_readw(epio, MUSB_RXCSR), 1606 musb_readw(epio, MUSB_RXCOUNT)); 1607#else 1608 done = true; 1609#endif 1610 } else if (urb->status == -EINPROGRESS) { 1611 /* if no errors, be sure a packet is ready for unloading */ 1612 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) { 1613 status = -EPROTO; 1614 ERR("Rx interrupt with no errors or packet!\n"); 1615 1616 1617/* SCRUB (RX) */ 1618 /* do the proper sequence to abort the transfer */ 1619 musb_ep_select(mbase, epnum); 1620 val &= ~MUSB_RXCSR_H_REQPKT; 1621 musb_writew(epio, MUSB_RXCSR, val); 1622 goto finish; 1623 } 1624 1625 /* we are expecting IN packets */ 1626#ifdef CONFIG_USB_INVENTRA_DMA 1627 if (dma) { 1628 struct dma_controller *c; 1629 u16 rx_count; 1630 int ret, length; 1631 dma_addr_t buf; 1632 1633 rx_count = musb_readw(epio, MUSB_RXCOUNT); 1634 1635 DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n", 1636 epnum, rx_count, 1637 urb->transfer_dma 1638 + urb->actual_length, 1639 qh->offset, 1640 urb->transfer_buffer_length); 1641 1642 c = musb->dma_controller; 1643 1644 if (usb_pipeisoc(pipe)) { 1645 int d_status = 0; 1646 struct usb_iso_packet_descriptor *d; 1647 1648 d = urb->iso_frame_desc + qh->iso_idx; 1649 1650 if (iso_err) { 1651 d_status = -EILSEQ; 1652 urb->error_count++; 1653 } 1654 if (rx_count > d->length) { 1655 if (d_status == 0) { 1656 d_status = -EOVERFLOW; 1657 urb->error_count++; 1658 } 1659 DBG(2, "** OVERFLOW %d into %d\n",\ 1660 rx_count, d->length); 1661 1662 length = d->length; 1663 } else 1664 length = rx_count; 1665 d->status = d_status; 1666 buf = urb->transfer_dma + d->offset; 1667 } else { 1668 length = rx_count; 1669 buf = urb->transfer_dma + 1670 urb->actual_length; 1671 } 1672 1673 dma->desired_mode = 0; 1674#ifdef USE_MODE1 1675 /* because of the issue below, mode 1 will 1676 * only rarely behave with correct semantics. 1677 */ 1678 if ((urb->transfer_flags & 1679 URB_SHORT_NOT_OK) 1680 && (urb->transfer_buffer_length - 1681 urb->actual_length) 1682 > qh->maxpacket) 1683 dma->desired_mode = 1; 1684 if (rx_count < hw_ep->max_packet_sz_rx) { 1685 length = rx_count; 1686 dma->desired_mode = 0; 1687 } else { 1688 length = urb->transfer_buffer_length; 1689 } 1690#endif 1691 1692/* Disadvantage of using mode 1: 1693 * It's basically usable only for mass storage class; essentially all 1694 * other protocols also terminate transfers on short packets. 1695 * 1696 * Details: 1697 * An extra IN token is sent at the end of the transfer (due to AUTOREQ) 1698 * If you try to use mode 1 for (transfer_buffer_length - 512), and try 1699 * to use the extra IN token to grab the last packet using mode 0, then 1700 * the problem is that you cannot be sure when the device will send the 1701 * last packet and RxPktRdy set. Sometimes the packet is recd too soon 1702 * such that it gets lost when RxCSR is re-set at the end of the mode 1 1703 * transfer, while sometimes it is recd just a little late so that if you 1704 * try to configure for mode 0 soon after the mode 1 transfer is 1705 * completed, you will find rxcount 0. Okay, so you might think why not 1706 * wait for an interrupt when the pkt is recd. Well, you won't get any! 1707 */ 1708 1709 val = musb_readw(epio, MUSB_RXCSR); 1710 val &= ~MUSB_RXCSR_H_REQPKT; 1711 1712 if (dma->desired_mode == 0) 1713 val &= ~MUSB_RXCSR_H_AUTOREQ; 1714 else 1715 val |= MUSB_RXCSR_H_AUTOREQ; 1716 val |= MUSB_RXCSR_DMAENAB; 1717 1718 /* autoclear shouldn't be set in high bandwidth */ 1719 if (qh->hb_mult == 1) 1720 val |= MUSB_RXCSR_AUTOCLEAR; 1721 1722 musb_writew(epio, MUSB_RXCSR, 1723 MUSB_RXCSR_H_WZC_BITS | val); 1724 1725 /* REVISIT if when actual_length != 0, 1726 * transfer_buffer_length needs to be 1727 * adjusted first... 1728 */ 1729 ret = c->channel_program( 1730 dma, qh->maxpacket, 1731 dma->desired_mode, buf, length); 1732 1733 if (!ret) { 1734 c->channel_release(dma); 1735 hw_ep->rx_channel = NULL; 1736 dma = NULL; 1737 /* REVISIT reset CSR */ 1738 } 1739 } 1740#endif /* Mentor DMA */ 1741 1742 if (!dma) { 1743 done = musb_host_packet_rx(musb, urb, 1744 epnum, iso_err); 1745 DBG(6, "read %spacket\n", done ? "last " : ""); 1746 } 1747 } 1748 1749finish: 1750 urb->actual_length += xfer_len; 1751 qh->offset += xfer_len; 1752 if (done) { 1753 if (urb->status == -EINPROGRESS) 1754 urb->status = status; 1755 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); 1756 } 1757} 1758 1759/* schedule nodes correspond to peripheral endpoints, like an OHCI QH. 1760 * the software schedule associates multiple such nodes with a given 1761 * host side hardware endpoint + direction; scheduling may activate 1762 * that hardware endpoint. 1763 */ 1764static int musb_schedule( 1765 struct musb *musb, 1766 struct musb_qh *qh, 1767 int is_in) 1768{ 1769 int idle; 1770 int best_diff; 1771 int best_end, epnum; 1772 struct musb_hw_ep *hw_ep = NULL; 1773 struct list_head *head = NULL; 1774 u8 toggle; 1775 u8 txtype; 1776 struct urb *urb = next_urb(qh); 1777 1778 /* use fixed hardware for control and bulk */ 1779 if (qh->type == USB_ENDPOINT_XFER_CONTROL) { 1780 head = &musb->control; 1781 hw_ep = musb->control_ep; 1782 goto success; 1783 } 1784 1785 /* else, periodic transfers get muxed to other endpoints */ 1786 1787 /* 1788 * We know this qh hasn't been scheduled, so all we need to do 1789 * is choose which hardware endpoint to put it on ... 1790 * 1791 * REVISIT what we really want here is a regular schedule tree 1792 * like e.g. OHCI uses. 1793 */ 1794 best_diff = 4096; 1795 best_end = -1; 1796 1797 for (epnum = 1, hw_ep = musb->endpoints + 1; 1798 epnum < musb->nr_endpoints; 1799 epnum++, hw_ep++) { 1800 int diff; 1801 1802 if (musb_ep_get_qh(hw_ep, is_in) != NULL) 1803 continue; 1804 1805 if (hw_ep == musb->bulk_ep) 1806 continue; 1807 1808 if (is_in) 1809 diff = hw_ep->max_packet_sz_rx; 1810 else 1811 diff = hw_ep->max_packet_sz_tx; 1812 diff -= (qh->maxpacket * qh->hb_mult); 1813 1814 if (diff >= 0 && best_diff > diff) { 1815 1816 /* 1817 * Mentor controller has a bug in that if we schedule 1818 * a BULK Tx transfer on an endpoint that had earlier 1819 * handled ISOC then the BULK transfer has to start on 1820 * a zero toggle. If the BULK transfer starts on a 1 1821 * toggle then this transfer will fail as the mentor 1822 * controller starts the Bulk transfer on a 0 toggle 1823 * irrespective of the programming of the toggle bits 1824 * in the TXCSR register. Check for this condition 1825 * while allocating the EP for a Tx Bulk transfer. If 1826 * so skip this EP. 1827 */ 1828 hw_ep = musb->endpoints + epnum; 1829 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in); 1830 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE) 1831 >> 4) & 0x3; 1832 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) && 1833 toggle && (txtype == USB_ENDPOINT_XFER_ISOC)) 1834 continue; 1835 1836 best_diff = diff; 1837 best_end = epnum; 1838 } 1839 } 1840 /* use bulk reserved ep1 if no other ep is free */ 1841 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { 1842 hw_ep = musb->bulk_ep; 1843 if (is_in) 1844 head = &musb->in_bulk; 1845 else 1846 head = &musb->out_bulk; 1847 1848 /* Enable bulk RX NAK timeout scheme when bulk requests are 1849 * multiplexed. This scheme doen't work in high speed to full 1850 * speed scenario as NAK interrupts are not coming from a 1851 * full speed device connected to a high speed device. 1852 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and 1853 * 4 (8 frame or 8ms) for FS device. 1854 */ 1855 if (is_in && qh->dev) 1856 qh->intv_reg = 1857 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4; 1858 goto success; 1859 } else if (best_end < 0) { 1860 return -ENOSPC; 1861 } 1862 1863 idle = 1; 1864 qh->mux = 0; 1865 hw_ep = musb->endpoints + best_end; 1866 DBG(4, "qh %p periodic slot %d\n", qh, best_end); 1867success: 1868 if (head) { 1869 idle = list_empty(head); 1870 list_add_tail(&qh->ring, head); 1871 qh->mux = 1; 1872 } 1873 qh->hw_ep = hw_ep; 1874 qh->hep->hcpriv = qh; 1875 if (idle) 1876 musb_start_urb(musb, is_in, qh); 1877 return 0; 1878} 1879 1880static int musb_urb_enqueue( 1881 struct usb_hcd *hcd, 1882 struct urb *urb, 1883 gfp_t mem_flags) 1884{ 1885 unsigned long flags; 1886 struct musb *musb = hcd_to_musb(hcd); 1887 struct usb_host_endpoint *hep = urb->ep; 1888 struct musb_qh *qh; 1889 struct usb_endpoint_descriptor *epd = &hep->desc; 1890 int ret; 1891 unsigned type_reg; 1892 unsigned interval; 1893 1894 /* host role must be active */ 1895 if (!is_host_active(musb) || !musb->is_active) 1896 return -ENODEV; 1897 1898 spin_lock_irqsave(&musb->lock, flags); 1899 ret = usb_hcd_link_urb_to_ep(hcd, urb); 1900 qh = ret ? NULL : hep->hcpriv; 1901 if (qh) 1902 urb->hcpriv = qh; 1903 spin_unlock_irqrestore(&musb->lock, flags); 1904 1905 /* DMA mapping was already done, if needed, and this urb is on 1906 * hep->urb_list now ... so we're done, unless hep wasn't yet 1907 * scheduled onto a live qh. 1908 * 1909 * REVISIT best to keep hep->hcpriv valid until the endpoint gets 1910 * disabled, testing for empty qh->ring and avoiding qh setup costs 1911 * except for the first urb queued after a config change. 1912 */ 1913 if (qh || ret) 1914 return ret; 1915 1916 /* Allocate and initialize qh, minimizing the work done each time 1917 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it. 1918 * 1919 * REVISIT consider a dedicated qh kmem_cache, so it's harder 1920 * for bugs in other kernel code to break this driver... 1921 */ 1922 qh = kzalloc(sizeof *qh, mem_flags); 1923 if (!qh) { 1924 spin_lock_irqsave(&musb->lock, flags); 1925 usb_hcd_unlink_urb_from_ep(hcd, urb); 1926 spin_unlock_irqrestore(&musb->lock, flags); 1927 return -ENOMEM; 1928 } 1929 1930 qh->hep = hep; 1931 qh->dev = urb->dev; 1932 INIT_LIST_HEAD(&qh->ring); 1933 qh->is_ready = 1; 1934 1935 qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize); 1936 qh->type = usb_endpoint_type(epd); 1937 1938 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier. 1939 * Some musb cores don't support high bandwidth ISO transfers; and 1940 * we don't (yet!) support high bandwidth interrupt transfers. 1941 */ 1942 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03); 1943 if (qh->hb_mult > 1) { 1944 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC); 1945 1946 if (ok) 1947 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx) 1948 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx); 1949 if (!ok) { 1950 ret = -EMSGSIZE; 1951 goto done; 1952 } 1953 qh->maxpacket &= 0x7ff; 1954 } 1955 1956 qh->epnum = usb_endpoint_num(epd); 1957 1958 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */ 1959 qh->addr_reg = (u8) usb_pipedevice(urb->pipe); 1960 1961 /* precompute rxtype/txtype/type0 register */ 1962 type_reg = (qh->type << 4) | qh->epnum; 1963 switch (urb->dev->speed) { 1964 case USB_SPEED_LOW: 1965 type_reg |= 0xc0; 1966 break; 1967 case USB_SPEED_FULL: 1968 type_reg |= 0x80; 1969 break; 1970 default: 1971 type_reg |= 0x40; 1972 } 1973 qh->type_reg = type_reg; 1974 1975 /* Precompute RXINTERVAL/TXINTERVAL register */ 1976 switch (qh->type) { 1977 case USB_ENDPOINT_XFER_INT: 1978 /* 1979 * Full/low speeds use the linear encoding, 1980 * high speed uses the logarithmic encoding. 1981 */ 1982 if (urb->dev->speed <= USB_SPEED_FULL) { 1983 interval = max_t(u8, epd->bInterval, 1); 1984 break; 1985 } 1986 /* FALLTHROUGH */ 1987 case USB_ENDPOINT_XFER_ISOC: 1988 /* ISO always uses logarithmic encoding */ 1989 interval = min_t(u8, epd->bInterval, 16); 1990 break; 1991 default: 1992 /* REVISIT we actually want to use NAK limits, hinting to the 1993 * transfer scheduling logic to try some other qh, e.g. try 1994 * for 2 msec first: 1995 * 1996 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2; 1997 * 1998 * The downside of disabling this is that transfer scheduling 1999 * gets VERY unfair for nonperiodic transfers; a misbehaving 2000 * peripheral could make that hurt. That's perfectly normal 2001 * for reads from network or serial adapters ... so we have 2002 * partial NAKlimit support for bulk RX. 2003 * 2004 * The upside of disabling it is simpler transfer scheduling. 2005 */ 2006 interval = 0; 2007 } 2008 qh->intv_reg = interval; 2009 2010 /* precompute addressing for external hub/tt ports */ 2011 if (musb->is_multipoint) { 2012 struct usb_device *parent = urb->dev->parent; 2013 2014 if (parent != hcd->self.root_hub) { 2015 qh->h_addr_reg = (u8) parent->devnum; 2016 2017 /* set up tt info if needed */ 2018 if (urb->dev->tt) { 2019 qh->h_port_reg = (u8) urb->dev->ttport; 2020 if (urb->dev->tt->hub) 2021 qh->h_addr_reg = 2022 (u8) urb->dev->tt->hub->devnum; 2023 if (urb->dev->tt->multi) 2024 qh->h_addr_reg |= 0x80; 2025 } 2026 } 2027 } 2028 2029 /* invariant: hep->hcpriv is null OR the qh that's already scheduled. 2030 * until we get real dma queues (with an entry for each urb/buffer), 2031 * we only have work to do in the former case. 2032 */ 2033 spin_lock_irqsave(&musb->lock, flags); 2034 if (hep->hcpriv) { 2035 /* some concurrent activity submitted another urb to hep... 2036 * odd, rare, error prone, but legal. 2037 */ 2038 kfree(qh); 2039 qh = NULL; 2040 ret = 0; 2041 } else 2042 ret = musb_schedule(musb, qh, 2043 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK); 2044 2045 if (ret == 0) { 2046 urb->hcpriv = qh; 2047 } 2048 spin_unlock_irqrestore(&musb->lock, flags); 2049 2050done: 2051 if (ret != 0) { 2052 spin_lock_irqsave(&musb->lock, flags); 2053 usb_hcd_unlink_urb_from_ep(hcd, urb); 2054 spin_unlock_irqrestore(&musb->lock, flags); 2055 kfree(qh); 2056 } 2057 return ret; 2058} 2059 2060 2061/* 2062 * abort a transfer that's at the head of a hardware queue. 2063 * called with controller locked, irqs blocked 2064 * that hardware queue advances to the next transfer, unless prevented 2065 */ 2066static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh) 2067{ 2068 struct musb_hw_ep *ep = qh->hw_ep; 2069 void __iomem *epio = ep->regs; 2070 unsigned hw_end = ep->epnum; 2071 void __iomem *regs = ep->musb->mregs; 2072 int is_in = usb_pipein(urb->pipe); 2073 int status = 0; 2074 u16 csr; 2075 2076 musb_ep_select(regs, hw_end); 2077 2078 if (is_dma_capable()) { 2079 struct dma_channel *dma; 2080 2081 dma = is_in ? ep->rx_channel : ep->tx_channel; 2082 if (dma) { 2083 status = ep->musb->dma_controller->channel_abort(dma); 2084 DBG(status ? 1 : 3, 2085 "abort %cX%d DMA for urb %p --> %d\n", 2086 is_in ? 'R' : 'T', ep->epnum, 2087 urb, status); 2088 urb->actual_length += dma->actual_len; 2089 } 2090 } 2091 2092 /* turn off DMA requests, discard state, stop polling ... */ 2093 if (is_in) { 2094 /* giveback saves bulk toggle */ 2095 csr = musb_h_flush_rxfifo(ep, 0); 2096 2097 /* REVISIT we still get an irq; should likely clear the 2098 * endpoint's irq status here to avoid bogus irqs. 2099 * clearing that status is platform-specific... 2100 */ 2101 } else if (ep->epnum) { 2102 musb_h_tx_flush_fifo(ep); 2103 csr = musb_readw(epio, MUSB_TXCSR); 2104 csr &= ~(MUSB_TXCSR_AUTOSET 2105 | MUSB_TXCSR_DMAENAB 2106 | MUSB_TXCSR_H_RXSTALL 2107 | MUSB_TXCSR_H_NAKTIMEOUT 2108 | MUSB_TXCSR_H_ERROR 2109 | MUSB_TXCSR_TXPKTRDY); 2110 musb_writew(epio, MUSB_TXCSR, csr); 2111 /* REVISIT may need to clear FLUSHFIFO ... */ 2112 musb_writew(epio, MUSB_TXCSR, csr); 2113 /* flush cpu writebuffer */ 2114 csr = musb_readw(epio, MUSB_TXCSR); 2115 } else { 2116 musb_h_ep0_flush_fifo(ep); 2117 } 2118 if (status == 0) 2119 musb_advance_schedule(ep->musb, urb, ep, is_in); 2120 return status; 2121} 2122 2123static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 2124{ 2125 struct musb *musb = hcd_to_musb(hcd); 2126 struct musb_qh *qh; 2127 unsigned long flags; 2128 int is_in = usb_pipein(urb->pipe); 2129 int ret; 2130 2131 DBG(4, "urb=%p, dev%d ep%d%s\n", urb, 2132 usb_pipedevice(urb->pipe), 2133 usb_pipeendpoint(urb->pipe), 2134 is_in ? "in" : "out"); 2135 2136 spin_lock_irqsave(&musb->lock, flags); 2137 ret = usb_hcd_check_unlink_urb(hcd, urb, status); 2138 if (ret) 2139 goto done; 2140 2141 qh = urb->hcpriv; 2142 if (!qh) 2143 goto done; 2144 2145 /* 2146 * Any URB not actively programmed into endpoint hardware can be 2147 * immediately given back; that's any URB not at the head of an 2148 * endpoint queue, unless someday we get real DMA queues. And even 2149 * if it's at the head, it might not be known to the hardware... 2150 * 2151 * Otherwise abort current transfer, pending DMA, etc.; urb->status 2152 * has already been updated. This is a synchronous abort; it'd be 2153 * OK to hold off until after some IRQ, though. 2154 * 2155 * NOTE: qh is invalid unless !list_empty(&hep->urb_list) 2156 */ 2157 if (!qh->is_ready 2158 || urb->urb_list.prev != &qh->hep->urb_list 2159 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) { 2160 int ready = qh->is_ready; 2161 2162 qh->is_ready = 0; 2163 musb_giveback(musb, urb, 0); 2164 qh->is_ready = ready; 2165 2166 /* If nothing else (usually musb_giveback) is using it 2167 * and its URB list has emptied, recycle this qh. 2168 */ 2169 if (ready && list_empty(&qh->hep->urb_list)) { 2170 qh->hep->hcpriv = NULL; 2171 list_del(&qh->ring); 2172 kfree(qh); 2173 } 2174 } else 2175 ret = musb_cleanup_urb(urb, qh); 2176done: 2177 spin_unlock_irqrestore(&musb->lock, flags); 2178 return ret; 2179} 2180 2181/* disable an endpoint */ 2182static void 2183musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) 2184{ 2185 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN; 2186 unsigned long flags; 2187 struct musb *musb = hcd_to_musb(hcd); 2188 struct musb_qh *qh; 2189 struct urb *urb; 2190 2191 spin_lock_irqsave(&musb->lock, flags); 2192 2193 qh = hep->hcpriv; 2194 if (qh == NULL) 2195 goto exit; 2196 2197 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ 2198 2199 /* Kick the first URB off the hardware, if needed */ 2200 qh->is_ready = 0; 2201 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) { 2202 urb = next_urb(qh); 2203 2204 /* make software (then hardware) stop ASAP */ 2205 if (!urb->unlinked) 2206 urb->status = -ESHUTDOWN; 2207 2208 /* cleanup */ 2209 musb_cleanup_urb(urb, qh); 2210 2211 /* Then nuke all the others ... and advance the 2212 * queue on hw_ep (e.g. bulk ring) when we're done. 2213 */ 2214 while (!list_empty(&hep->urb_list)) { 2215 urb = next_urb(qh); 2216 urb->status = -ESHUTDOWN; 2217 musb_advance_schedule(musb, urb, qh->hw_ep, is_in); 2218 } 2219 } else { 2220 /* Just empty the queue; the hardware is busy with 2221 * other transfers, and since !qh->is_ready nothing 2222 * will activate any of these as it advances. 2223 */ 2224 while (!list_empty(&hep->urb_list)) 2225 musb_giveback(musb, next_urb(qh), -ESHUTDOWN); 2226 2227 hep->hcpriv = NULL; 2228 list_del(&qh->ring); 2229 kfree(qh); 2230 } 2231exit: 2232 spin_unlock_irqrestore(&musb->lock, flags); 2233} 2234 2235static int musb_h_get_frame_number(struct usb_hcd *hcd) 2236{ 2237 struct musb *musb = hcd_to_musb(hcd); 2238 2239 return musb_readw(musb->mregs, MUSB_FRAME); 2240} 2241 2242static int musb_h_start(struct usb_hcd *hcd) 2243{ 2244 struct musb *musb = hcd_to_musb(hcd); 2245 2246 /* NOTE: musb_start() is called when the hub driver turns 2247 * on port power, or when (OTG) peripheral starts. 2248 */ 2249 hcd->state = HC_STATE_RUNNING; 2250 musb->port1_status = 0; 2251 return 0; 2252} 2253 2254static void musb_h_stop(struct usb_hcd *hcd) 2255{ 2256 musb_stop(hcd_to_musb(hcd)); 2257 hcd->state = HC_STATE_HALT; 2258} 2259 2260static int musb_bus_suspend(struct usb_hcd *hcd) 2261{ 2262 struct musb *musb = hcd_to_musb(hcd); 2263 u8 devctl; 2264 2265 if (!is_host_active(musb)) 2266 return 0; 2267 2268 switch (musb->xceiv->state) { 2269 case OTG_STATE_A_SUSPEND: 2270 return 0; 2271 case OTG_STATE_A_WAIT_VRISE: 2272 /* ID could be grounded even if there's no device 2273 * on the other end of the cable. NOTE that the 2274 * A_WAIT_VRISE timers are messy with MUSB... 2275 */ 2276 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2277 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 2278 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 2279 break; 2280 default: 2281 break; 2282 } 2283 2284 if (musb->is_active) { 2285 WARNING("trying to suspend as %s while active\n", 2286 otg_state_string(musb)); 2287 return -EBUSY; 2288 } else 2289 return 0; 2290} 2291 2292static int musb_bus_resume(struct usb_hcd *hcd) 2293{ 2294 /* resuming child port does the work */ 2295 return 0; 2296} 2297 2298const struct hc_driver musb_hc_driver = { 2299 .description = "musb-hcd", 2300 .product_desc = "MUSB HDRC host driver", 2301 .hcd_priv_size = sizeof(struct musb), 2302 .flags = HCD_USB2 | HCD_MEMORY, 2303 2304 /* not using irq handler or reset hooks from usbcore, since 2305 * those must be shared with peripheral code for OTG configs 2306 */ 2307 2308 .start = musb_h_start, 2309 .stop = musb_h_stop, 2310 2311 .get_frame_number = musb_h_get_frame_number, 2312 2313 .urb_enqueue = musb_urb_enqueue, 2314 .urb_dequeue = musb_urb_dequeue, 2315 .endpoint_disable = musb_h_disable, 2316 2317 .hub_status_data = musb_hub_status_data, 2318 .hub_control = musb_hub_control, 2319 .bus_suspend = musb_bus_suspend, 2320 .bus_resume = musb_bus_resume, 2321 /* .start_port_reset = NULL, */ 2322 /* .hub_irq_enable = NULL, */ 2323}; 2324