1/* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19#ifndef __LINUX_EHCI_HCD_H 20#define __LINUX_EHCI_HCD_H 21 22/* definitions used for the EHCI driver */ 23 24/* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33typedef __u32 __bitwise __hc32; 34typedef __u16 __bitwise __hc16; 35#else 36#define __hc32 __le32 37#define __hc16 __le16 38#endif 39 40/* statistics can be kept for tuning/monitoring */ 41struct ehci_stats { 42 /* irq usage */ 43 unsigned long normal; 44 unsigned long error; 45 unsigned long reclaim; 46 unsigned long lost_iaa; 47 48 /* termination of urbs from core */ 49 unsigned long complete; 50 unsigned long unlink; 51}; 52 53/* ehci_hcd->lock guards shared data against other CPUs: 54 * ehci_hcd: async, reclaim, periodic (and shadow), ... 55 * usb_host_endpoint: hcpriv 56 * ehci_qh: qh_next, qtd_list 57 * ehci_qtd: qtd_list 58 * 59 * Also, hold this lock when talking to HC registers or 60 * when updating hw_* fields in shared qh/qtd/... structures. 61 */ 62 63#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 64 65struct ehci_hcd { /* one per controller */ 66 /* glue to PCI and HCD framework */ 67 struct ehci_caps __iomem *caps; 68 struct ehci_regs __iomem *regs; 69 struct ehci_dbg_port __iomem *debug; 70 71 __u32 hcs_params; /* cached register copy */ 72 spinlock_t lock; 73 74 /* async schedule support */ 75 struct ehci_qh *async; 76 struct ehci_qh *reclaim; 77 unsigned scanning : 1; 78 79 /* periodic schedule support */ 80#define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 81 unsigned periodic_size; 82 __hc32 *periodic; /* hw periodic table */ 83 dma_addr_t periodic_dma; 84 unsigned i_thresh; /* uframes HC might cache */ 85 86 union ehci_shadow *pshadow; /* mirror hw periodic table */ 87 int next_uframe; /* scan periodic, start here */ 88 unsigned periodic_sched; /* periodic activity count */ 89 90 /* list of itds & sitds completed while clock_frame was still active */ 91 struct list_head cached_itd_list; 92 struct list_head cached_sitd_list; 93 unsigned clock_frame; 94 95 /* per root hub port */ 96 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 97 98 /* bit vectors (one bit per port) */ 99 unsigned long bus_suspended; /* which ports were 100 already suspended at the start of a bus suspend */ 101 unsigned long companion_ports; /* which ports are 102 dedicated to the companion controller */ 103 unsigned long owned_ports; /* which ports are 104 owned by the companion during a bus suspend */ 105 unsigned long port_c_suspend; /* which ports have 106 the change-suspend feature turned on */ 107 unsigned long suspended_ports; /* which ports are 108 suspended */ 109 110 /* per-HC memory pools (could be per-bus, but ...) */ 111 struct dma_pool *qh_pool; /* qh per active urb */ 112 struct dma_pool *qtd_pool; /* one or more per qh */ 113 struct dma_pool *itd_pool; /* itd per iso urb */ 114 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 115 116 struct timer_list iaa_watchdog; 117 struct timer_list watchdog; 118 unsigned long actions; 119 unsigned stamp; 120 unsigned random_frame; 121 unsigned long next_statechange; 122 ktime_t last_periodic_enable; 123 u32 command; 124 125 /* SILICON QUIRKS */ 126 unsigned no_selective_suspend:1; 127 unsigned has_fsl_port_bug:1; /* FreeScale */ 128 unsigned big_endian_mmio:1; 129 unsigned big_endian_desc:1; 130 unsigned has_amcc_usb23:1; 131 unsigned need_io_watchdog:1; 132 unsigned broken_periodic:1; 133 unsigned amd_l1_fix:1; 134 unsigned fs_i_thresh:1; /* Intel iso scheduling */ 135 136 /* required for usb32 quirk */ 137 #define OHCI_CTRL_HCFS (3 << 6) 138 #define OHCI_USB_OPER (2 << 6) 139 #define OHCI_USB_SUSPEND (3 << 6) 140 141 #define OHCI_HCCTRL_OFFSET 0x4 142 #define OHCI_HCCTRL_LEN 0x4 143 __hc32 *ohci_hcctrl_reg; 144 unsigned has_hostpc:1; 145 unsigned has_lpm:1; /* support link power management */ 146 unsigned has_ppcd:1; /* support per-port change bits */ 147 u8 sbrn; /* packed release number */ 148 149 /* irq statistics */ 150#ifdef EHCI_STATS 151 struct ehci_stats stats; 152# define COUNT(x) do { (x)++; } while (0) 153#else 154# define COUNT(x) do {} while (0) 155#endif 156 157 /* debug files */ 158#ifdef DEBUG 159 struct dentry *debug_dir; 160#endif 161}; 162 163/* convert between an HCD pointer and the corresponding EHCI_HCD */ 164static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 165{ 166 return (struct ehci_hcd *) (hcd->hcd_priv); 167} 168static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 169{ 170 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 171} 172 173 174static inline void 175iaa_watchdog_start(struct ehci_hcd *ehci) 176{ 177 WARN_ON(timer_pending(&ehci->iaa_watchdog)); 178 mod_timer(&ehci->iaa_watchdog, 179 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); 180} 181 182static inline void iaa_watchdog_done(struct ehci_hcd *ehci) 183{ 184 del_timer(&ehci->iaa_watchdog); 185} 186 187enum ehci_timer_action { 188 TIMER_IO_WATCHDOG, 189 TIMER_ASYNC_SHRINK, 190 TIMER_ASYNC_OFF, 191}; 192 193static inline void 194timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) 195{ 196 clear_bit (action, &ehci->actions); 197} 198 199static void free_cached_lists(struct ehci_hcd *ehci); 200 201/*-------------------------------------------------------------------------*/ 202 203#include <linux/usb/ehci_def.h> 204 205/*-------------------------------------------------------------------------*/ 206 207#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 208 209/* 210 * EHCI Specification 0.95 Section 3.5 211 * QTD: describe data transfer components (buffer, direction, ...) 212 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 213 * 214 * These are associated only with "QH" (Queue Head) structures, 215 * used with control, bulk, and interrupt transfers. 216 */ 217struct ehci_qtd { 218 /* first part defined by EHCI spec */ 219 __hc32 hw_next; /* see EHCI 3.5.1 */ 220 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 221 __hc32 hw_token; /* see EHCI 3.5.3 */ 222#define QTD_TOGGLE (1 << 31) /* data toggle */ 223#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 224#define QTD_IOC (1 << 15) /* interrupt on complete */ 225#define QTD_CERR(tok) (((tok)>>10) & 0x3) 226#define QTD_PID(tok) (((tok)>>8) & 0x3) 227#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 228#define QTD_STS_HALT (1 << 6) /* halted on error */ 229#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 230#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 231#define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 232#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 233#define QTD_STS_STS (1 << 1) /* split transaction state */ 234#define QTD_STS_PING (1 << 0) /* issue PING? */ 235 236#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 237#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 238#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 239 240 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 241 __hc32 hw_buf_hi [5]; /* Appendix B */ 242 243 /* the rest is HCD-private */ 244 dma_addr_t qtd_dma; /* qtd address */ 245 struct list_head qtd_list; /* sw qtd list */ 246 struct urb *urb; /* qtd's urb */ 247 size_t length; /* length of buffer */ 248} __attribute__ ((aligned (32))); 249 250/* mask NakCnt+T in qh->hw_alt_next */ 251#define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 252 253#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 254 255/*-------------------------------------------------------------------------*/ 256 257/* type tag from {qh,itd,sitd,fstn}->hw_next */ 258#define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 259 260/* 261 * Now the following defines are not converted using the 262 * cpu_to_le32() macro anymore, since we have to support 263 * "dynamic" switching between be and le support, so that the driver 264 * can be used on one system with SoC EHCI controller using big-endian 265 * descriptors as well as a normal little-endian PCI EHCI controller. 266 */ 267/* values for that type tag */ 268#define Q_TYPE_ITD (0 << 1) 269#define Q_TYPE_QH (1 << 1) 270#define Q_TYPE_SITD (2 << 1) 271#define Q_TYPE_FSTN (3 << 1) 272 273/* next async queue entry, or pointer to interrupt/periodic QH */ 274#define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 275 276/* for periodic/async schedules and qtd lists, mark end of list */ 277#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 278 279/* 280 * Entries in periodic shadow table are pointers to one of four kinds 281 * of data structure. That's dictated by the hardware; a type tag is 282 * encoded in the low bits of the hardware's periodic schedule. Use 283 * Q_NEXT_TYPE to get the tag. 284 * 285 * For entries in the async schedule, the type tag always says "qh". 286 */ 287union ehci_shadow { 288 struct ehci_qh *qh; /* Q_TYPE_QH */ 289 struct ehci_itd *itd; /* Q_TYPE_ITD */ 290 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 291 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 292 __hc32 *hw_next; /* (all types) */ 293 void *ptr; 294}; 295 296/*-------------------------------------------------------------------------*/ 297 298/* 299 * EHCI Specification 0.95 Section 3.6 300 * QH: describes control/bulk/interrupt endpoints 301 * See Fig 3-7 "Queue Head Structure Layout". 302 * 303 * These appear in both the async and (for interrupt) periodic schedules. 304 */ 305 306/* first part defined by EHCI spec */ 307struct ehci_qh_hw { 308 __hc32 hw_next; /* see EHCI 3.6.1 */ 309 __hc32 hw_info1; /* see EHCI 3.6.2 */ 310#define QH_HEAD 0x00008000 311 __hc32 hw_info2; /* see EHCI 3.6.2 */ 312#define QH_SMASK 0x000000ff 313#define QH_CMASK 0x0000ff00 314#define QH_HUBADDR 0x007f0000 315#define QH_HUBPORT 0x3f800000 316#define QH_MULT 0xc0000000 317 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 318 319 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 320 __hc32 hw_qtd_next; 321 __hc32 hw_alt_next; 322 __hc32 hw_token; 323 __hc32 hw_buf [5]; 324 __hc32 hw_buf_hi [5]; 325} __attribute__ ((aligned(32))); 326 327struct ehci_qh { 328 struct ehci_qh_hw *hw; 329 /* the rest is HCD-private */ 330 dma_addr_t qh_dma; /* address of qh */ 331 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 332 struct list_head qtd_list; /* sw qtd list */ 333 struct ehci_qtd *dummy; 334 struct ehci_qh *reclaim; /* next to reclaim */ 335 336 struct ehci_hcd *ehci; 337 338 /* 339 * Do NOT use atomic operations for QH refcounting. On some CPUs 340 * (PPC7448 for example), atomic operations cannot be performed on 341 * memory that is cache-inhibited (i.e. being used for DMA). 342 * Spinlocks are used to protect all QH fields. 343 */ 344 u32 refcount; 345 unsigned stamp; 346 347 u8 needs_rescan; /* Dequeue during giveback */ 348 u8 qh_state; 349#define QH_STATE_LINKED 1 /* HC sees this */ 350#define QH_STATE_UNLINK 2 /* HC may still see this */ 351#define QH_STATE_IDLE 3 /* HC doesn't see this */ 352#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ 353#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 354 355 u8 xacterrs; /* XactErr retry counter */ 356#define QH_XACTERR_MAX 32 /* XactErr retry limit */ 357 358 /* periodic schedule info */ 359 u8 usecs; /* intr bandwidth */ 360 u8 gap_uf; /* uframes split/csplit gap */ 361 u8 c_usecs; /* ... split completion bw */ 362 u16 tt_usecs; /* tt downstream bandwidth */ 363 unsigned short period; /* polling interval */ 364 unsigned short start; /* where polling starts */ 365#define NO_FRAME ((unsigned short)~0) /* pick new start */ 366 367 struct usb_device *dev; /* access to TT */ 368 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ 369}; 370 371/*-------------------------------------------------------------------------*/ 372 373/* description of one iso transaction (up to 3 KB data if highspeed) */ 374struct ehci_iso_packet { 375 /* These will be copied to iTD when scheduling */ 376 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 377 __hc32 transaction; /* itd->hw_transaction[i] |= */ 378 u8 cross; /* buf crosses pages */ 379 /* for full speed OUT splits */ 380 u32 buf1; 381}; 382 383/* temporary schedule data for packets from iso urbs (both speeds) 384 * each packet is one logical usb transaction to the device (not TT), 385 * beginning at stream->next_uframe 386 */ 387struct ehci_iso_sched { 388 struct list_head td_list; 389 unsigned span; 390 struct ehci_iso_packet packet [0]; 391}; 392 393/* 394 * ehci_iso_stream - groups all (s)itds for this endpoint. 395 * acts like a qh would, if EHCI had them for ISO. 396 */ 397struct ehci_iso_stream { 398 /* first field matches ehci_hq, but is NULL */ 399 struct ehci_qh_hw *hw; 400 401 u32 refcount; 402 u8 bEndpointAddress; 403 u8 highspeed; 404 struct list_head td_list; /* queued itds/sitds */ 405 struct list_head free_list; /* list of unused itds/sitds */ 406 struct usb_device *udev; 407 struct usb_host_endpoint *ep; 408 409 /* output of (re)scheduling */ 410 int next_uframe; 411 __hc32 splits; 412 413 /* the rest is derived from the endpoint descriptor, 414 * trusting urb->interval == f(epdesc->bInterval) and 415 * including the extra info for hw_bufp[0..2] 416 */ 417 u8 usecs, c_usecs; 418 u16 interval; 419 u16 tt_usecs; 420 u16 maxp; 421 u16 raw_mask; 422 unsigned bandwidth; 423 424 /* This is used to initialize iTD's hw_bufp fields */ 425 __hc32 buf0; 426 __hc32 buf1; 427 __hc32 buf2; 428 429 /* this is used to initialize sITD's tt info */ 430 __hc32 address; 431}; 432 433/*-------------------------------------------------------------------------*/ 434 435/* 436 * EHCI Specification 0.95 Section 3.3 437 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 438 * 439 * Schedule records for high speed iso xfers 440 */ 441struct ehci_itd { 442 /* first part defined by EHCI spec */ 443 __hc32 hw_next; /* see EHCI 3.3.1 */ 444 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 445#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 446#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 447#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 448#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 449#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 450#define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 451 452#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 453 454 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 455 __hc32 hw_bufp_hi [7]; /* Appendix B */ 456 457 /* the rest is HCD-private */ 458 dma_addr_t itd_dma; /* for this itd */ 459 union ehci_shadow itd_next; /* ptr to periodic q entry */ 460 461 struct urb *urb; 462 struct ehci_iso_stream *stream; /* endpoint's queue */ 463 struct list_head itd_list; /* list of stream's itds */ 464 465 /* any/all hw_transactions here may be used by that urb */ 466 unsigned frame; /* where scheduled */ 467 unsigned pg; 468 unsigned index[8]; /* in urb->iso_frame_desc */ 469} __attribute__ ((aligned (32))); 470 471/*-------------------------------------------------------------------------*/ 472 473/* 474 * EHCI Specification 0.95 Section 3.4 475 * siTD, aka split-transaction isochronous Transfer Descriptor 476 * ... describe full speed iso xfers through TT in hubs 477 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 478 */ 479struct ehci_sitd { 480 /* first part defined by EHCI spec */ 481 __hc32 hw_next; 482/* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 483 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 484 __hc32 hw_uframe; /* EHCI table 3-10 */ 485 __hc32 hw_results; /* EHCI table 3-11 */ 486#define SITD_IOC (1 << 31) /* interrupt on completion */ 487#define SITD_PAGE (1 << 30) /* buffer 0/1 */ 488#define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 489#define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 490#define SITD_STS_ERR (1 << 6) /* error from TT */ 491#define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 492#define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 493#define SITD_STS_XACT (1 << 3) /* illegal IN response */ 494#define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 495#define SITD_STS_STS (1 << 1) /* split transaction state */ 496 497#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 498 499 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 500 __hc32 hw_backpointer; /* EHCI table 3-13 */ 501 __hc32 hw_buf_hi [2]; /* Appendix B */ 502 503 /* the rest is HCD-private */ 504 dma_addr_t sitd_dma; 505 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 506 507 struct urb *urb; 508 struct ehci_iso_stream *stream; /* endpoint's queue */ 509 struct list_head sitd_list; /* list of stream's sitds */ 510 unsigned frame; 511 unsigned index; 512} __attribute__ ((aligned (32))); 513 514/*-------------------------------------------------------------------------*/ 515 516/* 517 * EHCI Specification 0.96 Section 3.7 518 * Periodic Frame Span Traversal Node (FSTN) 519 * 520 * Manages split interrupt transactions (using TT) that span frame boundaries 521 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 522 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 523 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 524 */ 525struct ehci_fstn { 526 __hc32 hw_next; /* any periodic q entry */ 527 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 528 529 /* the rest is HCD-private */ 530 dma_addr_t fstn_dma; 531 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 532} __attribute__ ((aligned (32))); 533 534/*-------------------------------------------------------------------------*/ 535 536/* Prepare the PORTSC wakeup flags during controller suspend/resume */ 537 538#define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ 539 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup); 540 541#define ehci_prepare_ports_for_controller_resume(ehci) \ 542 ehci_adjust_port_wakeup_flags(ehci, false, false); 543 544/*-------------------------------------------------------------------------*/ 545 546#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 547 548/* 549 * Some EHCI controllers have a Transaction Translator built into the 550 * root hub. This is a non-standard feature. Each controller will need 551 * to add code to the following inline functions, and call them as 552 * needed (mostly in root hub code). 553 */ 554 555#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 556 557/* Returns the speed of a device attached to a port on the root hub. */ 558static inline unsigned int 559ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 560{ 561 if (ehci_is_TDI(ehci)) { 562 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { 563 case 0: 564 return 0; 565 case 1: 566 return USB_PORT_STAT_LOW_SPEED; 567 case 2: 568 default: 569 return USB_PORT_STAT_HIGH_SPEED; 570 } 571 } 572 return USB_PORT_STAT_HIGH_SPEED; 573} 574 575#else 576 577#define ehci_is_TDI(e) (0) 578 579#define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED 580#endif 581 582/*-------------------------------------------------------------------------*/ 583 584#ifdef CONFIG_PPC_83xx 585/* Some Freescale processors have an erratum in which the TT 586 * port number in the queue head was 0..N-1 instead of 1..N. 587 */ 588#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 589#else 590#define ehci_has_fsl_portno_bug(e) (0) 591#endif 592 593/* 594 * While most USB host controllers implement their registers in 595 * little-endian format, a minority (celleb companion chip) implement 596 * them in big endian format. 597 * 598 * This attempts to support either format at compile time without a 599 * runtime penalty, or both formats with the additional overhead 600 * of checking a flag bit. 601 */ 602 603#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 604#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 605#else 606#define ehci_big_endian_mmio(e) 0 607#endif 608 609/* 610 * Big-endian read/write functions are arch-specific. 611 * Other arches can be added if/when they're needed. 612 */ 613#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 614#define readl_be(addr) __raw_readl((__force unsigned *)addr) 615#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 616#endif 617 618static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 619 __u32 __iomem * regs) 620{ 621#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 622 return ehci_big_endian_mmio(ehci) ? 623 readl_be(regs) : 624 readl(regs); 625#else 626 return readl(regs); 627#endif 628} 629 630static inline void ehci_writel(const struct ehci_hcd *ehci, 631 const unsigned int val, __u32 __iomem *regs) 632{ 633#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 634 ehci_big_endian_mmio(ehci) ? 635 writel_be(val, regs) : 636 writel(val, regs); 637#else 638 writel(val, regs); 639#endif 640} 641 642/* 643 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 644 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 645 * Other common bits are dependant on has_amcc_usb23 quirk flag. 646 */ 647#ifdef CONFIG_44x 648static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 649{ 650 u32 hc_control; 651 652 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 653 if (operational) 654 hc_control |= OHCI_USB_OPER; 655 else 656 hc_control |= OHCI_USB_SUSPEND; 657 658 writel_be(hc_control, ehci->ohci_hcctrl_reg); 659 (void) readl_be(ehci->ohci_hcctrl_reg); 660} 661#else 662static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 663{ } 664#endif 665 666/*-------------------------------------------------------------------------*/ 667 668/* 669 * The AMCC 440EPx not only implements its EHCI registers in big-endian 670 * format, but also its DMA data structures (descriptors). 671 * 672 * EHCI controllers accessed through PCI work normally (little-endian 673 * everywhere), so we won't bother supporting a BE-only mode for now. 674 */ 675#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 676#define ehci_big_endian_desc(e) ((e)->big_endian_desc) 677 678/* cpu to ehci */ 679static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 680{ 681 return ehci_big_endian_desc(ehci) 682 ? (__force __hc32)cpu_to_be32(x) 683 : (__force __hc32)cpu_to_le32(x); 684} 685 686/* ehci to cpu */ 687static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 688{ 689 return ehci_big_endian_desc(ehci) 690 ? be32_to_cpu((__force __be32)x) 691 : le32_to_cpu((__force __le32)x); 692} 693 694static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 695{ 696 return ehci_big_endian_desc(ehci) 697 ? be32_to_cpup((__force __be32 *)x) 698 : le32_to_cpup((__force __le32 *)x); 699} 700 701#else 702 703/* cpu to ehci */ 704static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 705{ 706 return cpu_to_le32(x); 707} 708 709/* ehci to cpu */ 710static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 711{ 712 return le32_to_cpu(x); 713} 714 715static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 716{ 717 return le32_to_cpup(x); 718} 719 720#endif 721 722/*-------------------------------------------------------------------------*/ 723 724#ifndef DEBUG 725#define STUB_DEBUG_FILES 726#endif /* DEBUG */ 727 728/*-------------------------------------------------------------------------*/ 729 730#endif /* __LINUX_EHCI_HCD_H */ 731