1/* 2 * ehci-omap.c - driver for USBHOST on OMAP 34xx processor 3 * 4 * Bus Glue for OMAP34xx USBHOST 3 port EHCI controller 5 * Tested on OMAP3430 ES2.0 SDP 6 * 7 * Copyright (C) 2007-2008 Texas Instruments, Inc. 8 * Author: Vikram Pandita <vikram.pandita@ti.com> 9 * 10 * Copyright (C) 2009 Nokia Corporation 11 * Contact: Felipe Balbi <felipe.balbi@nokia.com> 12 * 13 * Based on "ehci-fsl.c" and "ehci-au1xxx.c" ehci glue layers 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28 * 29 * TODO (last updated Feb 12, 2010): 30 * - add kernel-doc 31 * - enable AUTOIDLE 32 * - add suspend/resume 33 * - move workarounds to board-files 34 */ 35 36#include <linux/platform_device.h> 37#include <linux/clk.h> 38#include <linux/gpio.h> 39#include <linux/regulator/consumer.h> 40#include <linux/slab.h> 41#include <linux/usb/ulpi.h> 42#include <plat/usb.h> 43 44/* 45 * OMAP USBHOST Register addresses: VIRTUAL ADDRESSES 46 * Use ehci_omap_readl()/ehci_omap_writel() functions 47 */ 48 49/* TLL Register Set */ 50#define OMAP_USBTLL_REVISION (0x00) 51#define OMAP_USBTLL_SYSCONFIG (0x10) 52#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) 53#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) 54#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) 55#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) 56#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0) 57 58#define OMAP_USBTLL_SYSSTATUS (0x14) 59#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0) 60 61#define OMAP_USBTLL_IRQSTATUS (0x18) 62#define OMAP_USBTLL_IRQENABLE (0x1C) 63 64#define OMAP_TLL_SHARED_CONF (0x30) 65#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6) 66#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5) 67#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2) 68#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1) 69#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0) 70 71#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num) 72#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) 73#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10) 74#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9) 75#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8) 76#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0) 77 78#define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num) 79#define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num) 80#define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num) 81#define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num) 82#define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num) 83#define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num) 84#define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num) 85#define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num) 86#define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num) 87 88#define OMAP_TLL_CHANNEL_COUNT 3 89#define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 1) 90#define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 2) 91#define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 4) 92 93/* UHH Register Set */ 94#define OMAP_UHH_REVISION (0x00) 95#define OMAP_UHH_SYSCONFIG (0x10) 96#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) 97#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) 98#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) 99#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) 100#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) 101#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0) 102 103#define OMAP_UHH_SYSSTATUS (0x14) 104#define OMAP_UHH_HOSTCONFIG (0x40) 105#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0) 106#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0) 107#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11) 108#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12) 109#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) 110#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) 111#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) 112#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5) 113#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8) 114#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9) 115#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10) 116 117#define OMAP_UHH_DEBUG_CSR (0x44) 118 119/* EHCI Register Set */ 120#define EHCI_INSNREG04 (0xA0) 121#define EHCI_INSNREG04_DISABLE_UNSUSPEND (1 << 5) 122#define EHCI_INSNREG05_ULPI (0xA4) 123#define EHCI_INSNREG05_ULPI_CONTROL_SHIFT 31 124#define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT 24 125#define EHCI_INSNREG05_ULPI_OPSEL_SHIFT 22 126#define EHCI_INSNREG05_ULPI_REGADD_SHIFT 16 127#define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT 8 128#define EHCI_INSNREG05_ULPI_WRDATA_SHIFT 0 129 130/*-------------------------------------------------------------------------*/ 131 132static inline void ehci_omap_writel(void __iomem *base, u32 reg, u32 val) 133{ 134 __raw_writel(val, base + reg); 135} 136 137static inline u32 ehci_omap_readl(void __iomem *base, u32 reg) 138{ 139 return __raw_readl(base + reg); 140} 141 142static inline void ehci_omap_writeb(void __iomem *base, u8 reg, u8 val) 143{ 144 __raw_writeb(val, base + reg); 145} 146 147static inline u8 ehci_omap_readb(void __iomem *base, u8 reg) 148{ 149 return __raw_readb(base + reg); 150} 151 152/*-------------------------------------------------------------------------*/ 153 154struct ehci_hcd_omap { 155 struct ehci_hcd *ehci; 156 struct device *dev; 157 158 struct clk *usbhost_ick; 159 struct clk *usbhost2_120m_fck; 160 struct clk *usbhost1_48m_fck; 161 struct clk *usbtll_fck; 162 struct clk *usbtll_ick; 163 164 165 /* gpio for resetting phy */ 166 int reset_gpio_port[OMAP3_HS_USB_PORTS]; 167 168 int phy_reset; 169 170 /* desired phy_mode: TLL, PHY */ 171 enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS]; 172 173 void __iomem *uhh_base; 174 void __iomem *tll_base; 175 void __iomem *ehci_base; 176 177 /* Regulators for USB PHYs. 178 * Each PHY can have a separate regulator. 179 */ 180 struct regulator *regulator[OMAP3_HS_USB_PORTS]; 181}; 182 183/*-------------------------------------------------------------------------*/ 184 185static void omap_usb_utmi_init(struct ehci_hcd_omap *omap, u8 tll_channel_mask) 186{ 187 unsigned reg; 188 int i; 189 190 /* Program the 3 TLL channels upfront */ 191 for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) { 192 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i)); 193 194 /* Disable AutoIdle, BitStuffing and use SDR Mode */ 195 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE 196 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF 197 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE); 198 ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg); 199 } 200 201 /* Program Common TLL register */ 202 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF); 203 reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON 204 | OMAP_TLL_SHARED_CONF_USB_DIVRATION 205 | OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN); 206 reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN; 207 208 ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg); 209 210 /* Enable channels now */ 211 for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) { 212 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i)); 213 214 /* Enable only the reg that is needed */ 215 if (!(tll_channel_mask & 1<<i)) 216 continue; 217 218 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN; 219 ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg); 220 221 ehci_omap_writeb(omap->tll_base, 222 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe); 223 dev_dbg(omap->dev, "ULPI_SCRATCH_REG[ch=%d]= 0x%02x\n", 224 i+1, ehci_omap_readb(omap->tll_base, 225 OMAP_TLL_ULPI_SCRATCH_REGISTER(i))); 226 } 227} 228 229/*-------------------------------------------------------------------------*/ 230 231static void omap_ehci_soft_phy_reset(struct ehci_hcd_omap *omap, u8 port) 232{ 233 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 234 unsigned reg = 0; 235 236 reg = ULPI_FUNC_CTRL_RESET 237 /* FUNCTION_CTRL_SET register */ 238 | (ULPI_SET(ULPI_FUNC_CTRL) << EHCI_INSNREG05_ULPI_REGADD_SHIFT) 239 /* Write */ 240 | (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) 241 /* PORTn */ 242 | ((port + 1) << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) 243 /* start ULPI access*/ 244 | (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT); 245 246 ehci_omap_writel(omap->ehci_base, EHCI_INSNREG05_ULPI, reg); 247 248 /* Wait for ULPI access completion */ 249 while ((ehci_omap_readl(omap->ehci_base, EHCI_INSNREG05_ULPI) 250 & (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT))) { 251 cpu_relax(); 252 253 if (time_after(jiffies, timeout)) { 254 dev_dbg(omap->dev, "phy reset operation timed out\n"); 255 break; 256 } 257 } 258} 259 260/* omap_start_ehc 261 * - Start the TI USBHOST controller 262 */ 263static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) 264{ 265 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 266 u8 tll_ch_mask = 0; 267 unsigned reg = 0; 268 int ret = 0; 269 270 dev_dbg(omap->dev, "starting TI EHCI USB Controller\n"); 271 272 /* Enable Clocks for USBHOST */ 273 omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick"); 274 if (IS_ERR(omap->usbhost_ick)) { 275 ret = PTR_ERR(omap->usbhost_ick); 276 goto err_host_ick; 277 } 278 clk_enable(omap->usbhost_ick); 279 280 omap->usbhost2_120m_fck = clk_get(omap->dev, "usbhost_120m_fck"); 281 if (IS_ERR(omap->usbhost2_120m_fck)) { 282 ret = PTR_ERR(omap->usbhost2_120m_fck); 283 goto err_host_120m_fck; 284 } 285 clk_enable(omap->usbhost2_120m_fck); 286 287 omap->usbhost1_48m_fck = clk_get(omap->dev, "usbhost_48m_fck"); 288 if (IS_ERR(omap->usbhost1_48m_fck)) { 289 ret = PTR_ERR(omap->usbhost1_48m_fck); 290 goto err_host_48m_fck; 291 } 292 clk_enable(omap->usbhost1_48m_fck); 293 294 if (omap->phy_reset) { 295 /* Refer: ISSUE1 */ 296 if (gpio_is_valid(omap->reset_gpio_port[0])) { 297 gpio_request(omap->reset_gpio_port[0], 298 "USB1 PHY reset"); 299 gpio_direction_output(omap->reset_gpio_port[0], 0); 300 } 301 302 if (gpio_is_valid(omap->reset_gpio_port[1])) { 303 gpio_request(omap->reset_gpio_port[1], 304 "USB2 PHY reset"); 305 gpio_direction_output(omap->reset_gpio_port[1], 0); 306 } 307 308 /* Hold the PHY in RESET for enough time till DIR is high */ 309 udelay(10); 310 } 311 312 /* Configure TLL for 60Mhz clk for ULPI */ 313 omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck"); 314 if (IS_ERR(omap->usbtll_fck)) { 315 ret = PTR_ERR(omap->usbtll_fck); 316 goto err_tll_fck; 317 } 318 clk_enable(omap->usbtll_fck); 319 320 omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick"); 321 if (IS_ERR(omap->usbtll_ick)) { 322 ret = PTR_ERR(omap->usbtll_ick); 323 goto err_tll_ick; 324 } 325 clk_enable(omap->usbtll_ick); 326 327 /* perform TLL soft reset, and wait until reset is complete */ 328 ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, 329 OMAP_USBTLL_SYSCONFIG_SOFTRESET); 330 331 /* Wait for TLL reset to complete */ 332 while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS) 333 & OMAP_USBTLL_SYSSTATUS_RESETDONE)) { 334 cpu_relax(); 335 336 if (time_after(jiffies, timeout)) { 337 dev_dbg(omap->dev, "operation timed out\n"); 338 ret = -EINVAL; 339 goto err_sys_status; 340 } 341 } 342 343 dev_dbg(omap->dev, "TLL RESET DONE\n"); 344 345 /* (1<<3) = no idle mode only for initial debugging */ 346 ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, 347 OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | 348 OMAP_USBTLL_SYSCONFIG_SIDLEMODE | 349 OMAP_USBTLL_SYSCONFIG_CACTIVITY); 350 351 352 /* Put UHH in NoIdle/NoStandby mode */ 353 reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG); 354 reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP 355 | OMAP_UHH_SYSCONFIG_SIDLEMODE 356 | OMAP_UHH_SYSCONFIG_CACTIVITY 357 | OMAP_UHH_SYSCONFIG_MIDLEMODE); 358 reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE; 359 360 ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg); 361 362 reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG); 363 364 /* setup ULPI bypass and burst configurations */ 365 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN 366 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN 367 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); 368 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; 369 370 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN) 371 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; 372 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN) 373 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; 374 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN) 375 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; 376 377 /* Bypass the TLL module for PHY mode operation */ 378 if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) { 379 dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1\n"); 380 if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) || 381 (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) || 382 (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY)) 383 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; 384 else 385 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; 386 } else { 387 dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n"); 388 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) 389 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; 390 else if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) 391 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; 392 393 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) 394 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; 395 else if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) 396 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; 397 398 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY) 399 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; 400 else if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL) 401 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; 402 403 } 404 ehci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); 405 dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg); 406 407 408 /* 409 * An undocumented "feature" in the OMAP3 EHCI controller, 410 * causes suspended ports to be taken out of suspend when 411 * the USBCMD.Run/Stop bit is cleared (for example when 412 * we do ehci_bus_suspend). 413 * This breaks suspend-resume if the root-hub is allowed 414 * to suspend. Writing 1 to this undocumented register bit 415 * disables this feature and restores normal behavior. 416 */ 417 ehci_omap_writel(omap->ehci_base, EHCI_INSNREG04, 418 EHCI_INSNREG04_DISABLE_UNSUSPEND); 419 420 if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) || 421 (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) || 422 (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) { 423 424 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) 425 tll_ch_mask |= OMAP_TLL_CHANNEL_1_EN_MASK; 426 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) 427 tll_ch_mask |= OMAP_TLL_CHANNEL_2_EN_MASK; 428 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL) 429 tll_ch_mask |= OMAP_TLL_CHANNEL_3_EN_MASK; 430 431 /* Enable UTMI mode for required TLL channels */ 432 omap_usb_utmi_init(omap, tll_ch_mask); 433 } 434 435 if (omap->phy_reset) { 436 /* Refer ISSUE1: 437 * Hold the PHY in RESET for enough time till 438 * PHY is settled and ready 439 */ 440 udelay(10); 441 442 if (gpio_is_valid(omap->reset_gpio_port[0])) 443 gpio_set_value(omap->reset_gpio_port[0], 1); 444 445 if (gpio_is_valid(omap->reset_gpio_port[1])) 446 gpio_set_value(omap->reset_gpio_port[1], 1); 447 } 448 449 /* Soft reset the PHY using PHY reset command over ULPI */ 450 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) 451 omap_ehci_soft_phy_reset(omap, 0); 452 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) 453 omap_ehci_soft_phy_reset(omap, 1); 454 455 return 0; 456 457err_sys_status: 458 clk_disable(omap->usbtll_ick); 459 clk_put(omap->usbtll_ick); 460 461err_tll_ick: 462 clk_disable(omap->usbtll_fck); 463 clk_put(omap->usbtll_fck); 464 465err_tll_fck: 466 clk_disable(omap->usbhost1_48m_fck); 467 clk_put(omap->usbhost1_48m_fck); 468 469 if (omap->phy_reset) { 470 if (gpio_is_valid(omap->reset_gpio_port[0])) 471 gpio_free(omap->reset_gpio_port[0]); 472 473 if (gpio_is_valid(omap->reset_gpio_port[1])) 474 gpio_free(omap->reset_gpio_port[1]); 475 } 476 477err_host_48m_fck: 478 clk_disable(omap->usbhost2_120m_fck); 479 clk_put(omap->usbhost2_120m_fck); 480 481err_host_120m_fck: 482 clk_disable(omap->usbhost_ick); 483 clk_put(omap->usbhost_ick); 484 485err_host_ick: 486 return ret; 487} 488 489static void omap_stop_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) 490{ 491 unsigned long timeout = jiffies + msecs_to_jiffies(100); 492 493 dev_dbg(omap->dev, "stopping TI EHCI USB Controller\n"); 494 495 /* Reset OMAP modules for insmod/rmmod to work */ 496 ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, 497 OMAP_UHH_SYSCONFIG_SOFTRESET); 498 while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) 499 & (1 << 0))) { 500 cpu_relax(); 501 502 if (time_after(jiffies, timeout)) 503 dev_dbg(omap->dev, "operation timed out\n"); 504 } 505 506 while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) 507 & (1 << 1))) { 508 cpu_relax(); 509 510 if (time_after(jiffies, timeout)) 511 dev_dbg(omap->dev, "operation timed out\n"); 512 } 513 514 while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) 515 & (1 << 2))) { 516 cpu_relax(); 517 518 if (time_after(jiffies, timeout)) 519 dev_dbg(omap->dev, "operation timed out\n"); 520 } 521 522 ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1)); 523 524 while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS) 525 & (1 << 0))) { 526 cpu_relax(); 527 528 if (time_after(jiffies, timeout)) 529 dev_dbg(omap->dev, "operation timed out\n"); 530 } 531 532 if (omap->usbtll_fck != NULL) { 533 clk_disable(omap->usbtll_fck); 534 clk_put(omap->usbtll_fck); 535 omap->usbtll_fck = NULL; 536 } 537 538 if (omap->usbhost_ick != NULL) { 539 clk_disable(omap->usbhost_ick); 540 clk_put(omap->usbhost_ick); 541 omap->usbhost_ick = NULL; 542 } 543 544 if (omap->usbhost1_48m_fck != NULL) { 545 clk_disable(omap->usbhost1_48m_fck); 546 clk_put(omap->usbhost1_48m_fck); 547 omap->usbhost1_48m_fck = NULL; 548 } 549 550 if (omap->usbhost2_120m_fck != NULL) { 551 clk_disable(omap->usbhost2_120m_fck); 552 clk_put(omap->usbhost2_120m_fck); 553 omap->usbhost2_120m_fck = NULL; 554 } 555 556 if (omap->usbtll_ick != NULL) { 557 clk_disable(omap->usbtll_ick); 558 clk_put(omap->usbtll_ick); 559 omap->usbtll_ick = NULL; 560 } 561 562 if (omap->phy_reset) { 563 if (gpio_is_valid(omap->reset_gpio_port[0])) 564 gpio_free(omap->reset_gpio_port[0]); 565 566 if (gpio_is_valid(omap->reset_gpio_port[1])) 567 gpio_free(omap->reset_gpio_port[1]); 568 } 569 570 dev_dbg(omap->dev, "Clock to USB host has been disabled\n"); 571} 572 573/*-------------------------------------------------------------------------*/ 574 575static const struct hc_driver ehci_omap_hc_driver; 576 577/* configure so an HC device and id are always provided */ 578/* always called with process context; sleeping is OK */ 579 580/** 581 * ehci_hcd_omap_probe - initialize TI-based HCDs 582 * 583 * Allocates basic resources for this USB host controller, and 584 * then invokes the start() method for the HCD associated with it 585 * through the hotplug entry's driver_data. 586 */ 587static int ehci_hcd_omap_probe(struct platform_device *pdev) 588{ 589 struct ehci_hcd_omap_platform_data *pdata = pdev->dev.platform_data; 590 struct ehci_hcd_omap *omap; 591 struct resource *res; 592 struct usb_hcd *hcd; 593 594 int irq = platform_get_irq(pdev, 0); 595 int ret = -ENODEV; 596 int i; 597 char supply[7]; 598 599 if (!pdata) { 600 dev_dbg(&pdev->dev, "missing platform_data\n"); 601 goto err_pdata; 602 } 603 604 if (usb_disabled()) 605 goto err_disabled; 606 607 omap = kzalloc(sizeof(*omap), GFP_KERNEL); 608 if (!omap) { 609 ret = -ENOMEM; 610 goto err_disabled; 611 } 612 613 hcd = usb_create_hcd(&ehci_omap_hc_driver, &pdev->dev, 614 dev_name(&pdev->dev)); 615 if (!hcd) { 616 dev_dbg(&pdev->dev, "failed to create hcd with err %d\n", ret); 617 ret = -ENOMEM; 618 goto err_create_hcd; 619 } 620 621 platform_set_drvdata(pdev, omap); 622 omap->dev = &pdev->dev; 623 omap->phy_reset = pdata->phy_reset; 624 omap->reset_gpio_port[0] = pdata->reset_gpio_port[0]; 625 omap->reset_gpio_port[1] = pdata->reset_gpio_port[1]; 626 omap->reset_gpio_port[2] = pdata->reset_gpio_port[2]; 627 omap->port_mode[0] = pdata->port_mode[0]; 628 omap->port_mode[1] = pdata->port_mode[1]; 629 omap->port_mode[2] = pdata->port_mode[2]; 630 omap->ehci = hcd_to_ehci(hcd); 631 omap->ehci->sbrn = 0x20; 632 633 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 634 635 hcd->rsrc_start = res->start; 636 hcd->rsrc_len = resource_size(res); 637 638 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); 639 if (!hcd->regs) { 640 dev_err(&pdev->dev, "EHCI ioremap failed\n"); 641 ret = -ENOMEM; 642 goto err_ioremap; 643 } 644 645 /* we know this is the memory we want, no need to ioremap again */ 646 omap->ehci->caps = hcd->regs; 647 omap->ehci_base = hcd->regs; 648 649 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 650 omap->uhh_base = ioremap(res->start, resource_size(res)); 651 if (!omap->uhh_base) { 652 dev_err(&pdev->dev, "UHH ioremap failed\n"); 653 ret = -ENOMEM; 654 goto err_uhh_ioremap; 655 } 656 657 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 658 omap->tll_base = ioremap(res->start, resource_size(res)); 659 if (!omap->tll_base) { 660 dev_err(&pdev->dev, "TLL ioremap failed\n"); 661 ret = -ENOMEM; 662 goto err_tll_ioremap; 663 } 664 665 /* get ehci regulator and enable */ 666 for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) { 667 if (omap->port_mode[i] != EHCI_HCD_OMAP_MODE_PHY) { 668 omap->regulator[i] = NULL; 669 continue; 670 } 671 snprintf(supply, sizeof(supply), "hsusb%d", i); 672 omap->regulator[i] = regulator_get(omap->dev, supply); 673 if (IS_ERR(omap->regulator[i])) { 674 omap->regulator[i] = NULL; 675 dev_dbg(&pdev->dev, 676 "failed to get ehci port%d regulator\n", i); 677 } else { 678 regulator_enable(omap->regulator[i]); 679 } 680 } 681 682 ret = omap_start_ehc(omap, hcd); 683 if (ret) { 684 dev_dbg(&pdev->dev, "failed to start ehci\n"); 685 goto err_start; 686 } 687 688 omap->ehci->regs = hcd->regs 689 + HC_LENGTH(readl(&omap->ehci->caps->hc_capbase)); 690 691 dbg_hcs_params(omap->ehci, "reset"); 692 dbg_hcc_params(omap->ehci, "reset"); 693 694 /* cache this readonly data; minimize chip reads */ 695 omap->ehci->hcs_params = readl(&omap->ehci->caps->hcs_params); 696 697 ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); 698 if (ret) { 699 dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret); 700 goto err_add_hcd; 701 } 702 703 /* root ports should always stay powered */ 704 ehci_port_power(omap->ehci, 1); 705 706 return 0; 707 708err_add_hcd: 709 omap_stop_ehc(omap, hcd); 710 711err_start: 712 for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) { 713 if (omap->regulator[i]) { 714 regulator_disable(omap->regulator[i]); 715 regulator_put(omap->regulator[i]); 716 } 717 } 718 iounmap(omap->tll_base); 719 720err_tll_ioremap: 721 iounmap(omap->uhh_base); 722 723err_uhh_ioremap: 724 iounmap(hcd->regs); 725 726err_ioremap: 727 usb_put_hcd(hcd); 728 729err_create_hcd: 730 kfree(omap); 731err_disabled: 732err_pdata: 733 return ret; 734} 735 736/* may be called without controller electrically present */ 737/* may be called with controller, bus, and devices active */ 738 739/** 740 * ehci_hcd_omap_remove - shutdown processing for EHCI HCDs 741 * @pdev: USB Host Controller being removed 742 * 743 * Reverses the effect of usb_ehci_hcd_omap_probe(), first invoking 744 * the HCD's stop() method. It is always called from a thread 745 * context, normally "rmmod", "apmd", or something similar. 746 */ 747static int ehci_hcd_omap_remove(struct platform_device *pdev) 748{ 749 struct ehci_hcd_omap *omap = platform_get_drvdata(pdev); 750 struct usb_hcd *hcd = ehci_to_hcd(omap->ehci); 751 int i; 752 753 usb_remove_hcd(hcd); 754 omap_stop_ehc(omap, hcd); 755 iounmap(hcd->regs); 756 for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) { 757 if (omap->regulator[i]) { 758 regulator_disable(omap->regulator[i]); 759 regulator_put(omap->regulator[i]); 760 } 761 } 762 iounmap(omap->tll_base); 763 iounmap(omap->uhh_base); 764 usb_put_hcd(hcd); 765 kfree(omap); 766 767 return 0; 768} 769 770static void ehci_hcd_omap_shutdown(struct platform_device *pdev) 771{ 772 struct ehci_hcd_omap *omap = platform_get_drvdata(pdev); 773 struct usb_hcd *hcd = ehci_to_hcd(omap->ehci); 774 775 if (hcd->driver->shutdown) 776 hcd->driver->shutdown(hcd); 777} 778 779static struct platform_driver ehci_hcd_omap_driver = { 780 .probe = ehci_hcd_omap_probe, 781 .remove = ehci_hcd_omap_remove, 782 .shutdown = ehci_hcd_omap_shutdown, 783 /*.suspend = ehci_hcd_omap_suspend, */ 784 /*.resume = ehci_hcd_omap_resume, */ 785 .driver = { 786 .name = "ehci-omap", 787 } 788}; 789 790/*-------------------------------------------------------------------------*/ 791 792static const struct hc_driver ehci_omap_hc_driver = { 793 .description = hcd_name, 794 .product_desc = "OMAP-EHCI Host Controller", 795 .hcd_priv_size = sizeof(struct ehci_hcd), 796 797 /* 798 * generic hardware linkage 799 */ 800 .irq = ehci_irq, 801 .flags = HCD_MEMORY | HCD_USB2, 802 803 /* 804 * basic lifecycle operations 805 */ 806 .reset = ehci_init, 807 .start = ehci_run, 808 .stop = ehci_stop, 809 .shutdown = ehci_shutdown, 810 811 /* 812 * managing i/o requests and associated device resources 813 */ 814 .urb_enqueue = ehci_urb_enqueue, 815 .urb_dequeue = ehci_urb_dequeue, 816 .endpoint_disable = ehci_endpoint_disable, 817 .endpoint_reset = ehci_endpoint_reset, 818 819 /* 820 * scheduling support 821 */ 822 .get_frame_number = ehci_get_frame, 823 824 /* 825 * root hub support 826 */ 827 .hub_status_data = ehci_hub_status_data, 828 .hub_control = ehci_hub_control, 829 .bus_suspend = ehci_bus_suspend, 830 .bus_resume = ehci_bus_resume, 831 832 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, 833}; 834 835MODULE_ALIAS("platform:omap-ehci"); 836MODULE_AUTHOR("Texas Instruments, Inc."); 837MODULE_AUTHOR("Felipe Balbi <felipe.balbi@nokia.com>"); 838