1/* 2 * Intel Langwell USB Device Controller driver 3 * Copyright (C) 2008-2009, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 * 18 */ 19 20 21/* #undef DEBUG */ 22/* #undef VERBOSE */ 23 24#if defined(CONFIG_USB_LANGWELL_OTG) 25#define OTG_TRANSCEIVER 26#endif 27 28 29#include <linux/module.h> 30#include <linux/pci.h> 31#include <linux/dma-mapping.h> 32#include <linux/kernel.h> 33#include <linux/delay.h> 34#include <linux/ioport.h> 35#include <linux/sched.h> 36#include <linux/slab.h> 37#include <linux/errno.h> 38#include <linux/init.h> 39#include <linux/timer.h> 40#include <linux/list.h> 41#include <linux/interrupt.h> 42#include <linux/moduleparam.h> 43#include <linux/device.h> 44#include <linux/usb/ch9.h> 45#include <linux/usb/gadget.h> 46#include <linux/usb/otg.h> 47#include <linux/pm.h> 48#include <linux/io.h> 49#include <linux/irq.h> 50#include <asm/system.h> 51#include <asm/unaligned.h> 52 53#include "langwell_udc.h" 54 55 56#define DRIVER_DESC "Intel Langwell USB Device Controller driver" 57#define DRIVER_VERSION "16 May 2009" 58 59static const char driver_name[] = "langwell_udc"; 60static const char driver_desc[] = DRIVER_DESC; 61 62 63/* controller device global variable */ 64static struct langwell_udc *the_controller; 65 66/* for endpoint 0 operations */ 67static const struct usb_endpoint_descriptor 68langwell_ep0_desc = { 69 .bLength = USB_DT_ENDPOINT_SIZE, 70 .bDescriptorType = USB_DT_ENDPOINT, 71 .bEndpointAddress = 0, 72 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 73 .wMaxPacketSize = EP0_MAX_PKT_SIZE, 74}; 75 76 77/*-------------------------------------------------------------------------*/ 78/* debugging */ 79 80#ifdef DEBUG 81#define DBG(dev, fmt, args...) \ 82 pr_debug("%s %s: " fmt , driver_name, \ 83 pci_name(dev->pdev), ## args) 84#else 85#define DBG(dev, fmt, args...) \ 86 do { } while (0) 87#endif /* DEBUG */ 88 89 90#ifdef VERBOSE 91#define VDBG DBG 92#else 93#define VDBG(dev, fmt, args...) \ 94 do { } while (0) 95#endif /* VERBOSE */ 96 97 98#define ERROR(dev, fmt, args...) \ 99 pr_err("%s %s: " fmt , driver_name, \ 100 pci_name(dev->pdev), ## args) 101 102#define WARNING(dev, fmt, args...) \ 103 pr_warning("%s %s: " fmt , driver_name, \ 104 pci_name(dev->pdev), ## args) 105 106#define INFO(dev, fmt, args...) \ 107 pr_info("%s %s: " fmt , driver_name, \ 108 pci_name(dev->pdev), ## args) 109 110 111#ifdef VERBOSE 112static inline void print_all_registers(struct langwell_udc *dev) 113{ 114 int i; 115 116 /* Capability Registers */ 117 printk(KERN_DEBUG "Capability Registers (offset: " 118 "0x%04x, length: 0x%08x)\n", 119 CAP_REG_OFFSET, 120 (u32)sizeof(struct langwell_cap_regs)); 121 printk(KERN_DEBUG "caplength=0x%02x\n", 122 readb(&dev->cap_regs->caplength)); 123 printk(KERN_DEBUG "hciversion=0x%04x\n", 124 readw(&dev->cap_regs->hciversion)); 125 printk(KERN_DEBUG "hcsparams=0x%08x\n", 126 readl(&dev->cap_regs->hcsparams)); 127 printk(KERN_DEBUG "hccparams=0x%08x\n", 128 readl(&dev->cap_regs->hccparams)); 129 printk(KERN_DEBUG "dciversion=0x%04x\n", 130 readw(&dev->cap_regs->dciversion)); 131 printk(KERN_DEBUG "dccparams=0x%08x\n", 132 readl(&dev->cap_regs->dccparams)); 133 134 /* Operational Registers */ 135 printk(KERN_DEBUG "Operational Registers (offset: " 136 "0x%04x, length: 0x%08x)\n", 137 OP_REG_OFFSET, 138 (u32)sizeof(struct langwell_op_regs)); 139 printk(KERN_DEBUG "extsts=0x%08x\n", 140 readl(&dev->op_regs->extsts)); 141 printk(KERN_DEBUG "extintr=0x%08x\n", 142 readl(&dev->op_regs->extintr)); 143 printk(KERN_DEBUG "usbcmd=0x%08x\n", 144 readl(&dev->op_regs->usbcmd)); 145 printk(KERN_DEBUG "usbsts=0x%08x\n", 146 readl(&dev->op_regs->usbsts)); 147 printk(KERN_DEBUG "usbintr=0x%08x\n", 148 readl(&dev->op_regs->usbintr)); 149 printk(KERN_DEBUG "frindex=0x%08x\n", 150 readl(&dev->op_regs->frindex)); 151 printk(KERN_DEBUG "ctrldssegment=0x%08x\n", 152 readl(&dev->op_regs->ctrldssegment)); 153 printk(KERN_DEBUG "deviceaddr=0x%08x\n", 154 readl(&dev->op_regs->deviceaddr)); 155 printk(KERN_DEBUG "endpointlistaddr=0x%08x\n", 156 readl(&dev->op_regs->endpointlistaddr)); 157 printk(KERN_DEBUG "ttctrl=0x%08x\n", 158 readl(&dev->op_regs->ttctrl)); 159 printk(KERN_DEBUG "burstsize=0x%08x\n", 160 readl(&dev->op_regs->burstsize)); 161 printk(KERN_DEBUG "txfilltuning=0x%08x\n", 162 readl(&dev->op_regs->txfilltuning)); 163 printk(KERN_DEBUG "txttfilltuning=0x%08x\n", 164 readl(&dev->op_regs->txttfilltuning)); 165 printk(KERN_DEBUG "ic_usb=0x%08x\n", 166 readl(&dev->op_regs->ic_usb)); 167 printk(KERN_DEBUG "ulpi_viewport=0x%08x\n", 168 readl(&dev->op_regs->ulpi_viewport)); 169 printk(KERN_DEBUG "configflag=0x%08x\n", 170 readl(&dev->op_regs->configflag)); 171 printk(KERN_DEBUG "portsc1=0x%08x\n", 172 readl(&dev->op_regs->portsc1)); 173 printk(KERN_DEBUG "devlc=0x%08x\n", 174 readl(&dev->op_regs->devlc)); 175 printk(KERN_DEBUG "otgsc=0x%08x\n", 176 readl(&dev->op_regs->otgsc)); 177 printk(KERN_DEBUG "usbmode=0x%08x\n", 178 readl(&dev->op_regs->usbmode)); 179 printk(KERN_DEBUG "endptnak=0x%08x\n", 180 readl(&dev->op_regs->endptnak)); 181 printk(KERN_DEBUG "endptnaken=0x%08x\n", 182 readl(&dev->op_regs->endptnaken)); 183 printk(KERN_DEBUG "endptsetupstat=0x%08x\n", 184 readl(&dev->op_regs->endptsetupstat)); 185 printk(KERN_DEBUG "endptprime=0x%08x\n", 186 readl(&dev->op_regs->endptprime)); 187 printk(KERN_DEBUG "endptflush=0x%08x\n", 188 readl(&dev->op_regs->endptflush)); 189 printk(KERN_DEBUG "endptstat=0x%08x\n", 190 readl(&dev->op_regs->endptstat)); 191 printk(KERN_DEBUG "endptcomplete=0x%08x\n", 192 readl(&dev->op_regs->endptcomplete)); 193 194 for (i = 0; i < dev->ep_max / 2; i++) { 195 printk(KERN_DEBUG "endptctrl[%d]=0x%08x\n", 196 i, readl(&dev->op_regs->endptctrl[i])); 197 } 198} 199#endif /* VERBOSE */ 200 201 202/*-------------------------------------------------------------------------*/ 203 204#define DIR_STRING(bAddress) (((bAddress) & USB_DIR_IN) ? "in" : "out") 205 206#define is_in(ep) (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \ 207 USB_DIR_IN) : ((ep)->desc->bEndpointAddress \ 208 & USB_DIR_IN) == USB_DIR_IN) 209 210 211#ifdef DEBUG 212static char *type_string(u8 bmAttributes) 213{ 214 switch ((bmAttributes) & USB_ENDPOINT_XFERTYPE_MASK) { 215 case USB_ENDPOINT_XFER_BULK: 216 return "bulk"; 217 case USB_ENDPOINT_XFER_ISOC: 218 return "iso"; 219 case USB_ENDPOINT_XFER_INT: 220 return "int"; 221 }; 222 223 return "control"; 224} 225#endif 226 227 228/* configure endpoint control registers */ 229static void ep_reset(struct langwell_ep *ep, unsigned char ep_num, 230 unsigned char is_in, unsigned char ep_type) 231{ 232 struct langwell_udc *dev; 233 u32 endptctrl; 234 235 dev = ep->dev; 236 VDBG(dev, "---> %s()\n", __func__); 237 238 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]); 239 if (is_in) { /* TX */ 240 if (ep_num) 241 endptctrl |= EPCTRL_TXR; 242 endptctrl |= EPCTRL_TXE; 243 endptctrl |= ep_type << EPCTRL_TXT_SHIFT; 244 } else { /* RX */ 245 if (ep_num) 246 endptctrl |= EPCTRL_RXR; 247 endptctrl |= EPCTRL_RXE; 248 endptctrl |= ep_type << EPCTRL_RXT_SHIFT; 249 } 250 251 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]); 252 253 VDBG(dev, "<--- %s()\n", __func__); 254} 255 256 257/* reset ep0 dQH and endptctrl */ 258static void ep0_reset(struct langwell_udc *dev) 259{ 260 struct langwell_ep *ep; 261 int i; 262 263 VDBG(dev, "---> %s()\n", __func__); 264 265 /* ep0 in and out */ 266 for (i = 0; i < 2; i++) { 267 ep = &dev->ep[i]; 268 ep->dev = dev; 269 270 /* ep0 dQH */ 271 ep->dqh = &dev->ep_dqh[i]; 272 273 /* configure ep0 endpoint capabilities in dQH */ 274 ep->dqh->dqh_ios = 1; 275 ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE; 276 277 if (is_in(ep)) 278 ep->dqh->dqh_zlt = 0; 279 ep->dqh->dqh_mult = 0; 280 281 /* configure ep0 control registers */ 282 ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL); 283 } 284 285 VDBG(dev, "<--- %s()\n", __func__); 286 return; 287} 288 289 290/*-------------------------------------------------------------------------*/ 291 292/* endpoints operations */ 293 294/* configure endpoint, making it usable */ 295static int langwell_ep_enable(struct usb_ep *_ep, 296 const struct usb_endpoint_descriptor *desc) 297{ 298 struct langwell_udc *dev; 299 struct langwell_ep *ep; 300 u16 max = 0; 301 unsigned long flags; 302 int retval = 0; 303 unsigned char zlt, ios = 0, mult = 0; 304 305 ep = container_of(_ep, struct langwell_ep, ep); 306 dev = ep->dev; 307 VDBG(dev, "---> %s()\n", __func__); 308 309 if (!_ep || !desc || ep->desc 310 || desc->bDescriptorType != USB_DT_ENDPOINT) 311 return -EINVAL; 312 313 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) 314 return -ESHUTDOWN; 315 316 max = le16_to_cpu(desc->wMaxPacketSize); 317 318 /* 319 * disable HW zero length termination select 320 * driver handles zero length packet through req->req.zero 321 */ 322 zlt = 1; 323 324 /* 325 * sanity check type, direction, address, and then 326 * initialize the endpoint capabilities fields in dQH 327 */ 328 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { 329 case USB_ENDPOINT_XFER_CONTROL: 330 ios = 1; 331 break; 332 case USB_ENDPOINT_XFER_BULK: 333 if ((dev->gadget.speed == USB_SPEED_HIGH 334 && max != 512) 335 || (dev->gadget.speed == USB_SPEED_FULL 336 && max > 64)) { 337 goto done; 338 } 339 break; 340 case USB_ENDPOINT_XFER_INT: 341 if (strstr(ep->ep.name, "-iso")) /* bulk is ok */ 342 goto done; 343 344 switch (dev->gadget.speed) { 345 case USB_SPEED_HIGH: 346 if (max <= 1024) 347 break; 348 case USB_SPEED_FULL: 349 if (max <= 64) 350 break; 351 default: 352 if (max <= 8) 353 break; 354 goto done; 355 } 356 break; 357 case USB_ENDPOINT_XFER_ISOC: 358 if (strstr(ep->ep.name, "-bulk") 359 || strstr(ep->ep.name, "-int")) 360 goto done; 361 362 switch (dev->gadget.speed) { 363 case USB_SPEED_HIGH: 364 if (max <= 1024) 365 break; 366 case USB_SPEED_FULL: 367 if (max <= 1023) 368 break; 369 default: 370 goto done; 371 } 372 mult = (unsigned char)(1 + ((max >> 11) & 0x03)); 373 max = max & 0x8ff; /* bit 0~10 */ 374 /* 3 transactions at most */ 375 if (mult > 3) 376 goto done; 377 break; 378 default: 379 goto done; 380 } 381 382 spin_lock_irqsave(&dev->lock, flags); 383 384 /* configure endpoint capabilities in dQH */ 385 ep->dqh->dqh_ios = ios; 386 ep->dqh->dqh_mpl = cpu_to_le16(max); 387 ep->dqh->dqh_zlt = zlt; 388 ep->dqh->dqh_mult = mult; 389 390 ep->ep.maxpacket = max; 391 ep->desc = desc; 392 ep->stopped = 0; 393 ep->ep_num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; 394 395 /* ep_type */ 396 ep->ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; 397 398 /* configure endpoint control registers */ 399 ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type); 400 401 DBG(dev, "enabled %s (ep%d%s-%s), max %04x\n", 402 _ep->name, 403 ep->ep_num, 404 DIR_STRING(desc->bEndpointAddress), 405 type_string(desc->bmAttributes), 406 max); 407 408 spin_unlock_irqrestore(&dev->lock, flags); 409done: 410 VDBG(dev, "<--- %s()\n", __func__); 411 return retval; 412} 413 414 415/*-------------------------------------------------------------------------*/ 416 417/* retire a request */ 418static void done(struct langwell_ep *ep, struct langwell_request *req, 419 int status) 420{ 421 struct langwell_udc *dev = ep->dev; 422 unsigned stopped = ep->stopped; 423 struct langwell_dtd *curr_dtd, *next_dtd; 424 int i; 425 426 VDBG(dev, "---> %s()\n", __func__); 427 428 /* remove the req from ep->queue */ 429 list_del_init(&req->queue); 430 431 if (req->req.status == -EINPROGRESS) 432 req->req.status = status; 433 else 434 status = req->req.status; 435 436 /* free dTD for the request */ 437 next_dtd = req->head; 438 for (i = 0; i < req->dtd_count; i++) { 439 curr_dtd = next_dtd; 440 if (i != req->dtd_count - 1) 441 next_dtd = curr_dtd->next_dtd_virt; 442 dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma); 443 } 444 445 if (req->mapped) { 446 dma_unmap_single(&dev->pdev->dev, req->req.dma, req->req.length, 447 is_in(ep) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE); 448 req->req.dma = DMA_ADDR_INVALID; 449 req->mapped = 0; 450 } else 451 dma_sync_single_for_cpu(&dev->pdev->dev, req->req.dma, 452 req->req.length, 453 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 454 455 if (status != -ESHUTDOWN) 456 DBG(dev, "complete %s, req %p, stat %d, len %u/%u\n", 457 ep->ep.name, &req->req, status, 458 req->req.actual, req->req.length); 459 460 /* don't modify queue heads during completion callback */ 461 ep->stopped = 1; 462 463 spin_unlock(&dev->lock); 464 /* complete routine from gadget driver */ 465 if (req->req.complete) 466 req->req.complete(&ep->ep, &req->req); 467 468 spin_lock(&dev->lock); 469 ep->stopped = stopped; 470 471 VDBG(dev, "<--- %s()\n", __func__); 472} 473 474 475static void langwell_ep_fifo_flush(struct usb_ep *_ep); 476 477/* delete all endpoint requests, called with spinlock held */ 478static void nuke(struct langwell_ep *ep, int status) 479{ 480 /* called with spinlock held */ 481 ep->stopped = 1; 482 483 /* endpoint fifo flush */ 484 if (&ep->ep && ep->desc) 485 langwell_ep_fifo_flush(&ep->ep); 486 487 while (!list_empty(&ep->queue)) { 488 struct langwell_request *req = NULL; 489 req = list_entry(ep->queue.next, struct langwell_request, 490 queue); 491 done(ep, req, status); 492 } 493} 494 495 496/*-------------------------------------------------------------------------*/ 497 498/* endpoint is no longer usable */ 499static int langwell_ep_disable(struct usb_ep *_ep) 500{ 501 struct langwell_ep *ep; 502 unsigned long flags; 503 struct langwell_udc *dev; 504 int ep_num; 505 u32 endptctrl; 506 507 ep = container_of(_ep, struct langwell_ep, ep); 508 dev = ep->dev; 509 VDBG(dev, "---> %s()\n", __func__); 510 511 if (!_ep || !ep->desc) 512 return -EINVAL; 513 514 spin_lock_irqsave(&dev->lock, flags); 515 516 /* disable endpoint control register */ 517 ep_num = ep->ep_num; 518 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]); 519 if (is_in(ep)) 520 endptctrl &= ~EPCTRL_TXE; 521 else 522 endptctrl &= ~EPCTRL_RXE; 523 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]); 524 525 /* nuke all pending requests (does flush) */ 526 nuke(ep, -ESHUTDOWN); 527 528 ep->desc = NULL; 529 ep->stopped = 1; 530 531 spin_unlock_irqrestore(&dev->lock, flags); 532 533 DBG(dev, "disabled %s\n", _ep->name); 534 VDBG(dev, "<--- %s()\n", __func__); 535 536 return 0; 537} 538 539 540/* allocate a request object to use with this endpoint */ 541static struct usb_request *langwell_alloc_request(struct usb_ep *_ep, 542 gfp_t gfp_flags) 543{ 544 struct langwell_ep *ep; 545 struct langwell_udc *dev; 546 struct langwell_request *req = NULL; 547 548 if (!_ep) 549 return NULL; 550 551 ep = container_of(_ep, struct langwell_ep, ep); 552 dev = ep->dev; 553 VDBG(dev, "---> %s()\n", __func__); 554 555 req = kzalloc(sizeof(*req), gfp_flags); 556 if (!req) 557 return NULL; 558 559 req->req.dma = DMA_ADDR_INVALID; 560 INIT_LIST_HEAD(&req->queue); 561 562 VDBG(dev, "alloc request for %s\n", _ep->name); 563 VDBG(dev, "<--- %s()\n", __func__); 564 return &req->req; 565} 566 567 568/* free a request object */ 569static void langwell_free_request(struct usb_ep *_ep, 570 struct usb_request *_req) 571{ 572 struct langwell_ep *ep; 573 struct langwell_udc *dev; 574 struct langwell_request *req = NULL; 575 576 ep = container_of(_ep, struct langwell_ep, ep); 577 dev = ep->dev; 578 VDBG(dev, "---> %s()\n", __func__); 579 580 if (!_ep || !_req) 581 return; 582 583 req = container_of(_req, struct langwell_request, req); 584 WARN_ON(!list_empty(&req->queue)); 585 586 if (_req) 587 kfree(req); 588 589 VDBG(dev, "free request for %s\n", _ep->name); 590 VDBG(dev, "<--- %s()\n", __func__); 591} 592 593 594/*-------------------------------------------------------------------------*/ 595 596/* queue dTD and PRIME endpoint */ 597static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req) 598{ 599 u32 bit_mask, usbcmd, endptstat, dtd_dma; 600 u8 dtd_status; 601 int i; 602 struct langwell_dqh *dqh; 603 struct langwell_udc *dev; 604 605 dev = ep->dev; 606 VDBG(dev, "---> %s()\n", __func__); 607 608 i = ep->ep_num * 2 + is_in(ep); 609 dqh = &dev->ep_dqh[i]; 610 611 if (ep->ep_num) 612 VDBG(dev, "%s\n", ep->name); 613 else 614 /* ep0 */ 615 VDBG(dev, "%s-%s\n", ep->name, is_in(ep) ? "in" : "out"); 616 617 VDBG(dev, "ep_dqh[%d] addr: 0x%08x\n", i, (u32)&(dev->ep_dqh[i])); 618 619 bit_mask = is_in(ep) ? 620 (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num)); 621 622 VDBG(dev, "bit_mask = 0x%08x\n", bit_mask); 623 624 /* check if the pipe is empty */ 625 if (!(list_empty(&ep->queue))) { 626 /* add dTD to the end of linked list */ 627 struct langwell_request *lastreq; 628 lastreq = list_entry(ep->queue.prev, 629 struct langwell_request, queue); 630 631 lastreq->tail->dtd_next = 632 cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK); 633 634 /* read prime bit, if 1 goto out */ 635 if (readl(&dev->op_regs->endptprime) & bit_mask) 636 goto out; 637 638 do { 639 /* set ATDTW bit in USBCMD */ 640 usbcmd = readl(&dev->op_regs->usbcmd); 641 writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd); 642 643 /* read correct status bit */ 644 endptstat = readl(&dev->op_regs->endptstat) & bit_mask; 645 646 } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW)); 647 648 /* write ATDTW bit to 0 */ 649 usbcmd = readl(&dev->op_regs->usbcmd); 650 writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd); 651 652 if (endptstat) 653 goto out; 654 } 655 656 /* write dQH next pointer and terminate bit to 0 */ 657 dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK; 658 dqh->dtd_next = cpu_to_le32(dtd_dma); 659 660 /* clear active and halt bit */ 661 dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED); 662 dqh->dtd_status &= dtd_status; 663 VDBG(dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status); 664 665 /* write 1 to endptprime register to PRIME endpoint */ 666 bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num); 667 VDBG(dev, "endprime bit_mask = 0x%08x\n", bit_mask); 668 writel(bit_mask, &dev->op_regs->endptprime); 669out: 670 VDBG(dev, "<--- %s()\n", __func__); 671 return 0; 672} 673 674 675/* fill in the dTD structure to build a transfer descriptor */ 676static struct langwell_dtd *build_dtd(struct langwell_request *req, 677 unsigned *length, dma_addr_t *dma, int *is_last) 678{ 679 u32 buf_ptr; 680 struct langwell_dtd *dtd; 681 struct langwell_udc *dev; 682 int i; 683 684 dev = req->ep->dev; 685 VDBG(dev, "---> %s()\n", __func__); 686 687 /* the maximum transfer length, up to 16k bytes */ 688 *length = min(req->req.length - req->req.actual, 689 (unsigned)DTD_MAX_TRANSFER_LENGTH); 690 691 /* create dTD dma_pool resource */ 692 dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma); 693 if (dtd == NULL) 694 return dtd; 695 dtd->dtd_dma = *dma; 696 697 /* initialize buffer page pointers */ 698 buf_ptr = (u32)(req->req.dma + req->req.actual); 699 for (i = 0; i < 5; i++) 700 dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE); 701 702 req->req.actual += *length; 703 704 /* fill in total bytes with transfer size */ 705 dtd->dtd_total = cpu_to_le16(*length); 706 VDBG(dev, "dtd->dtd_total = %d\n", dtd->dtd_total); 707 708 /* set is_last flag if req->req.zero is set or not */ 709 if (req->req.zero) { 710 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0) 711 *is_last = 1; 712 else 713 *is_last = 0; 714 } else if (req->req.length == req->req.actual) { 715 *is_last = 1; 716 } else 717 *is_last = 0; 718 719 if (*is_last == 0) 720 VDBG(dev, "multi-dtd request!\n"); 721 722 /* set interrupt on complete bit for the last dTD */ 723 if (*is_last && !req->req.no_interrupt) 724 dtd->dtd_ioc = 1; 725 726 /* set multiplier override 0 for non-ISO and non-TX endpoint */ 727 dtd->dtd_multo = 0; 728 729 /* set the active bit of status field to 1 */ 730 dtd->dtd_status = DTD_STS_ACTIVE; 731 VDBG(dev, "dtd->dtd_status = 0x%02x\n", dtd->dtd_status); 732 733 VDBG(dev, "length = %d, dma addr= 0x%08x\n", *length, (int)*dma); 734 VDBG(dev, "<--- %s()\n", __func__); 735 return dtd; 736} 737 738 739/* generate dTD linked list for a request */ 740static int req_to_dtd(struct langwell_request *req) 741{ 742 unsigned count; 743 int is_last, is_first = 1; 744 struct langwell_dtd *dtd, *last_dtd = NULL; 745 struct langwell_udc *dev; 746 dma_addr_t dma; 747 748 dev = req->ep->dev; 749 VDBG(dev, "---> %s()\n", __func__); 750 do { 751 dtd = build_dtd(req, &count, &dma, &is_last); 752 if (dtd == NULL) 753 return -ENOMEM; 754 755 if (is_first) { 756 is_first = 0; 757 req->head = dtd; 758 } else { 759 last_dtd->dtd_next = cpu_to_le32(dma); 760 last_dtd->next_dtd_virt = dtd; 761 } 762 last_dtd = dtd; 763 req->dtd_count++; 764 } while (!is_last); 765 766 /* set terminate bit to 1 for the last dTD */ 767 dtd->dtd_next = DTD_TERM; 768 769 req->tail = dtd; 770 771 VDBG(dev, "<--- %s()\n", __func__); 772 return 0; 773} 774 775/*-------------------------------------------------------------------------*/ 776 777/* queue (submits) an I/O requests to an endpoint */ 778static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req, 779 gfp_t gfp_flags) 780{ 781 struct langwell_request *req; 782 struct langwell_ep *ep; 783 struct langwell_udc *dev; 784 unsigned long flags; 785 int is_iso = 0, zlflag = 0; 786 787 /* always require a cpu-view buffer */ 788 req = container_of(_req, struct langwell_request, req); 789 ep = container_of(_ep, struct langwell_ep, ep); 790 791 if (!_req || !_req->complete || !_req->buf 792 || !list_empty(&req->queue)) { 793 return -EINVAL; 794 } 795 796 if (unlikely(!_ep || !ep->desc)) 797 return -EINVAL; 798 799 dev = ep->dev; 800 req->ep = ep; 801 VDBG(dev, "---> %s()\n", __func__); 802 803 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 804 if (req->req.length > ep->ep.maxpacket) 805 return -EMSGSIZE; 806 is_iso = 1; 807 } 808 809 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) 810 return -ESHUTDOWN; 811 812 /* set up dma mapping in case the caller didn't */ 813 if (_req->dma == DMA_ADDR_INVALID) { 814 if (_req->length == 0) { 815 VDBG(dev, "req->length: 0->1\n"); 816 zlflag = 1; 817 _req->length++; 818 } 819 820 _req->dma = dma_map_single(&dev->pdev->dev, 821 _req->buf, _req->length, 822 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 823 if (zlflag && (_req->length == 1)) { 824 VDBG(dev, "req->length: 1->0\n"); 825 zlflag = 0; 826 _req->length = 0; 827 } 828 829 req->mapped = 1; 830 VDBG(dev, "req->mapped = 1\n"); 831 } else { 832 dma_sync_single_for_device(&dev->pdev->dev, 833 _req->dma, _req->length, 834 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 835 req->mapped = 0; 836 VDBG(dev, "req->mapped = 0\n"); 837 } 838 839 DBG(dev, "%s queue req %p, len %u, buf %p, dma 0x%08llx\n", 840 _ep->name, 841 _req, _req->length, _req->buf, (unsigned long long)_req->dma); 842 843 _req->status = -EINPROGRESS; 844 _req->actual = 0; 845 req->dtd_count = 0; 846 847 spin_lock_irqsave(&dev->lock, flags); 848 849 /* build and put dTDs to endpoint queue */ 850 if (!req_to_dtd(req)) { 851 queue_dtd(ep, req); 852 } else { 853 spin_unlock_irqrestore(&dev->lock, flags); 854 return -ENOMEM; 855 } 856 857 /* update ep0 state */ 858 if (ep->ep_num == 0) 859 dev->ep0_state = DATA_STATE_XMIT; 860 861 if (likely(req != NULL)) { 862 list_add_tail(&req->queue, &ep->queue); 863 VDBG(dev, "list_add_tail() \n"); 864 } 865 866 spin_unlock_irqrestore(&dev->lock, flags); 867 868 VDBG(dev, "<--- %s()\n", __func__); 869 return 0; 870} 871 872 873/* dequeue (cancels, unlinks) an I/O request from an endpoint */ 874static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 875{ 876 struct langwell_ep *ep; 877 struct langwell_udc *dev; 878 struct langwell_request *req; 879 unsigned long flags; 880 int stopped, ep_num, retval = 0; 881 u32 endptctrl; 882 883 ep = container_of(_ep, struct langwell_ep, ep); 884 dev = ep->dev; 885 VDBG(dev, "---> %s()\n", __func__); 886 887 if (!_ep || !ep->desc || !_req) 888 return -EINVAL; 889 890 if (!dev->driver) 891 return -ESHUTDOWN; 892 893 spin_lock_irqsave(&dev->lock, flags); 894 stopped = ep->stopped; 895 896 /* quiesce dma while we patch the queue */ 897 ep->stopped = 1; 898 ep_num = ep->ep_num; 899 900 /* disable endpoint control register */ 901 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]); 902 if (is_in(ep)) 903 endptctrl &= ~EPCTRL_TXE; 904 else 905 endptctrl &= ~EPCTRL_RXE; 906 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]); 907 908 /* make sure it's still queued on this endpoint */ 909 list_for_each_entry(req, &ep->queue, queue) { 910 if (&req->req == _req) 911 break; 912 } 913 914 if (&req->req != _req) { 915 retval = -EINVAL; 916 goto done; 917 } 918 919 /* queue head may be partially complete. */ 920 if (ep->queue.next == &req->queue) { 921 DBG(dev, "unlink (%s) dma\n", _ep->name); 922 _req->status = -ECONNRESET; 923 langwell_ep_fifo_flush(&ep->ep); 924 925 /* not the last request in endpoint queue */ 926 if (likely(ep->queue.next == &req->queue)) { 927 struct langwell_dqh *dqh; 928 struct langwell_request *next_req; 929 930 dqh = ep->dqh; 931 next_req = list_entry(req->queue.next, 932 struct langwell_request, queue); 933 934 /* point the dQH to the first dTD of next request */ 935 writel((u32) next_req->head, &dqh->dqh_current); 936 } 937 } else { 938 struct langwell_request *prev_req; 939 940 prev_req = list_entry(req->queue.prev, 941 struct langwell_request, queue); 942 writel(readl(&req->tail->dtd_next), 943 &prev_req->tail->dtd_next); 944 } 945 946 done(ep, req, -ECONNRESET); 947 948done: 949 /* enable endpoint again */ 950 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]); 951 if (is_in(ep)) 952 endptctrl |= EPCTRL_TXE; 953 else 954 endptctrl |= EPCTRL_RXE; 955 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]); 956 957 ep->stopped = stopped; 958 spin_unlock_irqrestore(&dev->lock, flags); 959 960 VDBG(dev, "<--- %s()\n", __func__); 961 return retval; 962} 963 964 965/*-------------------------------------------------------------------------*/ 966 967/* endpoint set/clear halt */ 968static void ep_set_halt(struct langwell_ep *ep, int value) 969{ 970 u32 endptctrl = 0; 971 int ep_num; 972 struct langwell_udc *dev = ep->dev; 973 VDBG(dev, "---> %s()\n", __func__); 974 975 ep_num = ep->ep_num; 976 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]); 977 978 /* value: 1 - set halt, 0 - clear halt */ 979 if (value) { 980 /* set the stall bit */ 981 if (is_in(ep)) 982 endptctrl |= EPCTRL_TXS; 983 else 984 endptctrl |= EPCTRL_RXS; 985 } else { 986 /* clear the stall bit and reset data toggle */ 987 if (is_in(ep)) { 988 endptctrl &= ~EPCTRL_TXS; 989 endptctrl |= EPCTRL_TXR; 990 } else { 991 endptctrl &= ~EPCTRL_RXS; 992 endptctrl |= EPCTRL_RXR; 993 } 994 } 995 996 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]); 997 998 VDBG(dev, "<--- %s()\n", __func__); 999} 1000 1001 1002/* set the endpoint halt feature */ 1003static int langwell_ep_set_halt(struct usb_ep *_ep, int value) 1004{ 1005 struct langwell_ep *ep; 1006 struct langwell_udc *dev; 1007 unsigned long flags; 1008 int retval = 0; 1009 1010 ep = container_of(_ep, struct langwell_ep, ep); 1011 dev = ep->dev; 1012 1013 VDBG(dev, "---> %s()\n", __func__); 1014 1015 if (!_ep || !ep->desc) 1016 return -EINVAL; 1017 1018 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) 1019 return -ESHUTDOWN; 1020 1021 if (ep->desc && (ep->desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) 1022 == USB_ENDPOINT_XFER_ISOC) 1023 return -EOPNOTSUPP; 1024 1025 spin_lock_irqsave(&dev->lock, flags); 1026 1027 /* 1028 * attempt to halt IN ep will fail if any transfer requests 1029 * are still queue 1030 */ 1031 if (!list_empty(&ep->queue) && is_in(ep) && value) { 1032 /* IN endpoint FIFO holds bytes */ 1033 DBG(dev, "%s FIFO holds bytes\n", _ep->name); 1034 retval = -EAGAIN; 1035 goto done; 1036 } 1037 1038 /* endpoint set/clear halt */ 1039 if (ep->ep_num) { 1040 ep_set_halt(ep, value); 1041 } else { /* endpoint 0 */ 1042 dev->ep0_state = WAIT_FOR_SETUP; 1043 dev->ep0_dir = USB_DIR_OUT; 1044 } 1045done: 1046 spin_unlock_irqrestore(&dev->lock, flags); 1047 DBG(dev, "%s %s halt\n", _ep->name, value ? "set" : "clear"); 1048 VDBG(dev, "<--- %s()\n", __func__); 1049 return retval; 1050} 1051 1052 1053/* set the halt feature and ignores clear requests */ 1054static int langwell_ep_set_wedge(struct usb_ep *_ep) 1055{ 1056 struct langwell_ep *ep; 1057 struct langwell_udc *dev; 1058 1059 ep = container_of(_ep, struct langwell_ep, ep); 1060 dev = ep->dev; 1061 1062 VDBG(dev, "---> %s()\n", __func__); 1063 1064 if (!_ep || !ep->desc) 1065 return -EINVAL; 1066 1067 VDBG(dev, "<--- %s()\n", __func__); 1068 return usb_ep_set_halt(_ep); 1069} 1070 1071 1072/* flush contents of a fifo */ 1073static void langwell_ep_fifo_flush(struct usb_ep *_ep) 1074{ 1075 struct langwell_ep *ep; 1076 struct langwell_udc *dev; 1077 u32 flush_bit; 1078 unsigned long timeout; 1079 1080 ep = container_of(_ep, struct langwell_ep, ep); 1081 dev = ep->dev; 1082 1083 VDBG(dev, "---> %s()\n", __func__); 1084 1085 if (!_ep || !ep->desc) { 1086 VDBG(dev, "ep or ep->desc is NULL\n"); 1087 VDBG(dev, "<--- %s()\n", __func__); 1088 return; 1089 } 1090 1091 VDBG(dev, "%s-%s fifo flush\n", _ep->name, is_in(ep) ? "in" : "out"); 1092 1093 /* flush endpoint buffer */ 1094 if (ep->ep_num == 0) 1095 flush_bit = (1 << 16) | 1; 1096 else if (is_in(ep)) 1097 flush_bit = 1 << (ep->ep_num + 16); /* TX */ 1098 else 1099 flush_bit = 1 << ep->ep_num; /* RX */ 1100 1101 /* wait until flush complete */ 1102 timeout = jiffies + FLUSH_TIMEOUT; 1103 do { 1104 writel(flush_bit, &dev->op_regs->endptflush); 1105 while (readl(&dev->op_regs->endptflush)) { 1106 if (time_after(jiffies, timeout)) { 1107 ERROR(dev, "ep flush timeout\n"); 1108 goto done; 1109 } 1110 cpu_relax(); 1111 } 1112 } while (readl(&dev->op_regs->endptstat) & flush_bit); 1113done: 1114 VDBG(dev, "<--- %s()\n", __func__); 1115} 1116 1117 1118/* endpoints operations structure */ 1119static const struct usb_ep_ops langwell_ep_ops = { 1120 1121 /* configure endpoint, making it usable */ 1122 .enable = langwell_ep_enable, 1123 1124 /* endpoint is no longer usable */ 1125 .disable = langwell_ep_disable, 1126 1127 /* allocate a request object to use with this endpoint */ 1128 .alloc_request = langwell_alloc_request, 1129 1130 /* free a request object */ 1131 .free_request = langwell_free_request, 1132 1133 /* queue (submits) an I/O requests to an endpoint */ 1134 .queue = langwell_ep_queue, 1135 1136 /* dequeue (cancels, unlinks) an I/O request from an endpoint */ 1137 .dequeue = langwell_ep_dequeue, 1138 1139 /* set the endpoint halt feature */ 1140 .set_halt = langwell_ep_set_halt, 1141 1142 /* set the halt feature and ignores clear requests */ 1143 .set_wedge = langwell_ep_set_wedge, 1144 1145 /* flush contents of a fifo */ 1146 .fifo_flush = langwell_ep_fifo_flush, 1147}; 1148 1149 1150/*-------------------------------------------------------------------------*/ 1151 1152/* device controller usb_gadget_ops structure */ 1153 1154/* returns the current frame number */ 1155static int langwell_get_frame(struct usb_gadget *_gadget) 1156{ 1157 struct langwell_udc *dev; 1158 u16 retval; 1159 1160 if (!_gadget) 1161 return -ENODEV; 1162 1163 dev = container_of(_gadget, struct langwell_udc, gadget); 1164 VDBG(dev, "---> %s()\n", __func__); 1165 1166 retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK; 1167 1168 VDBG(dev, "<--- %s()\n", __func__); 1169 return retval; 1170} 1171 1172 1173/* tries to wake up the host connected to this gadget */ 1174static int langwell_wakeup(struct usb_gadget *_gadget) 1175{ 1176 struct langwell_udc *dev; 1177 u32 portsc1, devlc; 1178 unsigned long flags; 1179 1180 if (!_gadget) 1181 return 0; 1182 1183 dev = container_of(_gadget, struct langwell_udc, gadget); 1184 VDBG(dev, "---> %s()\n", __func__); 1185 1186 /* Remote Wakeup feature not enabled by host */ 1187 if (!dev->remote_wakeup) 1188 return -ENOTSUPP; 1189 1190 spin_lock_irqsave(&dev->lock, flags); 1191 1192 portsc1 = readl(&dev->op_regs->portsc1); 1193 if (!(portsc1 & PORTS_SUSP)) { 1194 spin_unlock_irqrestore(&dev->lock, flags); 1195 return 0; 1196 } 1197 1198 /* LPM L1 to L0, remote wakeup */ 1199 if (dev->lpm && dev->lpm_state == LPM_L1) { 1200 portsc1 |= PORTS_SLP; 1201 writel(portsc1, &dev->op_regs->portsc1); 1202 } 1203 1204 /* force port resume */ 1205 if (dev->usb_state == USB_STATE_SUSPENDED) { 1206 portsc1 |= PORTS_FPR; 1207 writel(portsc1, &dev->op_regs->portsc1); 1208 } 1209 1210 /* exit PHY low power suspend */ 1211 devlc = readl(&dev->op_regs->devlc); 1212 VDBG(dev, "devlc = 0x%08x\n", devlc); 1213 devlc &= ~LPM_PHCD; 1214 writel(devlc, &dev->op_regs->devlc); 1215 1216 spin_unlock_irqrestore(&dev->lock, flags); 1217 1218 VDBG(dev, "<--- %s()\n", __func__); 1219 return 0; 1220} 1221 1222 1223/* notify controller that VBUS is powered or not */ 1224static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active) 1225{ 1226 struct langwell_udc *dev; 1227 unsigned long flags; 1228 u32 usbcmd; 1229 1230 if (!_gadget) 1231 return -ENODEV; 1232 1233 dev = container_of(_gadget, struct langwell_udc, gadget); 1234 VDBG(dev, "---> %s()\n", __func__); 1235 1236 spin_lock_irqsave(&dev->lock, flags); 1237 VDBG(dev, "VBUS status: %s\n", is_active ? "on" : "off"); 1238 1239 dev->vbus_active = (is_active != 0); 1240 if (dev->driver && dev->softconnected && dev->vbus_active) { 1241 usbcmd = readl(&dev->op_regs->usbcmd); 1242 usbcmd |= CMD_RUNSTOP; 1243 writel(usbcmd, &dev->op_regs->usbcmd); 1244 } else { 1245 usbcmd = readl(&dev->op_regs->usbcmd); 1246 usbcmd &= ~CMD_RUNSTOP; 1247 writel(usbcmd, &dev->op_regs->usbcmd); 1248 } 1249 1250 spin_unlock_irqrestore(&dev->lock, flags); 1251 1252 VDBG(dev, "<--- %s()\n", __func__); 1253 return 0; 1254} 1255 1256 1257/* constrain controller's VBUS power usage */ 1258static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA) 1259{ 1260 struct langwell_udc *dev; 1261 1262 if (!_gadget) 1263 return -ENODEV; 1264 1265 dev = container_of(_gadget, struct langwell_udc, gadget); 1266 VDBG(dev, "---> %s()\n", __func__); 1267 1268 if (dev->transceiver) { 1269 VDBG(dev, "otg_set_power\n"); 1270 VDBG(dev, "<--- %s()\n", __func__); 1271 return otg_set_power(dev->transceiver, mA); 1272 } 1273 1274 VDBG(dev, "<--- %s()\n", __func__); 1275 return -ENOTSUPP; 1276} 1277 1278 1279/* D+ pullup, software-controlled connect/disconnect to USB host */ 1280static int langwell_pullup(struct usb_gadget *_gadget, int is_on) 1281{ 1282 struct langwell_udc *dev; 1283 u32 usbcmd; 1284 unsigned long flags; 1285 1286 if (!_gadget) 1287 return -ENODEV; 1288 1289 dev = container_of(_gadget, struct langwell_udc, gadget); 1290 1291 VDBG(dev, "---> %s()\n", __func__); 1292 1293 spin_lock_irqsave(&dev->lock, flags); 1294 dev->softconnected = (is_on != 0); 1295 1296 if (dev->driver && dev->softconnected && dev->vbus_active) { 1297 usbcmd = readl(&dev->op_regs->usbcmd); 1298 usbcmd |= CMD_RUNSTOP; 1299 writel(usbcmd, &dev->op_regs->usbcmd); 1300 } else { 1301 usbcmd = readl(&dev->op_regs->usbcmd); 1302 usbcmd &= ~CMD_RUNSTOP; 1303 writel(usbcmd, &dev->op_regs->usbcmd); 1304 } 1305 spin_unlock_irqrestore(&dev->lock, flags); 1306 1307 VDBG(dev, "<--- %s()\n", __func__); 1308 return 0; 1309} 1310 1311 1312/* device controller usb_gadget_ops structure */ 1313static const struct usb_gadget_ops langwell_ops = { 1314 1315 /* returns the current frame number */ 1316 .get_frame = langwell_get_frame, 1317 1318 /* tries to wake up the host connected to this gadget */ 1319 .wakeup = langwell_wakeup, 1320 1321 /* set the device selfpowered feature, always selfpowered */ 1322 /* .set_selfpowered = langwell_set_selfpowered, */ 1323 1324 /* notify controller that VBUS is powered or not */ 1325 .vbus_session = langwell_vbus_session, 1326 1327 /* constrain controller's VBUS power usage */ 1328 .vbus_draw = langwell_vbus_draw, 1329 1330 /* D+ pullup, software-controlled connect/disconnect to USB host */ 1331 .pullup = langwell_pullup, 1332}; 1333 1334 1335/*-------------------------------------------------------------------------*/ 1336 1337/* device controller operations */ 1338 1339/* reset device controller */ 1340static int langwell_udc_reset(struct langwell_udc *dev) 1341{ 1342 u32 usbcmd, usbmode, devlc, endpointlistaddr; 1343 unsigned long timeout; 1344 1345 if (!dev) 1346 return -EINVAL; 1347 1348 DBG(dev, "---> %s()\n", __func__); 1349 1350 /* set controller to stop state */ 1351 usbcmd = readl(&dev->op_regs->usbcmd); 1352 usbcmd &= ~CMD_RUNSTOP; 1353 writel(usbcmd, &dev->op_regs->usbcmd); 1354 1355 /* reset device controller */ 1356 usbcmd = readl(&dev->op_regs->usbcmd); 1357 usbcmd |= CMD_RST; 1358 writel(usbcmd, &dev->op_regs->usbcmd); 1359 1360 /* wait for reset to complete */ 1361 timeout = jiffies + RESET_TIMEOUT; 1362 while (readl(&dev->op_regs->usbcmd) & CMD_RST) { 1363 if (time_after(jiffies, timeout)) { 1364 ERROR(dev, "device reset timeout\n"); 1365 return -ETIMEDOUT; 1366 } 1367 cpu_relax(); 1368 } 1369 1370 /* set controller to device mode */ 1371 usbmode = readl(&dev->op_regs->usbmode); 1372 usbmode |= MODE_DEVICE; 1373 1374 /* turn setup lockout off, require setup tripwire in usbcmd */ 1375 usbmode |= MODE_SLOM; 1376 1377 writel(usbmode, &dev->op_regs->usbmode); 1378 usbmode = readl(&dev->op_regs->usbmode); 1379 VDBG(dev, "usbmode=0x%08x\n", usbmode); 1380 1381 /* Write-Clear setup status */ 1382 writel(0, &dev->op_regs->usbsts); 1383 1384 /* if support USB LPM, ACK all LPM token */ 1385 if (dev->lpm) { 1386 devlc = readl(&dev->op_regs->devlc); 1387 devlc &= ~LPM_STL; /* don't STALL LPM token */ 1388 devlc &= ~LPM_NYT_ACK; /* ACK LPM token */ 1389 writel(devlc, &dev->op_regs->devlc); 1390 } 1391 1392 /* fill endpointlistaddr register */ 1393 endpointlistaddr = dev->ep_dqh_dma; 1394 endpointlistaddr &= ENDPOINTLISTADDR_MASK; 1395 writel(endpointlistaddr, &dev->op_regs->endpointlistaddr); 1396 1397 VDBG(dev, "dQH base (vir: %p, phy: 0x%08x), endpointlistaddr=0x%08x\n", 1398 dev->ep_dqh, endpointlistaddr, 1399 readl(&dev->op_regs->endpointlistaddr)); 1400 DBG(dev, "<--- %s()\n", __func__); 1401 return 0; 1402} 1403 1404 1405/* reinitialize device controller endpoints */ 1406static int eps_reinit(struct langwell_udc *dev) 1407{ 1408 struct langwell_ep *ep; 1409 char name[14]; 1410 int i; 1411 1412 VDBG(dev, "---> %s()\n", __func__); 1413 1414 /* initialize ep0 */ 1415 ep = &dev->ep[0]; 1416 ep->dev = dev; 1417 strncpy(ep->name, "ep0", sizeof(ep->name)); 1418 ep->ep.name = ep->name; 1419 ep->ep.ops = &langwell_ep_ops; 1420 ep->stopped = 0; 1421 ep->ep.maxpacket = EP0_MAX_PKT_SIZE; 1422 ep->ep_num = 0; 1423 ep->desc = &langwell_ep0_desc; 1424 INIT_LIST_HEAD(&ep->queue); 1425 1426 ep->ep_type = USB_ENDPOINT_XFER_CONTROL; 1427 1428 /* initialize other endpoints */ 1429 for (i = 2; i < dev->ep_max; i++) { 1430 ep = &dev->ep[i]; 1431 if (i % 2) 1432 snprintf(name, sizeof(name), "ep%din", i / 2); 1433 else 1434 snprintf(name, sizeof(name), "ep%dout", i / 2); 1435 ep->dev = dev; 1436 strncpy(ep->name, name, sizeof(ep->name)); 1437 ep->ep.name = ep->name; 1438 1439 ep->ep.ops = &langwell_ep_ops; 1440 ep->stopped = 0; 1441 ep->ep.maxpacket = (unsigned short) ~0; 1442 ep->ep_num = i / 2; 1443 1444 INIT_LIST_HEAD(&ep->queue); 1445 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); 1446 1447 ep->dqh = &dev->ep_dqh[i]; 1448 } 1449 1450 VDBG(dev, "<--- %s()\n", __func__); 1451 return 0; 1452} 1453 1454 1455/* enable interrupt and set controller to run state */ 1456static void langwell_udc_start(struct langwell_udc *dev) 1457{ 1458 u32 usbintr, usbcmd; 1459 DBG(dev, "---> %s()\n", __func__); 1460 1461 /* enable interrupts */ 1462 usbintr = INTR_ULPIE /* ULPI */ 1463 | INTR_SLE /* suspend */ 1464 /* | INTR_SRE SOF received */ 1465 | INTR_URE /* USB reset */ 1466 | INTR_AAE /* async advance */ 1467 | INTR_SEE /* system error */ 1468 | INTR_FRE /* frame list rollover */ 1469 | INTR_PCE /* port change detect */ 1470 | INTR_UEE /* USB error interrupt */ 1471 | INTR_UE; /* USB interrupt */ 1472 writel(usbintr, &dev->op_regs->usbintr); 1473 1474 /* clear stopped bit */ 1475 dev->stopped = 0; 1476 1477 /* set controller to run */ 1478 usbcmd = readl(&dev->op_regs->usbcmd); 1479 usbcmd |= CMD_RUNSTOP; 1480 writel(usbcmd, &dev->op_regs->usbcmd); 1481 1482 DBG(dev, "<--- %s()\n", __func__); 1483 return; 1484} 1485 1486 1487/* disable interrupt and set controller to stop state */ 1488static void langwell_udc_stop(struct langwell_udc *dev) 1489{ 1490 u32 usbcmd; 1491 1492 DBG(dev, "---> %s()\n", __func__); 1493 1494 /* disable all interrupts */ 1495 writel(0, &dev->op_regs->usbintr); 1496 1497 /* set stopped bit */ 1498 dev->stopped = 1; 1499 1500 /* set controller to stop state */ 1501 usbcmd = readl(&dev->op_regs->usbcmd); 1502 usbcmd &= ~CMD_RUNSTOP; 1503 writel(usbcmd, &dev->op_regs->usbcmd); 1504 1505 DBG(dev, "<--- %s()\n", __func__); 1506 return; 1507} 1508 1509 1510/* stop all USB activities */ 1511static void stop_activity(struct langwell_udc *dev, 1512 struct usb_gadget_driver *driver) 1513{ 1514 struct langwell_ep *ep; 1515 DBG(dev, "---> %s()\n", __func__); 1516 1517 nuke(&dev->ep[0], -ESHUTDOWN); 1518 1519 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) { 1520 nuke(ep, -ESHUTDOWN); 1521 } 1522 1523 /* report disconnect; the driver is already quiesced */ 1524 if (driver) { 1525 spin_unlock(&dev->lock); 1526 driver->disconnect(&dev->gadget); 1527 spin_lock(&dev->lock); 1528 } 1529 1530 DBG(dev, "<--- %s()\n", __func__); 1531} 1532 1533 1534/*-------------------------------------------------------------------------*/ 1535 1536/* device "function" sysfs attribute file */ 1537static ssize_t show_function(struct device *_dev, 1538 struct device_attribute *attr, char *buf) 1539{ 1540 struct langwell_udc *dev = the_controller; 1541 1542 if (!dev->driver || !dev->driver->function 1543 || strlen(dev->driver->function) > PAGE_SIZE) 1544 return 0; 1545 1546 return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function); 1547} 1548static DEVICE_ATTR(function, S_IRUGO, show_function, NULL); 1549 1550 1551/* device "langwell_udc" sysfs attribute file */ 1552static ssize_t show_langwell_udc(struct device *_dev, 1553 struct device_attribute *attr, char *buf) 1554{ 1555 struct langwell_udc *dev = the_controller; 1556 struct langwell_request *req; 1557 struct langwell_ep *ep = NULL; 1558 char *next; 1559 unsigned size; 1560 unsigned t; 1561 unsigned i; 1562 unsigned long flags; 1563 u32 tmp_reg; 1564 1565 next = buf; 1566 size = PAGE_SIZE; 1567 spin_lock_irqsave(&dev->lock, flags); 1568 1569 /* driver basic information */ 1570 t = scnprintf(next, size, 1571 DRIVER_DESC "\n" 1572 "%s version: %s\n" 1573 "Gadget driver: %s\n\n", 1574 driver_name, DRIVER_VERSION, 1575 dev->driver ? dev->driver->driver.name : "(none)"); 1576 size -= t; 1577 next += t; 1578 1579 /* device registers */ 1580 tmp_reg = readl(&dev->op_regs->usbcmd); 1581 t = scnprintf(next, size, 1582 "USBCMD reg:\n" 1583 "SetupTW: %d\n" 1584 "Run/Stop: %s\n\n", 1585 (tmp_reg & CMD_SUTW) ? 1 : 0, 1586 (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop"); 1587 size -= t; 1588 next += t; 1589 1590 tmp_reg = readl(&dev->op_regs->usbsts); 1591 t = scnprintf(next, size, 1592 "USB Status Reg:\n" 1593 "Device Suspend: %d\n" 1594 "Reset Received: %d\n" 1595 "System Error: %s\n" 1596 "USB Error Interrupt: %s\n\n", 1597 (tmp_reg & STS_SLI) ? 1 : 0, 1598 (tmp_reg & STS_URI) ? 1 : 0, 1599 (tmp_reg & STS_SEI) ? "Error" : "No error", 1600 (tmp_reg & STS_UEI) ? "Error detected" : "No error"); 1601 size -= t; 1602 next += t; 1603 1604 tmp_reg = readl(&dev->op_regs->usbintr); 1605 t = scnprintf(next, size, 1606 "USB Intrrupt Enable Reg:\n" 1607 "Sleep Enable: %d\n" 1608 "SOF Received Enable: %d\n" 1609 "Reset Enable: %d\n" 1610 "System Error Enable: %d\n" 1611 "Port Change Dectected Enable: %d\n" 1612 "USB Error Intr Enable: %d\n" 1613 "USB Intr Enable: %d\n\n", 1614 (tmp_reg & INTR_SLE) ? 1 : 0, 1615 (tmp_reg & INTR_SRE) ? 1 : 0, 1616 (tmp_reg & INTR_URE) ? 1 : 0, 1617 (tmp_reg & INTR_SEE) ? 1 : 0, 1618 (tmp_reg & INTR_PCE) ? 1 : 0, 1619 (tmp_reg & INTR_UEE) ? 1 : 0, 1620 (tmp_reg & INTR_UE) ? 1 : 0); 1621 size -= t; 1622 next += t; 1623 1624 tmp_reg = readl(&dev->op_regs->frindex); 1625 t = scnprintf(next, size, 1626 "USB Frame Index Reg:\n" 1627 "Frame Number is 0x%08x\n\n", 1628 (tmp_reg & FRINDEX_MASK)); 1629 size -= t; 1630 next += t; 1631 1632 tmp_reg = readl(&dev->op_regs->deviceaddr); 1633 t = scnprintf(next, size, 1634 "USB Device Address Reg:\n" 1635 "Device Addr is 0x%x\n\n", 1636 USBADR(tmp_reg)); 1637 size -= t; 1638 next += t; 1639 1640 tmp_reg = readl(&dev->op_regs->endpointlistaddr); 1641 t = scnprintf(next, size, 1642 "USB Endpoint List Address Reg:\n" 1643 "Endpoint List Pointer is 0x%x\n\n", 1644 EPBASE(tmp_reg)); 1645 size -= t; 1646 next += t; 1647 1648 tmp_reg = readl(&dev->op_regs->portsc1); 1649 t = scnprintf(next, size, 1650 "USB Port Status & Control Reg:\n" 1651 "Port Reset: %s\n" 1652 "Port Suspend Mode: %s\n" 1653 "Over-current Change: %s\n" 1654 "Port Enable/Disable Change: %s\n" 1655 "Port Enabled/Disabled: %s\n" 1656 "Current Connect Status: %s\n\n", 1657 (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset", 1658 (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend", 1659 (tmp_reg & PORTS_OCC) ? "Detected" : "No", 1660 (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed", 1661 (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct", 1662 (tmp_reg & PORTS_CCS) ? "Attached" : "Not Attached"); 1663 size -= t; 1664 next += t; 1665 1666 tmp_reg = readl(&dev->op_regs->devlc); 1667 t = scnprintf(next, size, 1668 "Device LPM Control Reg:\n" 1669 "Parallel Transceiver : %d\n" 1670 "Serial Transceiver : %d\n" 1671 "Port Speed: %s\n" 1672 "Port Force Full Speed Connenct: %s\n" 1673 "PHY Low Power Suspend Clock Disable: %s\n" 1674 "BmAttributes: %d\n\n", 1675 LPM_PTS(tmp_reg), 1676 (tmp_reg & LPM_STS) ? 1 : 0, 1677 ({ 1678 char *s; 1679 switch (LPM_PSPD(tmp_reg)) { 1680 case LPM_SPEED_FULL: 1681 s = "Full Speed"; break; 1682 case LPM_SPEED_LOW: 1683 s = "Low Speed"; break; 1684 case LPM_SPEED_HIGH: 1685 s = "High Speed"; break; 1686 default: 1687 s = "Unknown Speed"; break; 1688 } 1689 s; 1690 }), 1691 (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force", 1692 (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled", 1693 LPM_BA(tmp_reg)); 1694 size -= t; 1695 next += t; 1696 1697 tmp_reg = readl(&dev->op_regs->usbmode); 1698 t = scnprintf(next, size, 1699 "USB Mode Reg:\n" 1700 "Controller Mode is : %s\n\n", ({ 1701 char *s; 1702 switch (MODE_CM(tmp_reg)) { 1703 case MODE_IDLE: 1704 s = "Idle"; break; 1705 case MODE_DEVICE: 1706 s = "Device Controller"; break; 1707 case MODE_HOST: 1708 s = "Host Controller"; break; 1709 default: 1710 s = "None"; break; 1711 } 1712 s; 1713 })); 1714 size -= t; 1715 next += t; 1716 1717 tmp_reg = readl(&dev->op_regs->endptsetupstat); 1718 t = scnprintf(next, size, 1719 "Endpoint Setup Status Reg:\n" 1720 "SETUP on ep 0x%04x\n\n", 1721 tmp_reg & SETUPSTAT_MASK); 1722 size -= t; 1723 next += t; 1724 1725 for (i = 0; i < dev->ep_max / 2; i++) { 1726 tmp_reg = readl(&dev->op_regs->endptctrl[i]); 1727 t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n", 1728 i, tmp_reg); 1729 size -= t; 1730 next += t; 1731 } 1732 tmp_reg = readl(&dev->op_regs->endptprime); 1733 t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg); 1734 size -= t; 1735 next += t; 1736 1737 /* langwell_udc, langwell_ep, langwell_request structure information */ 1738 ep = &dev->ep[0]; 1739 t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n", 1740 ep->ep.name, ep->ep.maxpacket, ep->ep_num); 1741 size -= t; 1742 next += t; 1743 1744 if (list_empty(&ep->queue)) { 1745 t = scnprintf(next, size, "its req queue is empty\n\n"); 1746 size -= t; 1747 next += t; 1748 } else { 1749 list_for_each_entry(req, &ep->queue, queue) { 1750 t = scnprintf(next, size, 1751 "req %p actual 0x%x length 0x%x buf %p\n", 1752 &req->req, req->req.actual, 1753 req->req.length, req->req.buf); 1754 size -= t; 1755 next += t; 1756 } 1757 } 1758 /* other gadget->eplist ep */ 1759 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) { 1760 if (ep->desc) { 1761 t = scnprintf(next, size, 1762 "\n%s MaxPacketSize: 0x%x, " 1763 "ep_num: %d\n", 1764 ep->ep.name, ep->ep.maxpacket, 1765 ep->ep_num); 1766 size -= t; 1767 next += t; 1768 1769 if (list_empty(&ep->queue)) { 1770 t = scnprintf(next, size, 1771 "its req queue is empty\n\n"); 1772 size -= t; 1773 next += t; 1774 } else { 1775 list_for_each_entry(req, &ep->queue, queue) { 1776 t = scnprintf(next, size, 1777 "req %p actual 0x%x length " 1778 "0x%x buf %p\n", 1779 &req->req, req->req.actual, 1780 req->req.length, req->req.buf); 1781 size -= t; 1782 next += t; 1783 } 1784 } 1785 } 1786 } 1787 1788 spin_unlock_irqrestore(&dev->lock, flags); 1789 return PAGE_SIZE - size; 1790} 1791static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL); 1792 1793 1794/*-------------------------------------------------------------------------*/ 1795 1796/* 1797 * when a driver is successfully registered, it will receive 1798 * control requests including set_configuration(), which enables 1799 * non-control requests. then usb traffic follows until a 1800 * disconnect is reported. then a host may connect again, or 1801 * the driver might get unbound. 1802 */ 1803 1804int usb_gadget_register_driver(struct usb_gadget_driver *driver) 1805{ 1806 struct langwell_udc *dev = the_controller; 1807 unsigned long flags; 1808 int retval; 1809 1810 if (!dev) 1811 return -ENODEV; 1812 1813 DBG(dev, "---> %s()\n", __func__); 1814 1815 if (dev->driver) 1816 return -EBUSY; 1817 1818 spin_lock_irqsave(&dev->lock, flags); 1819 1820 /* hook up the driver ... */ 1821 driver->driver.bus = NULL; 1822 dev->driver = driver; 1823 dev->gadget.dev.driver = &driver->driver; 1824 1825 spin_unlock_irqrestore(&dev->lock, flags); 1826 1827 retval = driver->bind(&dev->gadget); 1828 if (retval) { 1829 DBG(dev, "bind to driver %s --> %d\n", 1830 driver->driver.name, retval); 1831 dev->driver = NULL; 1832 dev->gadget.dev.driver = NULL; 1833 return retval; 1834 } 1835 1836 retval = device_create_file(&dev->pdev->dev, &dev_attr_function); 1837 if (retval) 1838 goto err_unbind; 1839 1840 dev->usb_state = USB_STATE_ATTACHED; 1841 dev->ep0_state = WAIT_FOR_SETUP; 1842 dev->ep0_dir = USB_DIR_OUT; 1843 1844 /* enable interrupt and set controller to run state */ 1845 if (dev->got_irq) 1846 langwell_udc_start(dev); 1847 1848 VDBG(dev, "After langwell_udc_start(), print all registers:\n"); 1849#ifdef VERBOSE 1850 print_all_registers(dev); 1851#endif 1852 1853 INFO(dev, "register driver: %s\n", driver->driver.name); 1854 VDBG(dev, "<--- %s()\n", __func__); 1855 return 0; 1856 1857err_unbind: 1858 driver->unbind(&dev->gadget); 1859 dev->gadget.dev.driver = NULL; 1860 dev->driver = NULL; 1861 1862 DBG(dev, "<--- %s()\n", __func__); 1863 return retval; 1864} 1865EXPORT_SYMBOL(usb_gadget_register_driver); 1866 1867 1868/* unregister gadget driver */ 1869int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) 1870{ 1871 struct langwell_udc *dev = the_controller; 1872 unsigned long flags; 1873 1874 if (!dev) 1875 return -ENODEV; 1876 1877 DBG(dev, "---> %s()\n", __func__); 1878 1879 if (unlikely(!driver || !driver->bind || !driver->unbind)) 1880 return -EINVAL; 1881 1882 /* unbind OTG transceiver */ 1883 if (dev->transceiver) 1884 (void)otg_set_peripheral(dev->transceiver, 0); 1885 1886 /* disable interrupt and set controller to stop state */ 1887 langwell_udc_stop(dev); 1888 1889 dev->usb_state = USB_STATE_ATTACHED; 1890 dev->ep0_state = WAIT_FOR_SETUP; 1891 dev->ep0_dir = USB_DIR_OUT; 1892 1893 spin_lock_irqsave(&dev->lock, flags); 1894 1895 /* stop all usb activities */ 1896 dev->gadget.speed = USB_SPEED_UNKNOWN; 1897 stop_activity(dev, driver); 1898 spin_unlock_irqrestore(&dev->lock, flags); 1899 1900 /* unbind gadget driver */ 1901 driver->unbind(&dev->gadget); 1902 dev->gadget.dev.driver = NULL; 1903 dev->driver = NULL; 1904 1905 device_remove_file(&dev->pdev->dev, &dev_attr_function); 1906 1907 INFO(dev, "unregistered driver '%s'\n", driver->driver.name); 1908 DBG(dev, "<--- %s()\n", __func__); 1909 return 0; 1910} 1911EXPORT_SYMBOL(usb_gadget_unregister_driver); 1912 1913 1914/*-------------------------------------------------------------------------*/ 1915 1916/* 1917 * setup tripwire is used as a semaphore to ensure that the setup data 1918 * payload is extracted from a dQH without being corrupted 1919 */ 1920static void setup_tripwire(struct langwell_udc *dev) 1921{ 1922 u32 usbcmd, 1923 endptsetupstat; 1924 unsigned long timeout; 1925 struct langwell_dqh *dqh; 1926 1927 VDBG(dev, "---> %s()\n", __func__); 1928 1929 /* ep0 OUT dQH */ 1930 dqh = &dev->ep_dqh[EP_DIR_OUT]; 1931 1932 /* Write-Clear endptsetupstat */ 1933 endptsetupstat = readl(&dev->op_regs->endptsetupstat); 1934 writel(endptsetupstat, &dev->op_regs->endptsetupstat); 1935 1936 /* wait until endptsetupstat is cleared */ 1937 timeout = jiffies + SETUPSTAT_TIMEOUT; 1938 while (readl(&dev->op_regs->endptsetupstat)) { 1939 if (time_after(jiffies, timeout)) { 1940 ERROR(dev, "setup_tripwire timeout\n"); 1941 break; 1942 } 1943 cpu_relax(); 1944 } 1945 1946 /* while a hazard exists when setup packet arrives */ 1947 do { 1948 /* set setup tripwire bit */ 1949 usbcmd = readl(&dev->op_regs->usbcmd); 1950 writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd); 1951 1952 /* copy the setup packet to local buffer */ 1953 memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8); 1954 } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW)); 1955 1956 /* Write-Clear setup tripwire bit */ 1957 usbcmd = readl(&dev->op_regs->usbcmd); 1958 writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd); 1959 1960 VDBG(dev, "<--- %s()\n", __func__); 1961} 1962 1963 1964/* protocol ep0 stall, will automatically be cleared on new transaction */ 1965static void ep0_stall(struct langwell_udc *dev) 1966{ 1967 u32 endptctrl; 1968 1969 VDBG(dev, "---> %s()\n", __func__); 1970 1971 /* set TX and RX to stall */ 1972 endptctrl = readl(&dev->op_regs->endptctrl[0]); 1973 endptctrl |= EPCTRL_TXS | EPCTRL_RXS; 1974 writel(endptctrl, &dev->op_regs->endptctrl[0]); 1975 1976 /* update ep0 state */ 1977 dev->ep0_state = WAIT_FOR_SETUP; 1978 dev->ep0_dir = USB_DIR_OUT; 1979 1980 VDBG(dev, "<--- %s()\n", __func__); 1981} 1982 1983 1984/* PRIME a status phase for ep0 */ 1985static int prime_status_phase(struct langwell_udc *dev, int dir) 1986{ 1987 struct langwell_request *req; 1988 struct langwell_ep *ep; 1989 int status = 0; 1990 1991 VDBG(dev, "---> %s()\n", __func__); 1992 1993 if (dir == EP_DIR_IN) 1994 dev->ep0_dir = USB_DIR_IN; 1995 else 1996 dev->ep0_dir = USB_DIR_OUT; 1997 1998 ep = &dev->ep[0]; 1999 dev->ep0_state = WAIT_FOR_OUT_STATUS; 2000 2001 req = dev->status_req; 2002 2003 req->ep = ep; 2004 req->req.length = 0; 2005 req->req.status = -EINPROGRESS; 2006 req->req.actual = 0; 2007 req->req.complete = NULL; 2008 req->dtd_count = 0; 2009 2010 if (!req_to_dtd(req)) 2011 status = queue_dtd(ep, req); 2012 else 2013 return -ENOMEM; 2014 2015 if (status) 2016 ERROR(dev, "can't queue ep0 status request\n"); 2017 2018 list_add_tail(&req->queue, &ep->queue); 2019 2020 VDBG(dev, "<--- %s()\n", __func__); 2021 return status; 2022} 2023 2024 2025/* SET_ADDRESS request routine */ 2026static void set_address(struct langwell_udc *dev, u16 value, 2027 u16 index, u16 length) 2028{ 2029 VDBG(dev, "---> %s()\n", __func__); 2030 2031 /* save the new address to device struct */ 2032 dev->dev_addr = (u8) value; 2033 VDBG(dev, "dev->dev_addr = %d\n", dev->dev_addr); 2034 2035 /* update usb state */ 2036 dev->usb_state = USB_STATE_ADDRESS; 2037 2038 /* STATUS phase */ 2039 if (prime_status_phase(dev, EP_DIR_IN)) 2040 ep0_stall(dev); 2041 2042 VDBG(dev, "<--- %s()\n", __func__); 2043} 2044 2045 2046/* return endpoint by windex */ 2047static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev, 2048 u16 wIndex) 2049{ 2050 struct langwell_ep *ep; 2051 VDBG(dev, "---> %s()\n", __func__); 2052 2053 if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0) 2054 return &dev->ep[0]; 2055 2056 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) { 2057 u8 bEndpointAddress; 2058 if (!ep->desc) 2059 continue; 2060 2061 bEndpointAddress = ep->desc->bEndpointAddress; 2062 if ((wIndex ^ bEndpointAddress) & USB_DIR_IN) 2063 continue; 2064 2065 if ((wIndex & USB_ENDPOINT_NUMBER_MASK) 2066 == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)) 2067 return ep; 2068 } 2069 2070 VDBG(dev, "<--- %s()\n", __func__); 2071 return NULL; 2072} 2073 2074 2075/* return whether endpoint is stalled, 0: not stalled; 1: stalled */ 2076static int ep_is_stall(struct langwell_ep *ep) 2077{ 2078 struct langwell_udc *dev = ep->dev; 2079 u32 endptctrl; 2080 int retval; 2081 2082 VDBG(dev, "---> %s()\n", __func__); 2083 2084 endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]); 2085 if (is_in(ep)) 2086 retval = endptctrl & EPCTRL_TXS ? 1 : 0; 2087 else 2088 retval = endptctrl & EPCTRL_RXS ? 1 : 0; 2089 2090 VDBG(dev, "<--- %s()\n", __func__); 2091 return retval; 2092} 2093 2094 2095/* GET_STATUS request routine */ 2096static void get_status(struct langwell_udc *dev, u8 request_type, u16 value, 2097 u16 index, u16 length) 2098{ 2099 struct langwell_request *req; 2100 struct langwell_ep *ep; 2101 u16 status_data = 0; /* 16 bits cpu view status data */ 2102 int status = 0; 2103 2104 VDBG(dev, "---> %s()\n", __func__); 2105 2106 ep = &dev->ep[0]; 2107 2108 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) { 2109 /* get device status */ 2110 status_data = 1 << USB_DEVICE_SELF_POWERED; 2111 status_data |= dev->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP; 2112 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) { 2113 /* get interface status */ 2114 status_data = 0; 2115 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) { 2116 /* get endpoint status */ 2117 struct langwell_ep *epn; 2118 epn = get_ep_by_windex(dev, index); 2119 /* stall if endpoint doesn't exist */ 2120 if (!epn) 2121 goto stall; 2122 2123 status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT; 2124 } 2125 2126 dev->ep0_dir = USB_DIR_IN; 2127 2128 /* borrow the per device status_req */ 2129 req = dev->status_req; 2130 2131 /* fill in the reqest structure */ 2132 *((u16 *) req->req.buf) = cpu_to_le16(status_data); 2133 req->ep = ep; 2134 req->req.length = 2; 2135 req->req.status = -EINPROGRESS; 2136 req->req.actual = 0; 2137 req->req.complete = NULL; 2138 req->dtd_count = 0; 2139 2140 /* prime the data phase */ 2141 if (!req_to_dtd(req)) 2142 status = queue_dtd(ep, req); 2143 else /* no mem */ 2144 goto stall; 2145 2146 if (status) { 2147 ERROR(dev, "response error on GET_STATUS request\n"); 2148 goto stall; 2149 } 2150 2151 list_add_tail(&req->queue, &ep->queue); 2152 dev->ep0_state = DATA_STATE_XMIT; 2153 2154 VDBG(dev, "<--- %s()\n", __func__); 2155 return; 2156stall: 2157 ep0_stall(dev); 2158 VDBG(dev, "<--- %s()\n", __func__); 2159} 2160 2161 2162/* setup packet interrupt handler */ 2163static void handle_setup_packet(struct langwell_udc *dev, 2164 struct usb_ctrlrequest *setup) 2165{ 2166 u16 wValue = le16_to_cpu(setup->wValue); 2167 u16 wIndex = le16_to_cpu(setup->wIndex); 2168 u16 wLength = le16_to_cpu(setup->wLength); 2169 2170 VDBG(dev, "---> %s()\n", __func__); 2171 2172 /* ep0 fifo flush */ 2173 nuke(&dev->ep[0], -ESHUTDOWN); 2174 2175 DBG(dev, "SETUP %02x.%02x v%04x i%04x l%04x\n", 2176 setup->bRequestType, setup->bRequest, 2177 wValue, wIndex, wLength); 2178 2179 /* RNDIS gadget delegate */ 2180 if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) { 2181 /* USB_CDC_SEND_ENCAPSULATED_COMMAND */ 2182 goto delegate; 2183 } 2184 2185 /* USB_CDC_GET_ENCAPSULATED_RESPONSE */ 2186 if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) { 2187 /* USB_CDC_GET_ENCAPSULATED_RESPONSE */ 2188 goto delegate; 2189 } 2190 2191 /* We process some stardard setup requests here */ 2192 switch (setup->bRequest) { 2193 case USB_REQ_GET_STATUS: 2194 DBG(dev, "SETUP: USB_REQ_GET_STATUS\n"); 2195 /* get status, DATA and STATUS phase */ 2196 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK)) 2197 != (USB_DIR_IN | USB_TYPE_STANDARD)) 2198 break; 2199 get_status(dev, setup->bRequestType, wValue, wIndex, wLength); 2200 goto end; 2201 2202 case USB_REQ_SET_ADDRESS: 2203 DBG(dev, "SETUP: USB_REQ_SET_ADDRESS\n"); 2204 /* STATUS phase */ 2205 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD 2206 | USB_RECIP_DEVICE)) 2207 break; 2208 set_address(dev, wValue, wIndex, wLength); 2209 goto end; 2210 2211 case USB_REQ_CLEAR_FEATURE: 2212 case USB_REQ_SET_FEATURE: 2213 /* STATUS phase */ 2214 { 2215 int rc = -EOPNOTSUPP; 2216 if (setup->bRequest == USB_REQ_SET_FEATURE) 2217 DBG(dev, "SETUP: USB_REQ_SET_FEATURE\n"); 2218 else if (setup->bRequest == USB_REQ_CLEAR_FEATURE) 2219 DBG(dev, "SETUP: USB_REQ_CLEAR_FEATURE\n"); 2220 2221 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK)) 2222 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) { 2223 struct langwell_ep *epn; 2224 epn = get_ep_by_windex(dev, wIndex); 2225 /* stall if endpoint doesn't exist */ 2226 if (!epn) { 2227 ep0_stall(dev); 2228 goto end; 2229 } 2230 2231 if (wValue != 0 || wLength != 0 2232 || epn->ep_num > dev->ep_max) 2233 break; 2234 2235 spin_unlock(&dev->lock); 2236 rc = langwell_ep_set_halt(&epn->ep, 2237 (setup->bRequest == USB_REQ_SET_FEATURE) 2238 ? 1 : 0); 2239 spin_lock(&dev->lock); 2240 2241 } else if ((setup->bRequestType & (USB_RECIP_MASK 2242 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE 2243 | USB_TYPE_STANDARD)) { 2244 if (!gadget_is_otg(&dev->gadget)) 2245 break; 2246 else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE) { 2247 dev->gadget.b_hnp_enable = 1; 2248#ifdef OTG_TRANSCEIVER 2249 if (!dev->lotg->otg.default_a) 2250 dev->lotg->hsm.b_hnp_enable = 1; 2251#endif 2252 } else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT) 2253 dev->gadget.a_hnp_support = 1; 2254 else if (setup->bRequest == 2255 USB_DEVICE_A_ALT_HNP_SUPPORT) 2256 dev->gadget.a_alt_hnp_support = 1; 2257 else 2258 break; 2259 rc = 0; 2260 } else 2261 break; 2262 2263 if (rc == 0) { 2264 if (prime_status_phase(dev, EP_DIR_IN)) 2265 ep0_stall(dev); 2266 } 2267 goto end; 2268 } 2269 2270 case USB_REQ_GET_DESCRIPTOR: 2271 DBG(dev, "SETUP: USB_REQ_GET_DESCRIPTOR\n"); 2272 goto delegate; 2273 2274 case USB_REQ_SET_DESCRIPTOR: 2275 DBG(dev, "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n"); 2276 goto delegate; 2277 2278 case USB_REQ_GET_CONFIGURATION: 2279 DBG(dev, "SETUP: USB_REQ_GET_CONFIGURATION\n"); 2280 goto delegate; 2281 2282 case USB_REQ_SET_CONFIGURATION: 2283 DBG(dev, "SETUP: USB_REQ_SET_CONFIGURATION\n"); 2284 goto delegate; 2285 2286 case USB_REQ_GET_INTERFACE: 2287 DBG(dev, "SETUP: USB_REQ_GET_INTERFACE\n"); 2288 goto delegate; 2289 2290 case USB_REQ_SET_INTERFACE: 2291 DBG(dev, "SETUP: USB_REQ_SET_INTERFACE\n"); 2292 goto delegate; 2293 2294 case USB_REQ_SYNCH_FRAME: 2295 DBG(dev, "SETUP: USB_REQ_SYNCH_FRAME unsupported\n"); 2296 goto delegate; 2297 2298 default: 2299 /* delegate USB standard requests to the gadget driver */ 2300 goto delegate; 2301delegate: 2302 /* USB requests handled by gadget */ 2303 if (wLength) { 2304 /* DATA phase from gadget, STATUS phase from udc */ 2305 dev->ep0_dir = (setup->bRequestType & USB_DIR_IN) 2306 ? USB_DIR_IN : USB_DIR_OUT; 2307 VDBG(dev, "dev->ep0_dir = 0x%x, wLength = %d\n", 2308 dev->ep0_dir, wLength); 2309 spin_unlock(&dev->lock); 2310 if (dev->driver->setup(&dev->gadget, 2311 &dev->local_setup_buff) < 0) 2312 ep0_stall(dev); 2313 spin_lock(&dev->lock); 2314 dev->ep0_state = (setup->bRequestType & USB_DIR_IN) 2315 ? DATA_STATE_XMIT : DATA_STATE_RECV; 2316 } else { 2317 /* no DATA phase, IN STATUS phase from gadget */ 2318 dev->ep0_dir = USB_DIR_IN; 2319 VDBG(dev, "dev->ep0_dir = 0x%x, wLength = %d\n", 2320 dev->ep0_dir, wLength); 2321 spin_unlock(&dev->lock); 2322 if (dev->driver->setup(&dev->gadget, 2323 &dev->local_setup_buff) < 0) 2324 ep0_stall(dev); 2325 spin_lock(&dev->lock); 2326 dev->ep0_state = WAIT_FOR_OUT_STATUS; 2327 } 2328 break; 2329 } 2330end: 2331 VDBG(dev, "<--- %s()\n", __func__); 2332 return; 2333} 2334 2335 2336/* transfer completion, process endpoint request and free the completed dTDs 2337 * for this request 2338 */ 2339static int process_ep_req(struct langwell_udc *dev, int index, 2340 struct langwell_request *curr_req) 2341{ 2342 struct langwell_dtd *curr_dtd; 2343 struct langwell_dqh *curr_dqh; 2344 int td_complete, actual, remaining_length; 2345 int i, dir; 2346 u8 dtd_status = 0; 2347 int retval = 0; 2348 2349 curr_dqh = &dev->ep_dqh[index]; 2350 dir = index % 2; 2351 2352 curr_dtd = curr_req->head; 2353 td_complete = 0; 2354 actual = curr_req->req.length; 2355 2356 VDBG(dev, "---> %s()\n", __func__); 2357 2358 for (i = 0; i < curr_req->dtd_count; i++) { 2359 remaining_length = le16_to_cpu(curr_dtd->dtd_total); 2360 actual -= remaining_length; 2361 2362 /* command execution states by dTD */ 2363 dtd_status = curr_dtd->dtd_status; 2364 2365 if (!dtd_status) { 2366 /* transfers completed successfully */ 2367 if (!remaining_length) { 2368 td_complete++; 2369 VDBG(dev, "dTD transmitted successfully\n"); 2370 } else { 2371 if (dir) { 2372 VDBG(dev, "TX dTD remains data\n"); 2373 retval = -EPROTO; 2374 break; 2375 2376 } else { 2377 td_complete++; 2378 break; 2379 } 2380 } 2381 } else { 2382 /* transfers completed with errors */ 2383 if (dtd_status & DTD_STS_ACTIVE) { 2384 DBG(dev, "request not completed\n"); 2385 retval = 1; 2386 return retval; 2387 } else if (dtd_status & DTD_STS_HALTED) { 2388 ERROR(dev, "dTD error %08x dQH[%d]\n", 2389 dtd_status, index); 2390 /* clear the errors and halt condition */ 2391 curr_dqh->dtd_status = 0; 2392 retval = -EPIPE; 2393 break; 2394 } else if (dtd_status & DTD_STS_DBE) { 2395 DBG(dev, "data buffer (overflow) error\n"); 2396 retval = -EPROTO; 2397 break; 2398 } else if (dtd_status & DTD_STS_TRE) { 2399 DBG(dev, "transaction(ISO) error\n"); 2400 retval = -EILSEQ; 2401 break; 2402 } else 2403 ERROR(dev, "unknown error (0x%x)!\n", 2404 dtd_status); 2405 } 2406 2407 if (i != curr_req->dtd_count - 1) 2408 curr_dtd = (struct langwell_dtd *) 2409 curr_dtd->next_dtd_virt; 2410 } 2411 2412 if (retval) 2413 return retval; 2414 2415 curr_req->req.actual = actual; 2416 2417 VDBG(dev, "<--- %s()\n", __func__); 2418 return 0; 2419} 2420 2421 2422/* complete DATA or STATUS phase of ep0 prime status phase if needed */ 2423static void ep0_req_complete(struct langwell_udc *dev, 2424 struct langwell_ep *ep0, struct langwell_request *req) 2425{ 2426 u32 new_addr; 2427 VDBG(dev, "---> %s()\n", __func__); 2428 2429 if (dev->usb_state == USB_STATE_ADDRESS) { 2430 /* set the new address */ 2431 new_addr = (u32)dev->dev_addr; 2432 writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr); 2433 2434 new_addr = USBADR(readl(&dev->op_regs->deviceaddr)); 2435 VDBG(dev, "new_addr = %d\n", new_addr); 2436 } 2437 2438 done(ep0, req, 0); 2439 2440 switch (dev->ep0_state) { 2441 case DATA_STATE_XMIT: 2442 /* receive status phase */ 2443 if (prime_status_phase(dev, EP_DIR_OUT)) 2444 ep0_stall(dev); 2445 break; 2446 case DATA_STATE_RECV: 2447 /* send status phase */ 2448 if (prime_status_phase(dev, EP_DIR_IN)) 2449 ep0_stall(dev); 2450 break; 2451 case WAIT_FOR_OUT_STATUS: 2452 dev->ep0_state = WAIT_FOR_SETUP; 2453 break; 2454 case WAIT_FOR_SETUP: 2455 ERROR(dev, "unexpect ep0 packets\n"); 2456 break; 2457 default: 2458 ep0_stall(dev); 2459 break; 2460 } 2461 2462 VDBG(dev, "<--- %s()\n", __func__); 2463} 2464 2465 2466/* USB transfer completion interrupt */ 2467static void handle_trans_complete(struct langwell_udc *dev) 2468{ 2469 u32 complete_bits; 2470 int i, ep_num, dir, bit_mask, status; 2471 struct langwell_ep *epn; 2472 struct langwell_request *curr_req, *temp_req; 2473 2474 VDBG(dev, "---> %s()\n", __func__); 2475 2476 complete_bits = readl(&dev->op_regs->endptcomplete); 2477 VDBG(dev, "endptcomplete register: 0x%08x\n", complete_bits); 2478 2479 /* Write-Clear the bits in endptcomplete register */ 2480 writel(complete_bits, &dev->op_regs->endptcomplete); 2481 2482 if (!complete_bits) { 2483 DBG(dev, "complete_bits = 0\n"); 2484 goto done; 2485 } 2486 2487 for (i = 0; i < dev->ep_max; i++) { 2488 ep_num = i / 2; 2489 dir = i % 2; 2490 2491 bit_mask = 1 << (ep_num + 16 * dir); 2492 2493 if (!(complete_bits & bit_mask)) 2494 continue; 2495 2496 /* ep0 */ 2497 if (i == 1) 2498 epn = &dev->ep[0]; 2499 else 2500 epn = &dev->ep[i]; 2501 2502 if (epn->name == NULL) { 2503 WARNING(dev, "invalid endpoint\n"); 2504 continue; 2505 } 2506 2507 if (i < 2) 2508 /* ep0 in and out */ 2509 DBG(dev, "%s-%s transfer completed\n", 2510 epn->name, 2511 is_in(epn) ? "in" : "out"); 2512 else 2513 DBG(dev, "%s transfer completed\n", epn->name); 2514 2515 /* process the req queue until an uncomplete request */ 2516 list_for_each_entry_safe(curr_req, temp_req, 2517 &epn->queue, queue) { 2518 status = process_ep_req(dev, i, curr_req); 2519 VDBG(dev, "%s req status: %d\n", epn->name, status); 2520 2521 if (status) 2522 break; 2523 2524 /* write back status to req */ 2525 curr_req->req.status = status; 2526 2527 /* ep0 request completion */ 2528 if (ep_num == 0) { 2529 ep0_req_complete(dev, epn, curr_req); 2530 break; 2531 } else { 2532 done(epn, curr_req, status); 2533 } 2534 } 2535 } 2536done: 2537 VDBG(dev, "<--- %s()\n", __func__); 2538 return; 2539} 2540 2541 2542/* port change detect interrupt handler */ 2543static void handle_port_change(struct langwell_udc *dev) 2544{ 2545 u32 portsc1, devlc; 2546 u32 speed; 2547 2548 VDBG(dev, "---> %s()\n", __func__); 2549 2550 if (dev->bus_reset) 2551 dev->bus_reset = 0; 2552 2553 portsc1 = readl(&dev->op_regs->portsc1); 2554 devlc = readl(&dev->op_regs->devlc); 2555 VDBG(dev, "portsc1 = 0x%08x, devlc = 0x%08x\n", 2556 portsc1, devlc); 2557 2558 /* bus reset is finished */ 2559 if (!(portsc1 & PORTS_PR)) { 2560 /* get the speed */ 2561 speed = LPM_PSPD(devlc); 2562 switch (speed) { 2563 case LPM_SPEED_HIGH: 2564 dev->gadget.speed = USB_SPEED_HIGH; 2565 break; 2566 case LPM_SPEED_FULL: 2567 dev->gadget.speed = USB_SPEED_FULL; 2568 break; 2569 case LPM_SPEED_LOW: 2570 dev->gadget.speed = USB_SPEED_LOW; 2571 break; 2572 default: 2573 dev->gadget.speed = USB_SPEED_UNKNOWN; 2574 break; 2575 } 2576 VDBG(dev, "speed = %d, dev->gadget.speed = %d\n", 2577 speed, dev->gadget.speed); 2578 } 2579 2580 /* LPM L0 to L1 */ 2581 if (dev->lpm && dev->lpm_state == LPM_L0) 2582 if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) { 2583 INFO(dev, "LPM L0 to L1\n"); 2584 dev->lpm_state = LPM_L1; 2585 } 2586 2587 /* LPM L1 to L0, force resume or remote wakeup finished */ 2588 if (dev->lpm && dev->lpm_state == LPM_L1) 2589 if (!(portsc1 & PORTS_SUSP)) { 2590 if (portsc1 & PORTS_SLP) 2591 INFO(dev, "LPM L1 to L0, force resume\n"); 2592 else 2593 INFO(dev, "LPM L1 to L0, remote wakeup\n"); 2594 2595 dev->lpm_state = LPM_L0; 2596 } 2597 2598 /* update USB state */ 2599 if (!dev->resume_state) 2600 dev->usb_state = USB_STATE_DEFAULT; 2601 2602 VDBG(dev, "<--- %s()\n", __func__); 2603} 2604 2605 2606/* USB reset interrupt handler */ 2607static void handle_usb_reset(struct langwell_udc *dev) 2608{ 2609 u32 deviceaddr, 2610 endptsetupstat, 2611 endptcomplete; 2612 unsigned long timeout; 2613 2614 VDBG(dev, "---> %s()\n", __func__); 2615 2616 /* Write-Clear the device address */ 2617 deviceaddr = readl(&dev->op_regs->deviceaddr); 2618 writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr); 2619 2620 dev->dev_addr = 0; 2621 2622 /* clear usb state */ 2623 dev->resume_state = 0; 2624 2625 /* LPM L1 to L0, reset */ 2626 if (dev->lpm) 2627 dev->lpm_state = LPM_L0; 2628 2629 dev->ep0_dir = USB_DIR_OUT; 2630 dev->ep0_state = WAIT_FOR_SETUP; 2631 dev->remote_wakeup = 0; /* default to 0 on reset */ 2632 dev->gadget.b_hnp_enable = 0; 2633 dev->gadget.a_hnp_support = 0; 2634 dev->gadget.a_alt_hnp_support = 0; 2635 2636 /* Write-Clear all the setup token semaphores */ 2637 endptsetupstat = readl(&dev->op_regs->endptsetupstat); 2638 writel(endptsetupstat, &dev->op_regs->endptsetupstat); 2639 2640 /* Write-Clear all the endpoint complete status bits */ 2641 endptcomplete = readl(&dev->op_regs->endptcomplete); 2642 writel(endptcomplete, &dev->op_regs->endptcomplete); 2643 2644 /* wait until all endptprime bits cleared */ 2645 timeout = jiffies + PRIME_TIMEOUT; 2646 while (readl(&dev->op_regs->endptprime)) { 2647 if (time_after(jiffies, timeout)) { 2648 ERROR(dev, "USB reset timeout\n"); 2649 break; 2650 } 2651 cpu_relax(); 2652 } 2653 2654 /* write 1s to endptflush register to clear any primed buffers */ 2655 writel((u32) ~0, &dev->op_regs->endptflush); 2656 2657 if (readl(&dev->op_regs->portsc1) & PORTS_PR) { 2658 VDBG(dev, "USB bus reset\n"); 2659 /* bus is reseting */ 2660 dev->bus_reset = 1; 2661 2662 /* reset all the queues, stop all USB activities */ 2663 stop_activity(dev, dev->driver); 2664 dev->usb_state = USB_STATE_DEFAULT; 2665 } else { 2666 VDBG(dev, "device controller reset\n"); 2667 /* controller reset */ 2668 langwell_udc_reset(dev); 2669 2670 /* reset all the queues, stop all USB activities */ 2671 stop_activity(dev, dev->driver); 2672 2673 /* reset ep0 dQH and endptctrl */ 2674 ep0_reset(dev); 2675 2676 /* enable interrupt and set controller to run state */ 2677 langwell_udc_start(dev); 2678 2679 dev->usb_state = USB_STATE_ATTACHED; 2680 } 2681 2682#ifdef OTG_TRANSCEIVER 2683 /* refer to USB OTG 6.6.2.3 b_hnp_en is cleared */ 2684 if (!dev->lotg->otg.default_a) 2685 dev->lotg->hsm.b_hnp_enable = 0; 2686#endif 2687 2688 VDBG(dev, "<--- %s()\n", __func__); 2689} 2690 2691 2692/* USB bus suspend/resume interrupt */ 2693static void handle_bus_suspend(struct langwell_udc *dev) 2694{ 2695 u32 devlc; 2696 DBG(dev, "---> %s()\n", __func__); 2697 2698 dev->resume_state = dev->usb_state; 2699 dev->usb_state = USB_STATE_SUSPENDED; 2700 2701#ifdef OTG_TRANSCEIVER 2702 if (dev->lotg->otg.default_a) { 2703 if (dev->lotg->hsm.b_bus_suspend_vld == 1) { 2704 dev->lotg->hsm.b_bus_suspend = 1; 2705 /* notify transceiver the state changes */ 2706 if (spin_trylock(&dev->lotg->wq_lock)) { 2707 langwell_update_transceiver(); 2708 spin_unlock(&dev->lotg->wq_lock); 2709 } 2710 } 2711 dev->lotg->hsm.b_bus_suspend_vld++; 2712 } else { 2713 if (!dev->lotg->hsm.a_bus_suspend) { 2714 dev->lotg->hsm.a_bus_suspend = 1; 2715 /* notify transceiver the state changes */ 2716 if (spin_trylock(&dev->lotg->wq_lock)) { 2717 langwell_update_transceiver(); 2718 spin_unlock(&dev->lotg->wq_lock); 2719 } 2720 } 2721 } 2722#endif 2723 2724 /* report suspend to the driver */ 2725 if (dev->driver) { 2726 if (dev->driver->suspend) { 2727 spin_unlock(&dev->lock); 2728 dev->driver->suspend(&dev->gadget); 2729 spin_lock(&dev->lock); 2730 DBG(dev, "suspend %s\n", dev->driver->driver.name); 2731 } 2732 } 2733 2734 /* enter PHY low power suspend */ 2735 devlc = readl(&dev->op_regs->devlc); 2736 VDBG(dev, "devlc = 0x%08x\n", devlc); 2737 devlc |= LPM_PHCD; 2738 writel(devlc, &dev->op_regs->devlc); 2739 2740 DBG(dev, "<--- %s()\n", __func__); 2741} 2742 2743 2744static void handle_bus_resume(struct langwell_udc *dev) 2745{ 2746 u32 devlc; 2747 DBG(dev, "---> %s()\n", __func__); 2748 2749 dev->usb_state = dev->resume_state; 2750 dev->resume_state = 0; 2751 2752 /* exit PHY low power suspend */ 2753 devlc = readl(&dev->op_regs->devlc); 2754 VDBG(dev, "devlc = 0x%08x\n", devlc); 2755 devlc &= ~LPM_PHCD; 2756 writel(devlc, &dev->op_regs->devlc); 2757 2758#ifdef OTG_TRANSCEIVER 2759 if (dev->lotg->otg.default_a == 0) 2760 dev->lotg->hsm.a_bus_suspend = 0; 2761#endif 2762 2763 /* report resume to the driver */ 2764 if (dev->driver) { 2765 if (dev->driver->resume) { 2766 spin_unlock(&dev->lock); 2767 dev->driver->resume(&dev->gadget); 2768 spin_lock(&dev->lock); 2769 DBG(dev, "resume %s\n", dev->driver->driver.name); 2770 } 2771 } 2772 2773 DBG(dev, "<--- %s()\n", __func__); 2774} 2775 2776 2777/* USB device controller interrupt handler */ 2778static irqreturn_t langwell_irq(int irq, void *_dev) 2779{ 2780 struct langwell_udc *dev = _dev; 2781 u32 usbsts, 2782 usbintr, 2783 irq_sts, 2784 portsc1; 2785 2786 VDBG(dev, "---> %s()\n", __func__); 2787 2788 if (dev->stopped) { 2789 VDBG(dev, "handle IRQ_NONE\n"); 2790 VDBG(dev, "<--- %s()\n", __func__); 2791 return IRQ_NONE; 2792 } 2793 2794 spin_lock(&dev->lock); 2795 2796 /* USB status */ 2797 usbsts = readl(&dev->op_regs->usbsts); 2798 2799 /* USB interrupt enable */ 2800 usbintr = readl(&dev->op_regs->usbintr); 2801 2802 irq_sts = usbsts & usbintr; 2803 VDBG(dev, "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n", 2804 usbsts, usbintr, irq_sts); 2805 2806 if (!irq_sts) { 2807 VDBG(dev, "handle IRQ_NONE\n"); 2808 VDBG(dev, "<--- %s()\n", __func__); 2809 spin_unlock(&dev->lock); 2810 return IRQ_NONE; 2811 } 2812 2813 /* Write-Clear interrupt status bits */ 2814 writel(irq_sts, &dev->op_regs->usbsts); 2815 2816 /* resume from suspend */ 2817 portsc1 = readl(&dev->op_regs->portsc1); 2818 if (dev->usb_state == USB_STATE_SUSPENDED) 2819 if (!(portsc1 & PORTS_SUSP)) 2820 handle_bus_resume(dev); 2821 2822 /* USB interrupt */ 2823 if (irq_sts & STS_UI) { 2824 VDBG(dev, "USB interrupt\n"); 2825 2826 /* setup packet received from ep0 */ 2827 if (readl(&dev->op_regs->endptsetupstat) 2828 & EP0SETUPSTAT_MASK) { 2829 VDBG(dev, "USB SETUP packet received interrupt\n"); 2830 /* setup tripwire semaphone */ 2831 setup_tripwire(dev); 2832 handle_setup_packet(dev, &dev->local_setup_buff); 2833 } 2834 2835 /* USB transfer completion */ 2836 if (readl(&dev->op_regs->endptcomplete)) { 2837 VDBG(dev, "USB transfer completion interrupt\n"); 2838 handle_trans_complete(dev); 2839 } 2840 } 2841 2842 /* SOF received interrupt (for ISO transfer) */ 2843 if (irq_sts & STS_SRI) { 2844 /* VDBG(dev, "SOF received interrupt\n"); */ 2845 } 2846 2847 /* port change detect interrupt */ 2848 if (irq_sts & STS_PCI) { 2849 VDBG(dev, "port change detect interrupt\n"); 2850 handle_port_change(dev); 2851 } 2852 2853 /* suspend interrrupt */ 2854 if (irq_sts & STS_SLI) { 2855 VDBG(dev, "suspend interrupt\n"); 2856 handle_bus_suspend(dev); 2857 } 2858 2859 /* USB reset interrupt */ 2860 if (irq_sts & STS_URI) { 2861 VDBG(dev, "USB reset interrupt\n"); 2862 handle_usb_reset(dev); 2863 } 2864 2865 /* USB error or system error interrupt */ 2866 if (irq_sts & (STS_UEI | STS_SEI)) { 2867 WARNING(dev, "error IRQ, irq_sts: %x\n", irq_sts); 2868 } 2869 2870 spin_unlock(&dev->lock); 2871 2872 VDBG(dev, "<--- %s()\n", __func__); 2873 return IRQ_HANDLED; 2874} 2875 2876 2877/*-------------------------------------------------------------------------*/ 2878 2879/* release device structure */ 2880static void gadget_release(struct device *_dev) 2881{ 2882 struct langwell_udc *dev = the_controller; 2883 2884 DBG(dev, "---> %s()\n", __func__); 2885 2886 complete(dev->done); 2887 2888 DBG(dev, "<--- %s()\n", __func__); 2889 kfree(dev); 2890} 2891 2892 2893/* tear down the binding between this driver and the pci device */ 2894static void langwell_udc_remove(struct pci_dev *pdev) 2895{ 2896 struct langwell_udc *dev = the_controller; 2897 2898 DECLARE_COMPLETION(done); 2899 2900 BUG_ON(dev->driver); 2901 DBG(dev, "---> %s()\n", __func__); 2902 2903 dev->done = &done; 2904 2905 /* free memory allocated in probe */ 2906 if (dev->dtd_pool) 2907 dma_pool_destroy(dev->dtd_pool); 2908 2909 if (dev->status_req) { 2910 kfree(dev->status_req->req.buf); 2911 kfree(dev->status_req); 2912 } 2913 2914 if (dev->ep_dqh) 2915 dma_free_coherent(&pdev->dev, dev->ep_dqh_size, 2916 dev->ep_dqh, dev->ep_dqh_dma); 2917 2918 kfree(dev->ep); 2919 2920 /* diable IRQ handler */ 2921 if (dev->got_irq) 2922 free_irq(pdev->irq, dev); 2923 2924#ifndef OTG_TRANSCEIVER 2925 if (dev->cap_regs) 2926 iounmap(dev->cap_regs); 2927 2928 if (dev->region) 2929 release_mem_region(pci_resource_start(pdev, 0), 2930 pci_resource_len(pdev, 0)); 2931 2932 if (dev->enabled) 2933 pci_disable_device(pdev); 2934#else 2935 if (dev->transceiver) { 2936 otg_put_transceiver(dev->transceiver); 2937 dev->transceiver = NULL; 2938 dev->lotg = NULL; 2939 } 2940#endif 2941 2942 dev->cap_regs = NULL; 2943 2944 INFO(dev, "unbind\n"); 2945 DBG(dev, "<--- %s()\n", __func__); 2946 2947 device_unregister(&dev->gadget.dev); 2948 device_remove_file(&pdev->dev, &dev_attr_langwell_udc); 2949 2950#ifndef OTG_TRANSCEIVER 2951 pci_set_drvdata(pdev, NULL); 2952#endif 2953 2954 /* free dev, wait for the release() finished */ 2955 wait_for_completion(&done); 2956 2957 the_controller = NULL; 2958} 2959 2960 2961/* 2962 * wrap this driver around the specified device, but 2963 * don't respond over USB until a gadget driver binds to us. 2964 */ 2965static int langwell_udc_probe(struct pci_dev *pdev, 2966 const struct pci_device_id *id) 2967{ 2968 struct langwell_udc *dev; 2969#ifndef OTG_TRANSCEIVER 2970 unsigned long resource, len; 2971#endif 2972 void __iomem *base = NULL; 2973 size_t size; 2974 int retval; 2975 2976 if (the_controller) { 2977 dev_warn(&pdev->dev, "ignoring\n"); 2978 return -EBUSY; 2979 } 2980 2981 /* alloc, and start init */ 2982 dev = kzalloc(sizeof *dev, GFP_KERNEL); 2983 if (dev == NULL) { 2984 retval = -ENOMEM; 2985 goto error; 2986 } 2987 2988 /* initialize device spinlock */ 2989 spin_lock_init(&dev->lock); 2990 2991 dev->pdev = pdev; 2992 DBG(dev, "---> %s()\n", __func__); 2993 2994#ifdef OTG_TRANSCEIVER 2995 /* PCI device is already enabled by otg_transceiver driver */ 2996 dev->enabled = 1; 2997 2998 /* mem region and register base */ 2999 dev->region = 1; 3000 dev->transceiver = otg_get_transceiver(); 3001 dev->lotg = otg_to_langwell(dev->transceiver); 3002 base = dev->lotg->regs; 3003#else 3004 pci_set_drvdata(pdev, dev); 3005 3006 /* now all the pci goodies ... */ 3007 if (pci_enable_device(pdev) < 0) { 3008 retval = -ENODEV; 3009 goto error; 3010 } 3011 dev->enabled = 1; 3012 3013 /* control register: BAR 0 */ 3014 resource = pci_resource_start(pdev, 0); 3015 len = pci_resource_len(pdev, 0); 3016 if (!request_mem_region(resource, len, driver_name)) { 3017 ERROR(dev, "controller already in use\n"); 3018 retval = -EBUSY; 3019 goto error; 3020 } 3021 dev->region = 1; 3022 3023 base = ioremap_nocache(resource, len); 3024#endif 3025 if (base == NULL) { 3026 ERROR(dev, "can't map memory\n"); 3027 retval = -EFAULT; 3028 goto error; 3029 } 3030 3031 dev->cap_regs = (struct langwell_cap_regs __iomem *) base; 3032 VDBG(dev, "dev->cap_regs: %p\n", dev->cap_regs); 3033 dev->op_regs = (struct langwell_op_regs __iomem *) 3034 (base + OP_REG_OFFSET); 3035 VDBG(dev, "dev->op_regs: %p\n", dev->op_regs); 3036 3037 /* irq setup after old hardware is cleaned up */ 3038 if (!pdev->irq) { 3039 ERROR(dev, "No IRQ. Check PCI setup!\n"); 3040 retval = -ENODEV; 3041 goto error; 3042 } 3043 3044#ifndef OTG_TRANSCEIVER 3045 INFO(dev, "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n", 3046 pdev->irq, resource, len, base); 3047 /* enables bus-mastering for device dev */ 3048 pci_set_master(pdev); 3049 3050 if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED, 3051 driver_name, dev) != 0) { 3052 ERROR(dev, "request interrupt %d failed\n", pdev->irq); 3053 retval = -EBUSY; 3054 goto error; 3055 } 3056 dev->got_irq = 1; 3057#endif 3058 3059 /* set stopped bit */ 3060 dev->stopped = 1; 3061 3062 /* capabilities and endpoint number */ 3063 dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0; 3064 dev->dciversion = readw(&dev->cap_regs->dciversion); 3065 dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0; 3066 VDBG(dev, "dev->lpm: %d\n", dev->lpm); 3067 VDBG(dev, "dev->dciversion: 0x%04x\n", dev->dciversion); 3068 VDBG(dev, "dccparams: 0x%08x\n", readl(&dev->cap_regs->dccparams)); 3069 VDBG(dev, "dev->devcap: %d\n", dev->devcap); 3070 if (!dev->devcap) { 3071 ERROR(dev, "can't support device mode\n"); 3072 retval = -ENODEV; 3073 goto error; 3074 } 3075 3076 /* a pair of endpoints (out/in) for each address */ 3077 dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2; 3078 VDBG(dev, "dev->ep_max: %d\n", dev->ep_max); 3079 3080 /* allocate endpoints memory */ 3081 dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max, 3082 GFP_KERNEL); 3083 if (!dev->ep) { 3084 ERROR(dev, "allocate endpoints memory failed\n"); 3085 retval = -ENOMEM; 3086 goto error; 3087 } 3088 3089 /* allocate device dQH memory */ 3090 size = dev->ep_max * sizeof(struct langwell_dqh); 3091 VDBG(dev, "orig size = %d\n", size); 3092 if (size < DQH_ALIGNMENT) 3093 size = DQH_ALIGNMENT; 3094 else if ((size % DQH_ALIGNMENT) != 0) { 3095 size += DQH_ALIGNMENT + 1; 3096 size &= ~(DQH_ALIGNMENT - 1); 3097 } 3098 dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size, 3099 &dev->ep_dqh_dma, GFP_KERNEL); 3100 if (!dev->ep_dqh) { 3101 ERROR(dev, "allocate dQH memory failed\n"); 3102 retval = -ENOMEM; 3103 goto error; 3104 } 3105 dev->ep_dqh_size = size; 3106 VDBG(dev, "ep_dqh_size = %d\n", dev->ep_dqh_size); 3107 3108 /* initialize ep0 status request structure */ 3109 dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL); 3110 if (!dev->status_req) { 3111 ERROR(dev, "allocate status_req memory failed\n"); 3112 retval = -ENOMEM; 3113 goto error; 3114 } 3115 INIT_LIST_HEAD(&dev->status_req->queue); 3116 3117 /* allocate a small amount of memory to get valid address */ 3118 dev->status_req->req.buf = kmalloc(8, GFP_KERNEL); 3119 dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf); 3120 3121 dev->resume_state = USB_STATE_NOTATTACHED; 3122 dev->usb_state = USB_STATE_POWERED; 3123 dev->ep0_dir = USB_DIR_OUT; 3124 dev->remote_wakeup = 0; /* default to 0 on reset */ 3125 3126#ifndef OTG_TRANSCEIVER 3127 /* reset device controller */ 3128 langwell_udc_reset(dev); 3129#endif 3130 3131 /* initialize gadget structure */ 3132 dev->gadget.ops = &langwell_ops; /* usb_gadget_ops */ 3133 dev->gadget.ep0 = &dev->ep[0].ep; /* gadget ep0 */ 3134 INIT_LIST_HEAD(&dev->gadget.ep_list); /* ep_list */ 3135 dev->gadget.speed = USB_SPEED_UNKNOWN; /* speed */ 3136 dev->gadget.is_dualspeed = 1; /* support dual speed */ 3137#ifdef OTG_TRANSCEIVER 3138 dev->gadget.is_otg = 1; /* support otg mode */ 3139#endif 3140 3141 /* the "gadget" abstracts/virtualizes the controller */ 3142 dev_set_name(&dev->gadget.dev, "gadget"); 3143 dev->gadget.dev.parent = &pdev->dev; 3144 dev->gadget.dev.dma_mask = pdev->dev.dma_mask; 3145 dev->gadget.dev.release = gadget_release; 3146 dev->gadget.name = driver_name; /* gadget name */ 3147 3148 /* controller endpoints reinit */ 3149 eps_reinit(dev); 3150 3151#ifndef OTG_TRANSCEIVER 3152 /* reset ep0 dQH and endptctrl */ 3153 ep0_reset(dev); 3154#endif 3155 3156 /* create dTD dma_pool resource */ 3157 dev->dtd_pool = dma_pool_create("langwell_dtd", 3158 &dev->pdev->dev, 3159 sizeof(struct langwell_dtd), 3160 DTD_ALIGNMENT, 3161 DMA_BOUNDARY); 3162 3163 if (!dev->dtd_pool) { 3164 retval = -ENOMEM; 3165 goto error; 3166 } 3167 3168 /* done */ 3169 INFO(dev, "%s\n", driver_desc); 3170 INFO(dev, "irq %d, pci mem %p\n", pdev->irq, base); 3171 INFO(dev, "Driver version: " DRIVER_VERSION "\n"); 3172 INFO(dev, "Support (max) %d endpoints\n", dev->ep_max); 3173 INFO(dev, "Device interface version: 0x%04x\n", dev->dciversion); 3174 INFO(dev, "Controller mode: %s\n", dev->devcap ? "Device" : "Host"); 3175 INFO(dev, "Support USB LPM: %s\n", dev->lpm ? "Yes" : "No"); 3176 3177 VDBG(dev, "After langwell_udc_probe(), print all registers:\n"); 3178#ifdef VERBOSE 3179 print_all_registers(dev); 3180#endif 3181 3182 the_controller = dev; 3183 3184 retval = device_register(&dev->gadget.dev); 3185 if (retval) 3186 goto error; 3187 3188 retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc); 3189 if (retval) 3190 goto error; 3191 3192 VDBG(dev, "<--- %s()\n", __func__); 3193 return 0; 3194 3195error: 3196 if (dev) { 3197 DBG(dev, "<--- %s()\n", __func__); 3198 langwell_udc_remove(pdev); 3199 } 3200 3201 return retval; 3202} 3203 3204 3205/* device controller suspend */ 3206static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state) 3207{ 3208 struct langwell_udc *dev = the_controller; 3209 u32 devlc; 3210 3211 DBG(dev, "---> %s()\n", __func__); 3212 3213 /* disable interrupt and set controller to stop state */ 3214 langwell_udc_stop(dev); 3215 3216 /* diable IRQ handler */ 3217 if (dev->got_irq) 3218 free_irq(pdev->irq, dev); 3219 dev->got_irq = 0; 3220 3221 3222 /* save PCI state */ 3223 pci_save_state(pdev); 3224 3225 /* set device power state */ 3226 pci_set_power_state(pdev, PCI_D3hot); 3227 3228 /* enter PHY low power suspend */ 3229 devlc = readl(&dev->op_regs->devlc); 3230 VDBG(dev, "devlc = 0x%08x\n", devlc); 3231 devlc |= LPM_PHCD; 3232 writel(devlc, &dev->op_regs->devlc); 3233 3234 DBG(dev, "<--- %s()\n", __func__); 3235 return 0; 3236} 3237 3238 3239/* device controller resume */ 3240static int langwell_udc_resume(struct pci_dev *pdev) 3241{ 3242 struct langwell_udc *dev = the_controller; 3243 u32 devlc; 3244 3245 DBG(dev, "---> %s()\n", __func__); 3246 3247 /* exit PHY low power suspend */ 3248 devlc = readl(&dev->op_regs->devlc); 3249 VDBG(dev, "devlc = 0x%08x\n", devlc); 3250 devlc &= ~LPM_PHCD; 3251 writel(devlc, &dev->op_regs->devlc); 3252 3253 /* set device D0 power state */ 3254 pci_set_power_state(pdev, PCI_D0); 3255 3256 /* restore PCI state */ 3257 pci_restore_state(pdev); 3258 3259 /* enable IRQ handler */ 3260 if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED, driver_name, dev) 3261 != 0) { 3262 ERROR(dev, "request interrupt %d failed\n", pdev->irq); 3263 return -1; 3264 } 3265 dev->got_irq = 1; 3266 3267 /* reset and start controller to run state */ 3268 if (dev->stopped) { 3269 /* reset device controller */ 3270 langwell_udc_reset(dev); 3271 3272 /* reset ep0 dQH and endptctrl */ 3273 ep0_reset(dev); 3274 3275 /* start device if gadget is loaded */ 3276 if (dev->driver) 3277 langwell_udc_start(dev); 3278 } 3279 3280 /* reset USB status */ 3281 dev->usb_state = USB_STATE_ATTACHED; 3282 dev->ep0_state = WAIT_FOR_SETUP; 3283 dev->ep0_dir = USB_DIR_OUT; 3284 3285 DBG(dev, "<--- %s()\n", __func__); 3286 return 0; 3287} 3288 3289 3290/* pci driver shutdown */ 3291static void langwell_udc_shutdown(struct pci_dev *pdev) 3292{ 3293 struct langwell_udc *dev = the_controller; 3294 u32 usbmode; 3295 3296 DBG(dev, "---> %s()\n", __func__); 3297 3298 /* reset controller mode to IDLE */ 3299 usbmode = readl(&dev->op_regs->usbmode); 3300 DBG(dev, "usbmode = 0x%08x\n", usbmode); 3301 usbmode &= (~3 | MODE_IDLE); 3302 writel(usbmode, &dev->op_regs->usbmode); 3303 3304 DBG(dev, "<--- %s()\n", __func__); 3305} 3306 3307/*-------------------------------------------------------------------------*/ 3308 3309static const struct pci_device_id pci_ids[] = { { 3310 .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe), 3311 .class_mask = ~0, 3312 .vendor = 0x8086, 3313 .device = 0x0811, 3314 .subvendor = PCI_ANY_ID, 3315 .subdevice = PCI_ANY_ID, 3316}, { /* end: all zeroes */ } 3317}; 3318 3319 3320MODULE_DEVICE_TABLE(pci, pci_ids); 3321 3322 3323static struct pci_driver langwell_pci_driver = { 3324 .name = (char *) driver_name, 3325 .id_table = pci_ids, 3326 3327 .probe = langwell_udc_probe, 3328 .remove = langwell_udc_remove, 3329 3330 /* device controller suspend/resume */ 3331 .suspend = langwell_udc_suspend, 3332 .resume = langwell_udc_resume, 3333 3334 .shutdown = langwell_udc_shutdown, 3335}; 3336 3337 3338MODULE_DESCRIPTION(DRIVER_DESC); 3339MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>"); 3340MODULE_VERSION(DRIVER_VERSION); 3341MODULE_LICENSE("GPL"); 3342 3343 3344static int __init init(void) 3345{ 3346#ifdef OTG_TRANSCEIVER 3347 return langwell_register_peripheral(&langwell_pci_driver); 3348#else 3349 return pci_register_driver(&langwell_pci_driver); 3350#endif 3351} 3352module_init(init); 3353 3354 3355static void __exit cleanup(void) 3356{ 3357#ifdef OTG_TRANSCEIVER 3358 return langwell_unregister_peripheral(&langwell_pci_driver); 3359#else 3360 pci_unregister_driver(&langwell_pci_driver); 3361#endif 3362} 3363module_exit(cleanup); 3364